Lattice Semiconductor CrossLink-NX User manual

CrossLink-NX Evaluation Board
User Guide
FPGA-EB-02028-1.3
November 2020
Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02028-1.3
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely
with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been
subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.
Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 3
Contents
Acronyms in This Document.................................................................................................................................................5
1. Introduction..................................................................................................................................................................6
1.1. CrossLink-NX Evaluation Board ...........................................................................................................................6
1.2. Features ..............................................................................................................................................................6
1.3. CrossLink-NX Device..........................................................................................................................................11
1.4. Applying Power to the Board............................................................................................................................11
2. Jumpers and Test Connection ....................................................................................................................................12
3. Power Scheme............................................................................................................................................................14
4. Programming and I2C..................................................................................................................................................15
4.1. JTAG Download Interface..................................................................................................................................15
4.2. Alternate JTAG Download Interface..................................................................................................................15
4.3. JTAG to MSPI Pass-through Interface ...............................................................................................................16
4.4. SPI Flash Device Selection in Programmer........................................................................................................16
4.5. Other JTAG Configuration Pins..........................................................................................................................17
5. CrossLink-NX Clock Sources........................................................................................................................................18
6. Control Buses –I2C, UART, and SPI.............................................................................................................................19
6.1. I2C......................................................................................................................................................................19
6.2. UART Topology..................................................................................................................................................19
6.3. SPI Topology......................................................................................................................................................20
6.3.1. SPI Configuration ..........................................................................................................................................20
7. LEDs and Switches ......................................................................................................................................................21
7.1. DIP Switch .........................................................................................................................................................21
7.2. General Purpose Push Buttons .........................................................................................................................21
7.3. General Purpose LEDs .......................................................................................................................................22
7.4. Indicator LEDs....................................................................................................................................................22
8. Headers/Connectors and LIFCL-40 Device Ball Mapping............................................................................................23
8.1. FMC LPC Connector...........................................................................................................................................23
8.2. Parallel FMC Configuration Header...................................................................................................................25
8.3. Raspberry Pi Board GPIO Header......................................................................................................................25
8.4. Camera Connector ............................................................................................................................................26
8.5. D-PHY1 Header..................................................................................................................................................27
8.6. PMOD Header ...................................................................................................................................................28
8.7. JTAG Header......................................................................................................................................................28
8.8. Parallel Configuration Header...........................................................................................................................29
8.9. ADC Test Header ...............................................................................................................................................29
9. Software Requirements..............................................................................................................................................30
10. Storage and Handling .............................................................................................................................................30
11. Ordering Information..............................................................................................................................................30
Appendix A. CrossLink-NX Evaluation Board Schematics ...................................................................................................31
Appendix B. CrossLink-NX Evaluation Board Bill of Materials ............................................................................................45
Appendix C. Fast Configuration Issues................................................................................................................................53
Appendix D. Schematics Updates for ADC Test..................................................................................................................54
References..........................................................................................................................................................................55
Lattice Semiconductor Documents.................................................................................................................................55
TechnicalSupportAssistance ..............................................................................................................................................56
Revision History..................................................................................................................................................................57
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02028-1.3
Figures
Figure 1.1. Top View of CrossLink-NX Evaluation Board.......................................................................................................7
Figure 1.2. Bottom View of CrossLink-NX Evaluation Board.................................................................................................8
Figure 1.3. Silkscreen of CrossLink-NX Evaluation Board (Top .............................................................................................9
Figure 1.4. Silkscreen of CrossLink-NX Evaluation Board (Bottom) ....................................................................................10
Figure 2.1. Top View of CrossLink-NX Evaluation Board –Jumper Locations.....................................................................12
Figure 3.1. Board Power Scheme........................................................................................................................................14
Figure 4.1. Configuration and I2C Architecture...................................................................................................................15
Figure 4.2. SPI Flash Operation Dialog................................................................................................................................16
Figure 6.1. I2C Architecture and UART Options ..................................................................................................................19
Figure A.1. Title Page ..........................................................................................................................................................31
Figure A.2. Block Diagram...................................................................................................................................................32
Figure A.3. USB Interface....................................................................................................................................................33
Figure A.4. Camera Interface (DPHYs) ................................................................................................................................34
Figure A.5. Raspberry Pi and User I/O Interface.................................................................................................................35
Figure A.6. SERDES SMAs/Switches/FMC Control ..............................................................................................................36
Figure A.7. I2C LEDs and Push Buttons ...............................................................................................................................37
Figure A.8. PMODs..............................................................................................................................................................38
Figure A.9. Configuration and ADC .....................................................................................................................................39
Figure A.10. FMC-LPC..........................................................................................................................................................40
Figure A.11. Power CSI and Banks ......................................................................................................................................41
Figure A.12. Power Decoupling...........................................................................................................................................42
Figure A.13. Power Regulators ...........................................................................................................................................43
Figure A.14. Power Block Diagram......................................................................................................................................44
Tables
Table 2.1. Jumper Table......................................................................................................................................................13
Table 3.1. CrossLink-NX VCCIO Supply Options ..................................................................................................................14
Table 4.1. JTAG Connections...............................................................................................................................................15
Table 4.2. Other JTAG Signals .............................................................................................................................................17
Table 5.1. Clock Sources .....................................................................................................................................................18
Table 6.1. I2C Global Bus Connections................................................................................................................................19
Table 6.2. CrossLink-NX SPI Connections............................................................................................................................20
Table 7.1. Eight-Position DIP Switch Signals .......................................................................................................................21
Table 7.2. Push Button Switch Signals ................................................................................................................................21
Table 7.3. General Purpose LED Signals..............................................................................................................................22
Table 7.4. Various LED Signals ............................................................................................................................................22
Table 8.1. FMC LPC Header Pin Connections......................................................................................................................23
Table 8.2. Parallel FMC Configuration J27 Pin Connections ...............................................................................................25
Table 8.3. Raspberry Pi JP8 Header Pin Connections..........................................................................................................25
Table 8.4. Camera CN1 Connector Pin Connections...........................................................................................................26
Table 8.5. D-PHY1 J6 Header Pin Connections....................................................................................................................27
Table 8.6. J17, J18 and J19 Header Pin Connections ..........................................................................................................28
Table 8.7. J1 Header Pin Connections.................................................................................................................................28
Table 8.8. J27 Header Pin Connections...............................................................................................................................29
Table 8.9. J26 Header Pin Connections...............................................................................................................................29
Table 11.1. Ordering Information.......................................................................................................................................30
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
caBGA
Chip Array Ball Grid Array
CMOS
Complementary Metal-Oxide Semiconductor
DIP
Dual Inline Package
DNI
Do Not Install
ESD
Electro Static Discharge
FMC LPC
FPGA Mezzanine Low Pin Count Connector
FPGA
Field Programmable Logic Array
FTDI
Future Technology Devices International
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
JTAG
Joint Test Action Group
LVDS
Low-Voltage Differential Signaling
PMOD
Peripheral Module
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver Transmitter
USB
Universal Serial Bus
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02028-1.3
1. Introduction
The Lattice Semiconductor CrossLink™-NX Evaluation Board allows designers to investigate and experiment with the
features of the CrossLink-NX Field Programmable Gate Array (FPGA). The features of the CrossLink-NX Evaluation Board
can assist engineers with the rapid prototyping and testing of their specific designs.
The CrossLink-NX Evaluation Board is part of the CrossLink-NX Evaluation Kit, which includes the following:
CrossLink-NX Evaluation Board pre-loaded with the shipping demo design
12 V AC/DC power adapter and international plug adapters
Lattice Radiant® Software license information
USB-A to USB-B (Mini) Cable for programming FPGA through a PC
Quick Start Guide
The contents of this user guide include top-level functional descriptions of the various portions of the development
board, descriptions of the on-board headers, diodes and switches and a complete set of schematics.
1.1. CrossLink-NX Evaluation Board
The CrossLink-NX Evaluation Board features the CrossLink-NX FPGA in the 400-ball caBGA package (LIFCL-40-9BG400C)
w the ability to expand the usability of the CrossLink-NX with Raspberry Pi, PMOD, FMC LPC connector, along with
access to PCIe channel. 118 wide range I/O and 37 high speed differential pairs are available for user-defined
applications.
Figure 1.1 shows the top view of the CrossLink-NX Evaluation Board. Figure 1.2 shows the bottom view of the board.
Figure 2.1 shows the jumper locations.
1.2. Features
The CrossLink-NX Evaluation Board includes the following features:
CrossLink-NX FPGA (LIFCL-40-9BG400C)
General Purpose Input/Output (GPIO) breakout with Raspberry Pi, PMOD, and FMC connector
MIPI CSI-2 Camera connector and D-PHY connector
118 wide range I/O and 37 high speed differential pair I/O with on board termination
x1 Gen2 PCIe interface
USB-B connection for device programming and Inter-Integrated Circuit (I2C) utility
On-board Boot Flash –128 Mbit Serial Peripheral Interface (SPI) Flash, with Quad read feature
Eight input DIP switches, four push buttons, three status LEDs and 14 LEDs for demo purposes
Lattice Radiant®Software programming support
Multiple reference clock sources
Potentiometer for ADC test
Caution:
The CrossLink-NX Evaluation Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 7
Power
Status
LEDs
(D19-D27)
Status
LEDs
User
Switches
(SW1)
Raspberry
PI Conn
(JP5)
Prototype
Area Potentiometer
(U8)
ADC Test
Header
(J26)
FMC Parallel
Config
Header (J27)
FPGA
Mezzanine
Carrier Card
Conn (U9)
Push Buttons
(SW5-SW2)
Output LEDs
(D16-D3)
PMOD
Conn
(J17-J19)
JTAG Header(J1)
Parallel Config
Header (J20)
LIFCL-40
Device (U3)
SPI Flash Memory (U6)
FTDI Interface Chip (U1)
Mini USB
12 V
Power Input
Camera
Conn
(CN1)
xD-Phy 1
Header (J6) Serdes Test SMA Conn
(J11, J15, J12, J16, J10 and J14)
Figure 1.1. Top View of CrossLink-NX Evaluation Board
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02028-1.3
200 MHZ OSC for Serdes (U5) 125 MHZ OSC for Serdes (U4)
Figure 1.2. Bottom View of CrossLink-NX Evaluation Board
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.39
Figure 1.3. Silkscreen of CrossLink-NX Evaluation Board
D27
D25
R119
R126
D23
R125
R117
D26
D24
R118
D21
D22
R115
D19
D20
R114
JP5
JP3
JP4
L15
SW1
D32
D31
C141
L14
R121
D30
R153
R152
J40
J39
C154
J41
C145 D29
C144
C151
C152
TP_V5P0
L17
D36
C155
D35
R162
J42
TP_V3P3
C142
C143 R160
R155
R159
C146
C147
C149
R151
U15
R154
R156
R157
TP_V1P8 J43
D18
J33
D17
D1
R76
X2
F1
D34 C170
R163
C159
U16 D33
C158
C165
L16
C166
TP_VCC_CORE_V1P0
R145
C135
R140
TP12
TP10
TP_V2P8
TP_V1P2
R24
CN1
C157C156
C163
R165
R170
R168
C161
R161
R150
R169
R164 FB8 J36 C137
U14
R141
C167 D16
R187
C160
R166
C164 J35
J34
TP_VCCIO3
TP_VCCIO4
TP_VCCIO5
R77
C76
D15
R186
TP13
TP_V1P0_LDO
R80
D13
D14
SW4
SW5
R185
R149
FB7
J32
TP_VCCIO7
J6
D12 R184
J31 FB6
TP_VCCIO6
C39
R36
J3
J5
J4
C32
L4 L8 L6
J13
J14
R72
C63 C61
D11
D10
R67
R69TP7
R182
R183
C134
R40 R35
R39
C68
U3
C133
C122
R27
R28
R30
C26 C30
R70 SW2
D8
D9
R180
R181
J38
R31
R66
C48
L10
R29
C56
L11
J10
D4 R174
R175
TP6
D7
R178
R179
R49
R52
R51
R48
R47
R56 C57
C49 R62
R50
D3
C102
R68
C105
D6
SW3 D5
R176
R177
JP8
JP6
JP7
J23
R41
R46
R65
R54
C55 C54
R64R61R59
R63
R60
C62
U10
R71
TP8
C88
R102
C64
R37
R74
R73
R75
TP_VCCIO0
C53 C50
TP_V1P0_VCCSD
R57
R58
R55
TP_V1P8_VCCPLLSD
TP_V1P8_VCCAUXSD
J16
C100
L13
U9
J30
C139
R143
TP_V1P8_LDO
RN1
R38
R111
R109
C99
C97 R110
R112
J29
TP5
R148
U13
C136
J37
J28
J7
J8 FB2
FB1
J9
FB3
TP2
J12
TP_VADJ
C104
C103
C101
R108
C98
C82
U7 J25
L12
TP_VCCIO1 TP_VCCIO2
TP4 TP3
U6
TP9
R21
J44
R18
R20
R17
R15
TP1
J21
J22
C89
J24
J20
R19
J27
R99
C90
R98
U2
U1
J15
J26
J1
C16 R9
C17
X1
JP1
U8
D2
J2
J19
J18
J17
JP2
J11
H40
C40
49
48
33
32
BOARD EDGE
64
16
17
BRD EDGE
1
30
ON
16
15
H1
C1
JTAG
1
RXDP
POT
PMOD2
1
PMOD1
1
PMOD0
1
USB
MINI
1
ADC
1
FMC CONFIG
1
RXDN
FLASH/FPGA
1
TXDP
PB1
TXDN
CrossLink-NX Evaluation Board
LIFCL-40-EVN REV B
Copyright C 2019
PROG
MIPI CSI-2
FPGA MEZZANINE CARD
D-PHY 1
1
CLKN
GSRN
11
CLKP
MADE IN USA
DEMO LEDS
CROSSLINK NX
PBO
SERDES
1
39
1
40
RASPBERRY PI AND USER I/O
1.8V
3.3V
2
POWER LEDS
PROTOTYPE AREA
DEMO SW
1.0V
1.0VL
1.8VL
1.2V
2.8V
1.8V
3.3V
12V
5V
3
GND
LEDS
STATUS
1
RPI/USER 1.8V/3.3V
INITN
DONE
ACT
POWER
2
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02028-1.3
Figure 1.4. Silkscreen of CrossLink-NX Evaluation Board (Bottom)
R122
R123
R132
R124
R113
C38
C37
R133
Q6 Q3 Q2 Q5 Q4
C148
C150
R81
C153
R79
R158
C168 Q1
R14
C111
D28
C169
R82R83
C109
C110
R116
U11
U12
C21
R23
R120 C20
R100
C162
R167 C138
C112 R25
R26
C19 C18
R101
R136 C23
C22
C24
R135 C94
R134
R130
C40
R131
R32
L5
R34
L9
L7
R33
C27
C28
C36
C34
C93
C92
C42
C127
C41
C35
C31
C114C71 C70
C33
C132
R138
C91
C69
C123
C121
C95 C119
C129
C96
C131
C130
C120
C126
C116 C115
R78
C118 C128
C124
C117
C113
C25C29
C47
R43
C107
C106
C85
C59
C65C125
C66
C75
C45
R45
C44
C46
U4
U5
R94
C58
C108
C86
C60
C43
C52
C51
R171
R107 R106 FB4
C87
R105
R104
R103
C74
R129 C140
R144
R137
R44
R42
R53
R128
R147
R146
R142
R89
R91
R85
FB5
R127
R93
C84
C83
R92R86
C81 C80 R84
R88
R22
C78
C77
R90 R87 C79 C15
C5
C14
C2 C11
R172
C4
R97
R95
R10
R11
R12
R16
R13
C1
L3
L1
R7
R8
R173
C3
R96
R4
R1
R3
C13
C10 C9
C6
C7
C12
R6
R5
R2
C73 C72 C67
C8
L2
NOV 2019
A
A
305-PD-19-0943
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 11
1.3. CrossLink-NX Device
The CrossLink-NX Evaluation Board features the CrossLink-NX device in a 400-ball caBGA package, also referred to as
LIFCL-40-9BG400C. For more information on the capabilities of CrossLink-NX, see CrossLink-NX Family Data Sheet
(FPGA-DS-02049).
1.4. Applying Power to the Board
Power LEDs light after applying 12 V power to CrossLink-NX Evaluation Board to indicate the board is functioning. An
Early I/O demo design is programmed into on-board boot flash as the default pattern. With this pattern, LED0 (D3)
(mapped an early I/O) immediately turns on as soon as 12 V power is supplied to the board. After about two seconds,
as configuration is successfully completed, DONE LED (D18) lights, and LED2 (D5) and LED3 (D6) light alternately in a
heartbeat pattern.
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02028-1.3
2. Jumpers and Test Connection
FTDI Reset
(JP1)
FTDI OSC
Reset (JP2)
Raspberry Pi
Conn Power
(JP3 and JP4)
Serdes Test
125 MHz/200 MHz
Ref CLK Selection
(J13)
ADC Test
Selection (J21,
J22, and J24-J26)
FMC VADJ 1.8 V,
2.5 V, and 3.3 V
Selection (J6-J8)
VCCIO0 Power
Selection (J44)
VCCIO6 Power
Selection (J33)
Current
Measurement 2 Pin
Header (J3-J5, J32,
and J40)
Current Measurement
2 Pin Header
(J7-J9)
Current
Measurement 2 Pin
Header (J28-J30,
and J37)
Current
Measurement 2 Pin
Header (J34-J36,
J41-J43, J23, J31,
and J38)
Figure 2.1. Top View of CrossLink-NX Evaluation Board –Jumper Locations
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 13
Table 2.1. Jumper Table
Part
Description
Setting
JP1
FTDI Reset Jumper
Default Open (active FTDI)/Short (reset FTDI)
JP2
FTDI Oscillator Jumper
Default Short (12 MHz OSC connected)/Open (12 MHz OSC
unconnected)
JP3
Raspberry Pi Connector Power
Default Open (Raspberry Pi self-power)/Short (3.3v applies
Paspberry Pi connector )
JP4
Raspberry Pi Connector Power
Default Open (Raspberry Pi self-power)/Short (5.0v applies
Paspberry Pi connector )
JP6, JP7, and
JP8
VADJ Selection Jumper For FMC LPC
Carrier Connector
NO Jumper -> 1.5 V (JP6, JP7, and JP8 open)
Only JP8* Short -> 1.8 V
Only JP7* Short -> 2.5 V
Only JP6* Short -> 3.3 V
J13
125 MHz / 200 MHz OSC Selection
Jumper
Default 1–2 (125 MHz)/2-3 (200 MHz)
J21
ADC_REFP0 Selection Jumper
Default 1–2 (V1P8_ADC_VREF)/2-3 (J26 connector Input Voltage)
J22
ADC_REFP1 Selection Jumper
Default 1–2 (V1P8_ADC_VREF)/2-3 (J26 connector Input Voltage)
J24
ADC_DN0 Selection Jumper
Default 1-2 (Disable), 2-3 (J26 connector)
To select POT, wire jumper: J24-1 to J25-2 and J24-2 to J25-1.
J25
ADC_DP0 Selection Jumper
J44
VCCIO0 Supply Voltage Selection
Jumper
Default 1–2 (3.3 V)/2-3 (1.8 V)
J33
VCCIO6 Supply Voltage Selection
Jumper
Default 1–2 (3.3 V)/2-3 (1.8 V)
J3,J4,J5,J7,J8,J9,
J23,J28,J29,J30,
J31,J32,J34,J35,
J36,J37,J38,J40,
J41,J42, and J43
Current Measurement 2 Pin Header
—
*Note: Only one jumper at a time. Otherwise, damage could occur.
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02028-1.3
3. Power Scheme
The CrossLink-NX Evaluation Board has most of its power supplied by onboard regulators powered by an external 12 V
power. Refer to Appendix A. CrossLink-NX Evaluation Board Schematics to see the details of these power supply
options. Figure 3.1 shows the high-level power supply architecture of the board. Table shows the voltage options
available for the various VCCIO supplies.
V1P8_DPHY
VCCIO0
VCCIO5
VCCIO1
V1P8_VCCADC18
VCCIO4
V1P0_VCCSD0
V1P8_VCCPLLSD0
V1P8_LDO V1P0_LDO
V1P8
VCCIO3 ADC
V1P0_LDO
V3P3/V1P8
V3P3
V3P3
V3P3/
V1P8
V3P3
V1P8 V1P8
Serde s
V1P0_DPHY
VCCIO7
VCCIO6
VCCIO2
V1P8_LDO
V1P8_LDO V1P8_LDO VCC_CORE_V1P0
V1P8_VCCAUX VCC
+12.0 V
SW (U15) SW (U16)
V1P0_LDO
V1P2
+1.0 V
VCC_CORE_1P0
+1.0 V
LDO (U14)
LDO (U11)
Camera (CN1)
V1P8
+1.8 V
V2P8
+1.2 V
+2.8 V
LDO (U12)
V1P8_LDO
+1.8 V
LDO (U13)
FTDI (U1)
Raspberry (JP5)
V5P0
+5.0 V
V3P3
+3.3 V
LIFCL-40
(U3)
V3P3
12 V
3.3 V
VADJ
FPGA Mezza ni ne
Card (FMC) Low Pin
Count (LPC)
(U9)
SW-3 A( U 10)
1. 5V/ 1.8 V /2 . 5V / 3.3 V
Figure 3.1. Board Power Scheme
Table 3.1. CrossLink-NX VCCIO Supply Options
VCCIO Bank
Selection
V3P3
V1P8
VCCIO0
J44 Connector
Default
Selectable
VCCIO1
—
Fixed
N/A
VCCIO2
—
Fixed
N/A
VCCIO3
—
N/A
Fixed
VCCIO4
—
N/A
Fixed
VCCIO5
—
N/A
Fixed
VCCIO6
J42 Connector
Default
Selectable
VCCIO7
—
Fixed
N/A
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 15
4. Programming and I2C
The JTAG/SPI programming architecture and I2C interface of the CrossLink-NX Evaluation Board is shown in Figure 4.1.
Mini USB
(J2)
FT2232H
(U1)
rst#
UART (DNI2)
I2C
JTAG
LIFCL
(U3)
JTAG Header (J1) DNI1Raspberry Pi (JP5)
Raspberry Pi (JP5)
DNI3
SPI
Flash
(U6)
SPI Header
(J20)
Port 0
Port 1
JP1Notes:
1. Via DNI 0 resistors R35, R36, R37 and R38
2. Via DNI 0 resistors R15 and R17
3. Via DNI 0 resistors R39 and R40
Figure 4.1. Configuration and I2C Architecture
4.1. JTAG Download Interface
The CrossLink-NX Evaluation Board has a built-in download controller for programming the CrossLink-NX device. It uses
an FT2232H Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in download
cable, connect the USB cable from a PC with Radiant Programmer tool installed to the mini USB connector on the board
(J2). A mini USB to USB-A cable is included in the CrossLink-NX Evaluation Kit. The USB hub on the PC detects the cable
of the USB function on Port 0, making the built-in cable available for use with the Radiant programming software.
4.2. Alternate JTAG Download Interface
J1 is an 8-pin standalone JTAG header used with an external Lattice download cable that is available separately, when
the FTDI part is disabled from the JTAG chain after setting the JP1 jumper. A USB download cable can be attached to
the board using J1 to interface with the CrossLink-NX. For details on the connection between the USB download cable
and J1, refer to Programming Cable User’s Guide (FPGA-UG-02042).
J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path
through the Raspberry Pi header (JP5) for customer applications. This is done by connecting the JP5 header to the J1
header through some onboard resistors. The JTAG connections between J1 and JP5 are listed in Table .
Table 4.1. JTAG Connections
J1 Pin
Number
JTAG Signal
Name
CrossLink-NX Ball
Location for JTAG
Raspberry Pi Header
(JP8) Pin Number
J1 to JP5 Isolation
(Assembly)
Raspberry Pi GPIO
1
VCCIO1
—
—
—
—
2
TDO
F19
10
R36 (DNI)
IO15
3
TDI
F17
11
R38 (DNI)
IO17
4
—
—
—
—
—
5
—
—
—
—
—
6
TMS
F15
12
R37 (DNI)
IO18
7
GND
—
—
—
—
8
TCK
G18
8
R35 (DNI)
IO14
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02028-1.3
4.3. JTAG to MSPI Pass-through Interface
The download controller can also access the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be
erased, programmed, and read with Radiant Programmer.
4.4. SPI Flash Device Selection in Programmer
The Flash device on this board is a Macronix MX25L12833F.
Figure 4.2. SPI Flash Operation Dialog
You may proceed with the Flash device programming by following the procedure in CrossLink-NX sysCONFIG Usage
Guide (FPGA-TN-02099).
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 17
4.5. Other JTAG Configuration Pins
The CrossLink-NX Evaluation Board provides test points for other JTAG configuration pins as shown in Table .
Table 4.2. Other JTAG Signals
Signal Name
CrossLink-NX Ball Location
Test Point
Push Button
PROGRAMN
E11
—
SW5
INITN
D11
TP10
—
DONE
D12
TP12
—
For more information on CrossLink-NX JTAG and SPI programming, refer to CrossLink-NX sysCONFIG Usage Guide
(FPGA-TN-02099).
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02028-1.3
5. CrossLink-NX Clock Sources
The CrossLink-NX Evaluation Board has three options for the CrossLink-NX clock sources:
Table 5.1. Clock Sources
Clock Frequency
Signal Name
CrossLink-NX Ball Location
Clock Source
Comments
12 MHz
12 MHz
L13
U1
JP2 installed. JP1 removed.
200 MHz
200 MHz/200 MHz_n
C12/ C11
U5
Insert R65 & R66, remove R54 & R56
125 MHz
125 MHz/125 MHz_n
C12/ C11
U4
Insert R54 & R56, remove R65 & R66
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.3 19
6. Control Buses –I2C, UART, and SPI
This section describes the topology of the various configuration and communication buses.
6.1. I2C
The CrossLink-NX Evaluation Board uses the I2C bus to support CrossLink-NX configuration, and optionally to support
Raspberry Pi communication. The global I2C bus has the signal names SDA and SCL and they are routed close to
Raspberry Pi header as shown in Figure 4.1 and in more detail in Figure 6.1.
Raspberry Pi connector is connected to a dedicated CrossLink-NX GPIO bank with a direct local I2C bus. Local I2C bus can
optionally connect to the global I2C bus through resistors. The local I2C connections are summarized in Table .
FTDI 2232H (UI)
BDBUS0
BDBUS1/2 SDA
SCL
Instantiated I2C
Resistors (R18, R19)
RASP_ID_SD
RASP_ID_SC
Bank6 (U3)
Bank1 (U3)
SDA
SCL
TXD_UART
RXD_UART
Figure 6.1. I2C Architecture and UART Options
Table 6.1. I2C Global Bus Connections
CrossLink-NX Bank
Component
(Reference)
Header Pin
CrossLink-NX -
85 Ball
Local Signal Name (Global I2C Signal)
Resistor
6
Raspberry Pi
header (JP5)
27
M7
RASP_ID_SD (SDA)
R40 (DNI)
28
M4
RASP_ID_SC (SCL)
R39 (DNI)
6.2. UART Topology
The board provides support for UART configuration by providing an uninstalled connection between the FTDI and
CrossLink-NX. Two 0 Ω resistors (R16 and R17) can be installed to connect Port 1 to two general purpose I/O (PR8A/F16
and PR10A/F18) in Bank 6 as shown in Figure 6.1.
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.

CrossLink-NX Evaluation Board
User Guide
© 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02028-1.3
6.3. SPI Topology
6.3.1. SPI Configuration
One of the major functions of SPI connections on the board is to support CrossLink-NX configuration from the SPI Flash
or the Parallel Configuration Header. The CrossLink-NX Evaluation Board can support both Master SPI (MSPI) and Slave
SPI (SSPI) modes for CrossLink-NX configuration.
Table 6.2. CrossLink-NX SPI Connections
Signal Name
CrossLink-NX Ball
Parallel Configuration Header Pin
SPI_MCLK
E12
12
DQ0_MOSI
D13
5
DQ1_MISO
D15
7
CSSPIN
E13
8
DQ2
D14
11
DQ3
D16
9
MCSNO
E16
3
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.