Lattice Semiconductor LatticeECP2M PCI Express x4 User manual

February 2008
Revision: EB22_01.6
LatticeECP2M™ PCI Express x4 Evaluation Board
User’s Guide

2
LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Introduction
This user’s guide describes the LatticeECP2M PCI Express x4 Evaluation Board featuring the LatticeECP2M
FPGA device. The evaluation board has been designed to support the LatticeECP2M35 device and the
LatticeECP2M50 device. Different versions of the evaluation board are available that contain either the
LatticeECP2M35 device or the LatticeECP2M50 device. The stand-alone evaluation PCB provides a functional
platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to PCI
Express protocols.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. Please note that boards populated with the LatticeECP2M-35 device have all avail-
able SERDES channels routed to the PCI Express, and in this case the SMAs are not active. The SMAs are avail-
able in larger density LatticeECP2M FPGAs fitting the same footprint, but with additional SERDES channels. The
board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for
single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete user evaluation of the LatticeECP2M device.
This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the
LatticeECP2M FPGA.
Figure 1. LatticeECP2M PCI Express x4 Evaluation Board

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Board Features
• SERDES interface to x4 PCI Express edge fingers
• DDR2 memory device
• SERDES high-speed interface SMA test points (active with LatticeECP2M-50 and larger FPGAs only) and clock
connections
• Power connections and power sources
• ispVM
®
programming support
• On-board and external reference clock sources
• Interchangeable clock oscillators
• On-board reference clock management using Lattice ispClock™ devices
– ORCAstra demonstration software interface via standard ispVM JTAG connection
– Various high-speed layout structures
• User defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 1 shows the functional partitioning of the board.
Figure 2. LatticeECP2M PCI Express x4 Evaluation Board
LatticeECP2Mxx
672 fpBGA
ispVM/JTAG
8LVDS Paired SMAs for
Demo of LVDS I/O
Performance
BNC Connector
DDR2
Memory
Component
General Purpose
I/Os -
Switches/LEDs
SMAs for a Single
1 Quad of 3G
(SRIO x1, x4),
XAUI
4 SMAs for External
Clock Sources
Oscillators
PCI Express (x4)
Edge Fingers
FPGA Loader
SPI Flash Device

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Figure 3. LatticeECP2M PCI Express x4 Evaluation Board,Top View
Additional Resources
For additional information and resources related to this board, including updated documentation and software
demos, please see the Lattice web site at: www.latticesemi.com/boards, and navigate to the appropriate page for
this board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
LatticeECP2M Device
This board features a LatticeECP2M FPGA with a 1.2V core supply. It can accommodate all pin compatible
LatticeECP2M devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP2M Family Data Sheet on the Lattice web site at www.latticesemi.com.
Note: The connections referenced in this document refer to the LFE2M35E-FF672 device. Available I/Os and asso-
ciated sysIO™ banks may differ for other densities within this device family. For example, only the LFE2M50E-
FF672 device allows full use of the high speed SERDES test SMAs and SMPTE BNC connections.
Applying Power to the Board
The LatticeECP2M PCI Express x4 Evaluation Board is ready to power on. The board can be supplied with power
from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a bench top sup-
ply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a
host board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J1 and plug the wall transformer into an AC wall outlet.
Power Supplies
(see Appendix A, Figure 7)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided for use with a bench top supply adjusted
to provide a nominal 12V DC.

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs
to indicate power GOOD status of the intermediate supplies
Table 1. Board Power Supply Fuses (see Appendix A, Figure 6)
Table 2. Board Power Supply Indicators (see Appendix A, Figure 6)
External power can be alternatively connected rather than the wall transformer power pack.
Table 3. Board Supply Disconnects (see Appendix A, Figure 6)
PCI Express Power Interface
Power can be sourced to the board via the PCB edge finger (CN1). This interface allows the user to provide power
from a PCI Express host board.
Programming/FPGA Configuration
(see Appendix A, Figure 8)
A programming header is provided on the evaluation board, providing access to the LatticeECP2M JTAG port.
ispVM Download Interface
J8 is an 10-pin JTAG connector, providing access to the LatticeECP2M JTAG port. It can be used in conjunction
with the ispVM System software and Lattice USB download cable to program and control the device.
F1 1.2V Core Fuse
F2 1.5V Fuse
F3 3.3V Fuse
F4 1.2V Fuse
F5 2.5V Fuse
F6 1.8V Fuse
D1 2.5V Source Good Indicator
D2 3.3V Source Good Indicator
D3 12V Input Good Indicator
D4 1.2V VCC Core Source Good Indicator
D5 1.5V Source Good Indicator
D6 1.8V Source Good Indicator
D7 1.2V Source Good Indicator
TB1 Screw Terminal for 12V DC Pin1 (Square PCB Pad) -> +12V DC Pin2 -> Ground

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Table 4. ispVM JTAG Connector (see Appendix A, Figure 8)
Programming Daisy Chain
This board includes two Lattice programmable devices that can be programmed in a daisy chain. A jumper setting
of J105 controls the chain. Both devices are in the programming chain from the JTAG header, J8, with jumpers on
J105 across Pins{1-2}, Pins{3-4}, and Pins{5-6}. Jumpers on J10 across Pins{1-2} and Pins{3-4} are also required
for both devices to be in the chain.
If the user desires to only program U1, J105 requires jumpers across Pins{1-2} and Pins{4-6}. J10 requires only a
jumper across Pins {1-2}.
Download Procedures
Requirements:
• PC with ispVM System v.16.1.2 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). The latest
ispVM System software can be downloaded from the Lattice web site at www.latticesemi.com/ispvm.
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (HW-DLN-3C, HW-USBN-2A, or equivalent)
JTAG Download
The LatticeECP2M device can be configured easily via its JTAG port. The device is SRAM-based; it must remain
powered on to retain its configuration when programmed in this fashion.
1. Connect the ispDOWNLOAD Cable to the appropriate header. J8 is used for the 1x10 cable.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the isp-
DOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2M FPGA device
and render the board inoperable.
2. Connect the LatticeECP2M Evaluation Board to the appropriate power sources and power up board.
3. Start the ispVM System software.
Pin 1 VCC
Pin 2 TDO
Pin 3 TDI
Pin 4 PROGRAMN
Pin 5 NC
Pin 6 TMS
Pin 7 GND
Pin 8 TCK
Pin 9 DONE
Pin 10 INITN

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
4. Press the SCAN button located in the toolbar. The LatticeECP2M device should be automatically detected.
5. Double-click the device to open the device information dialog. In the device information dialog, click the
Browse button located under Data File . Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
6. Click the green GO button. This will begin the download process into the device. Upon successful download,
the device will be operational.

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Configuration Status Indicators
(see Appendix A, Figure 8)
These LEDs indicate the status of configuration to the FPGA.
• D8 (RED) illuminated, this indicates that the programming was aborted or reinitialized driving the INITNoutput
low.
• D11 (GREEN) is illuminated, this indicates the successful completion of configuration by releasing the open col-
lector DONE output pin.
• D12 (GREEN) will flash indicating TDI activity.
• D10 (RED) illuminated, this indicates that PROGRAMNis low.
• D9 (RED) illuminated, this indicates that GSRNis low.
PROGRAMN and GSRN
(see Appendix A, Figure 8)
These push-button switches assert/de-assert the logic levels on the PROGRAMN(SW3) and GSRN(SW2).
Depressing the button drives a logic level “0” to the device.
CFG [2:0]
(see Appendix A, Figure 8)
The FPGA CFG pins are set on the board for a particular programming mode via the SW1 DIP switch. JTAG pro-
gramming is independent of the MODE pins and is always available to the user
On-Board Flash Memory
(see Appendix A, Figure 8)
Two memory devices (U10 and U12) are on-board for non-volatile configuration memory storage. These two
devices occupy the same Flash slot on the board. U10 can be populated with an 8M or smaller 8-pin SOIC device.
U12 can be used in place of U10 with a 16-pin TSSOP 64M Flash device. U15 always supplies as an 8M Flash
device. J11 is used to control the selection of the Flash memory to be accessed.
FPGA Clock Management
(see Appendix A, Figure 12)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-
erated from either input provided from SMAs (see table below) or from crystal oscillators (Y1 and Y2). Y1 is sock-
eted for interchangeability and Y2 is a 100MHz surface-mounted oscillator which is fanned out around U1 for
reference clocks with a fan-out buffer IC.
Y1 can be a 4-pin DIP type oscillator like the Connor-infield XO-400 series.
Both of these input clock sources are routed through the Lattice ispClock5620A devices (U2). These programmable
clock management devices allow for clock synthesis and buffering.
U2 is a Lattice ispClock5620A in-system programmable analog circuit that allows designers to implement clock dis-
tribution networks supporting multiple synchronized output frequencies using a single integrated circuit. By inte-
grating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620A can derive up to five
SMA Signal
J35 U2 Reference + Input
J36 U2 Reference - Input

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
separate output frequencies from a single input reference frequency. PAC-Designer
®
software (available from the
Lattice web site at www.latticesemi.com/pacdesigner) is used to program the ispClock features.
ispClock supports reference clocks in the range of 10 to 320 MHz. The duty cycle of the clock source need not be
50%; the only requirement is that both the HIGH and LOW times of this signal must be 1.25 ns or longer. The fol-
lowing standards are supported with either minimal or no external components: LVTTL, LVCMOS, SSTL2, SSTL3,
HSTL, LVDS and LVPECL.
When the ispClock5620A is in a LOCKED state, the LOCK output pin goes LOW. The LOCKNpins are connected
to amber LED D13 and will illuminate when the LOCKNpin goes low. The lock detector has two operating modes:
phase lock mode and frequency lock mode. In phase lock mode, the LOCK signal is asserted if the phases of the
reference and feedback signals match, whereas in frequency lock mode the LOCK signal is asserted when the fre-
quencies of the feedback and reference signals match.
U2 is controlled by SW4 or from a predefined connection to U1 (LatticeECP2M). The DIP switch controls the isp-
Clock device. The reference clock selection and device reset is controlled using the switches. The switches control-
ling the ispClock outputs can be synchronously controlled by the SGATE output on a bank-by-bank basis or tri-
stated on an output-by-output basis using the OEXb and OEYb inputs. All outputs may be tri-stated by bringing the
GOEb input high.
The VCCO voltage is board-connected to 2.5V or 3.3V based on the on-board connection of FB21 or FB22.
The output clocks of U2 are routed to devices to provide system level clocking. These pre-defined board clocks are
routed to input LatticeECP2M input clock pins for SERDES reference clocks, primary clocks, PLL inputs and DLL
inputs as well as connection to an SMA (J34). This SMA is 50-ohm terminated for off-board interconnection to test
equipment.
A clock input to the ispClock device can be provided from the PCI Express edge fingers. This is accomplished by
configuring the on-board resistor jumpers R79 and R80 (see Appendix A, Figure 9).
SERDES
(see Appendix A, Figure 9)
SERDES Reference Clock
The 50-ohm terminated SMA connectors are provided to supply reference clocks directly to the LatticeECP2M
device from the ispClock management device. This device drives clocks to both SERDES quads via 100-ohm
LVDS signaling. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same
SERDES reference clocks. The board can also be provisioned to source the clock from the PCI Express edge fin-
gers directly to the SERDES REFCLK pins.
SERDES Channels
Note: Surface Mounted SMA Connections are only available for the LFE2M50E-FF672 device.
(see Appendix A, Figure 9)
DC coupled top-mounted SMA connectors connect to the three SERDES Tx and Rx channels of the L-Quad SER-
DES. These pins are directly coupled to the designated SMA connector creating a path for both input and output
differential data.

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Lattice Semiconductor Evaluation Board User’s Guide
Table 5. SERDES Connectors (see Appendix A, Figure 9)
SERDES SMPTE Channels
Note: SERDES SMPTE channels are available only for the LFE2M50E-FF672 (or larger) device.
(see Appendix A, Figure 9)
A single-channel 75-ohm SERDES channel is connected to BNC edge connectors. These connections are pro-
vided to connect to SMPTE video equipment. The channels include the appropriate passive components for
interoperability to SMPTE devices.
Table 6. SERDES SMPTE BNC Connectors (see Appendix A, Figure 9)
SERDES PCI Express Channels
(see Appendix A, Figure 9)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge
fingers (CN1) to fit directly into an x4 host receptacle. Power can be supplied directly from the PCI Express host via
the edge finger connections.
FPGA Test Pins
(see Appendix A, Figure 14)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS
designated according to the following table.
Table 7. FPGA Test Pins (see Appendix A, Figure 11)
SMA Channel Name SMA Channel Name
J18 L_HDINP0 J19 L_HDOUTP0
J21 L_HDINN0 J22 L_HDOUTN0
J24 L_HDINP1 J25 L_HDOUTP1
J26 L_HDINN1 J27 L_HDOUTN1
J29 L_HDINP2 J30 L_HDOUTP2
J32 L_HDINN2 J33 L_HDOUTN2
BNC Channel Name
J20 L_HDINP3
J23 L_HDINN3
J28 L_HDOUTP3
J31 L_HDOUTN3
Switch BGA Netname LED BGA NetName
SW6D T30 Switch1 D16 U3 RED1
SW6C T4 Switch2 D17 U4 YELLOW1
SW6B P8 Switch3 D19 U5 GREEN1
SW6A R6 Switch4 D21 U6 BLUE1
SW5D T1 Switch5 D15 U2 RED2
SW5C U1 Switch6 D18 V1 YELLOW2
SW5B R7 Switch7 D20 W2 GREEN2
SW5A T5 Switch8 D22 V2 BLUE2

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LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Note: LEDs will illuminate if connected to an unprogrammed FPGA pin. It is recommended that a pull-down be pro-
grammed on FPGA output pins.
17-Segment LED Display
(see Appendix A, Figure 14)
General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins
can be driven low to illuminate the display segments.
Figure 4. 17-Segment LED Display
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit the
evaluation of several types of FPGA I/O buffers. The use of several termination schemes permits an easy interface
for each buffer type.
Table 8. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13)
SMA
Designation Name
LFE2M35E
Signal 672-BGA
Termination
Description
Termination
Resistor(s)
J37 LVDS_INP0 PR37A N23 100-ohm Differential R130
J39 LVDS_INN0 PR37B M21
LVDS_INP1 PR41A P24 100-ohm Differential R132
LVDS_INN1 PR41B P23
J45 LVDS_INP2 PR51A T24 100-ohm Differential R134
J47 LVDS_INN2 PR51B U24
J49* LVDS_INP3 PR57A V24 100-ohm Differential R136
J51* LVDS_INN3 PR57B W24
J38 LVDS_OUTP0 PR50A T23 100-ohm Differential R131
J40 LVDS_OUTN0 PR50B T22
J42 LVDS_OUTP1 PR53A V26 100-ohm Differential R133
Segment BGA
A
B
C
D
E
F
G
H
K
M
N
P
R
S
T
U
DP
H2
J3
G1
H3
J7
H5
G5
G6
F3
J8
E1
J9
E3
F5
D3
F6
C2
AB
C
D
G
FE DP
H
TSR
KMN
UP

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Lattice Semiconductor Evaluation Board User’s Guide
Test Pad Array
A 5 x 12 array of test pads are provided for the user to utilize for test points. This array provides 48 general I/O con-
tacts and 12 ground points.
Table 9. Test Pad Array BGA Reference
High Speed Test Point
(see Appendix A, Figure 13)
DP1
General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
(see Appendix A, Figure 14)
U18
The LatticeECP2M Evaluation Board is equipped to an 84-ball BGA DDR2 SDRAM memory device such as a
Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation
board includes termination of address and command signals. It includes all power and external components
needed to demonstrate the memory controller of the LatticeECP2M device
J44 LVDS_OUTN1 PR53B V25
J46 LVDS_OUTP2 PR55A W26 100-ohm Differential R135
J48 LVDS_OUTN2 PR55B W25
J50 LVDS_OUTP3 PR59A Y26 100-ohm Differential R137
J52 LVDS_OUTN3 PR59A AA26
AA20 V17 W20 AC25 AC23 AD26 AB21 AC22 AD12 AF12 W14 AB13
AA13 AE9 AF9 AB6 E23 E24 P26 P25 U21 U19 V21 J2
GND GND GND GND GND GND GND GND GND GND GND GND
K7 J6 K5 L5 P5 N6 P4 R3 W5 Y4 U8 W6
G7 G8 E6 D5 G12 C8 E13 H17 E14 G17 D17 E17
Table 8. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13) (Continued)
SMA
Designation Name
LFE2M35E
Signal 672-BGA
Termination
Description
Termination
Resistor(s)
12345 6789101112
13 14 15 16 17 1819 20 21 22 23 24
25 26 27 2829 30 31 32 33 34 35 36
37 3839 40 41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56 57 5859 60
Test Points Array on Component Side

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Lattice Semiconductor Evaluation Board User’s Guide
Ordering Information
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
[phone] (Outside North America)
e-mail: techsuppor[email protected]
Internet: www.latticesemi.com
Revision History
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
Description Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP2M PCI Express x4 Evaluation Board LFE2M35E-P4-EV
Date Version Change Summary
September 2006 01.0
Initial release.
December 2006 01.1
Includes new SERDES schematic in Appendix A.
March 2007 01.2
Added Ordering Information section.
April 2007 01.3
Updated Configuration/Testpoints schematic.
April 2007 01.4
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
January 2008 01.5
Updated Introduction text section.
February 2008 01.6
Updated board photo.
10

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Appendix A. Schematics
Figure 5. Cover Page
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Title
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ECP2M PCI EXPRESS Card
1.0
Cover Page
C
111
Title
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teehS:etaDof
ECP2M PCI EXPRESS Card
1.0
Cover Page
C
111
Title
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ECP2M PCI EXPRESS Card
1.0
Cover Page
C
111
Board will meet PCI Express Electromechanical Specification Rev 1.0 Add-in card form factor for standard height and full length
4.376" Height x 9.5" Length
ECP2M-672fpBGA PCI Express Platform Evaluation Board
ECP2M 672fpBGA
ispClk 5620A
SMPTE Video Interface
3G SMAs
x4 PCIe

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Lattice Semiconductor Evaluation Board User’s Guide
Figure 6. DC/DC Conversion
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
2_5_TRIM
CORE_TRIM
1_2_TRIM
3_3_TRIM
12_0V
2_5V
3_3V
12_0V
VCC_CORE 1_5V
2_5V12_0V
1_2V
1_8V
12_0V12_0V
VCC_CORE
3_3VIN
12_0V
1_8V
1_5V
1_2V
3_3VIN
3_3VIN
12_0V
12_0V
12_0V
12_0V
3_3VIN 3_3V
12_0V 12_0V
Title
veR
t
cejorP
e
z
iS
t
eeh
S
:eta
Dof
ECP2M PCI EXPRESS Card
1.0
DC/DC Conversion
C
211
Title
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zi
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teehS:etaD of
ECP2M PCI EXPRESS Card
1.0
DC/DC Conversion
C
211
Title
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ECP2M PCI EXPRESS Card
1.0
DC/DC Conversion
C
211
GND Pads
Distributed around the board
2.5V
POWER RAIL GOOD INDICATORS
V5.2V8
.1E
ROC_CCV 3.3V1.2V
1.5V
FPGA VCC_CORE
1.8V
1.5V
1.2V
12VIN GOOD
+12VDC
GND
3.3V
4.32K Typical
POWER INPUT
Q2
2N2222/SOT23
Q2
2N2222/SOT23
3
1
2
R1
470R-1206SMT
R1
470R-1206SMT
F3 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse
F3 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse
R8
10K-0603SMT
R8
10K-0603SMT
G
D1
LED-SMT1206_GREEN
G
D1
LED-SMT1206_GREEN
R38
2_2K-0603SMT
R38
2_2K-0603SMT
TP8
TESTPOINT
TP8
TESTPOINT
1
U5
PTH12060W
U5
PTH12060W
GND
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND
7TRACK 8
MDWN 9
MUP 10
TP5
TESTPOINT
TP5
TESTPOINT
1
+
C5
330UF-FKSMT
+
C5
330UF-FKSMT
C18
22UF-16V_TANTBSMT
C18
22UF-16V_TANTBSMT
F2 F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F2 F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
U7
PTH12060W
U7
PTH12060W
GND
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND
7TRACK 8
MDWN 9
MUP 10
G
D3
LED-SMT1206_GREEN
G
D3
LED-SMT1206_GREEN
G
D6
LED-SMT1206_GREEN
G
D6
LED-SMT1206_GREEN
+
C7
330UF-FKSMT
+
C7
330UF-FKSMT
R31
OPEN-0805SMT
R31
OPEN-0805SMT
C17
100NF-0603SMT
C17
100NF-0603SMT
C14
10UF-16V_TANTBSMT
C14
10UF-16V_TANTBSMT
+
C15 330UF-FKSMT
+
C15 330UF-FKSMT
C4
10UF-16V_TANTBSMT
C4
10UF-16V_TANTBSMT
+
C1
470UF-FKSMT
+
C1
470UF-FKSMT
R29
0R-0603SMT
R29
0R-0603SMT
G
D2
LED-SMT1206_GREEN
G
D2
LED-SMT1206_GREEN
TP10
TESTPOINT
TP10
TESTPOINT
1
R22 BOURNS-3224W-10K R22 BOURNS-3224W-10K
R14
0R-0805SMT
R14
0R-0805SMT
R18
OPEN-0805SMT
R18
OPEN-0805SMT
R15
0R-0603SMT
R15
0R-0603SMT
R35
OPEN-0603SMT
R35
OPEN-0603SMT
R32
OPEN-0805SMT
R32
OPEN-0805SMT
R37 BOURNS-3224W-10K R37 BOURNS-3224W-10K
R5
470R-1206SMT
R5
470R-1206SMT
C16
10UF-16V_TANTBSMT
C16
10UF-16V_TANTBSMT
U8
AMS1503CT
U8
AMS1503CT
VPOWER
5
VCONTROL
4OUTPUT 3
ADJUST_GND
2SENSE 1
R26
100K-0603SMT
R26
100K-0603SMT
TP12
TESTPOINT
TP12
TESTPOINT
1
TP11
TESTPOINT
TP11
TESTPOINT
1
R24
BOURNS-3224W-2K
R24
BOURNS-3224W-2K
C10
22UF-16V_TANTBSMT
C10
22UF-16V_TANTBSMT
R9
10K-0603SMT
R9
10K-0603SMT
R3
470R-1206SMT
R3
470R-1206SMT
R12
100K-0603SMT
R12
100K-0603SMT
R39
BOURNS-3224W-5K
R39
BOURNS-3224W-5K
G
D7 LED-SMT1206_GREEN
G
D7 LED-SMT1206_GREEN
G
D5 LED-SMT1206_GREEN
G
D5 LED-SMT1206_GREEN
C19
100NF-0603SMT
C19
100NF-0603SMT
R19
OPEN-0805SMT
R19
OPEN-0805SMT
Q3
2N2222/SOT23
Q3
2N2222/SOT23
3
1
2
TP7
TESTPOINT
TP7
TESTPOINT
1
C3
10UF-16V_TANTBSMT
C3
10UF-16V_TANTBSMT
F6
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F6
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
+
C2
100UF-FKSMT
+
C2
100UF-FKSMT
R23 15K-0603SMT R23 15K-0603SMT
R27
100K-0603SMT
R27
100K-0603SMT
U4
AMS1503CT
U4
AMS1503CT
VPOWER
5
VCONTROL
4OUTPUT 3
ADJUST_GND
2SENSE 1
Q4
2N2222/SOT23
Q4
2N2222/SOT23
3
1
2
R33
124R-0603SMT
R33
124R-0603SMT
R4 470R-1206SMT R4 470R-1206SMT
F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse
F5 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse
TP3
TESTPOINT
TP3
TESTPOINT
1
TP2
TESTPOINT
TP2
TESTPOINT
1
R13
100K-0603SMT
R13
100K-0603SMT
U6
PTH12060W
U6
PTH12060W
GND
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND
7TRACK 8
MDWN 9
MUP 10
R30
0R-0805SMT
R30
0R-0805SMT
F1
F1251CT-ND
10A Fast-Blo SMT Socketed Fuse
F1
F1251CT-ND
10A Fast-Blo SMT Socketed Fuse
C6 10UF-16V_TANTBSMT C6 10UF-16V_TANTBSMT
R16
0R-0603SMT
R16
0R-0603SMT
F4 F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F4 F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
R20
OPEN-0603SMT
R20
OPEN-0603SMT
U3
PTH03010W
U3
PTH03010W
GND
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND
7TRACK 8
MDWN 9
MUP 10
R21 BOURNS-3224W-10K R21 BOURNS-3224W-10K
TP4
TESTPOINT
TP4
TESTPOINT
1
G
D4
LED-SMT1206_GREEN
G
D4
LED-SMT1206_GREEN
TP1
TESTPOINT
TP1
TESTPOINT
1
R2
470R-1206SMT
R2
470R-1206SMT
+
C13
330UF-FKSMT
+
C13
330UF-FKSMT
Q1
2N2222/SOT23
Q1
2N2222/SOT23
3
1
2
C11
100NF-0603SMT
C11
100NF-0603SMT
R7
150R-0603SMT
R7
150R-0603SMT
J1
22HP037
Male Power Jack 2.1mm
J1
22HP037
Male Power Jack 2.1mm
1
3
2
R17
124R-0603SMT
R17
124R-0603SMT
C8
10UF-16V_TANTBSMT
C8
10UF-16V_TANTBSMT
R28
0R-0603SMT
R28
0R-0603SMT
R11
10K-0603SMT
R11
10K-0603SMT
R34
BOURNS-3224W-10K
R34
BOURNS-3224W-10K
TP9
TESTPOINT
TP9
TESTPOINT
1
TP6
TESTPOINT
TP6
TESTPOINT
1
R25
1_8K-0603SMT
R25
1_8K-0603SMT
C12
10UF-16V_TANTBSMT
C12
10UF-16V_TANTBSMT
TB1 Terminal Block/ED1202DS TB1 Terminal Block/ED1202DS
1
2
R6 100R-0603SMT R6 100R-0603SMT
C9
100NF-0603SMT
C9
100NF-0603SMT
R10
10K-0603SMT
R10
10K-0603SMT
R36
3_3K-0603SMT
R36
3_3K-0603SMT

16
LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Figure 7. Power Supplies
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
VCC_CORE
VDDTX
1_2V VDDP
VDDRX
1_8V
VCC_CORE
2_5V
VDDRX
VCC_CORE
VDDTX
VDDP
3_3V VDDP
VDDTX VDDRX
3_3V
VDDOB
2_5V
3_3V
1_8V
1_5V 1_2V
VDDIB
VDDIB
VDDOB
1_5V 1_2V
VDDIB VDDOB
1_2V
VCC_PLL
VCC_PLL
Title
veRtcej
o
r
P
eziS
teehS
:
e
t
a
Dof
ECP2M PCI EXPRESS Card
1.0
Power Supplies
C
311
Title
veR
t
c
e
jorPe
zi
S
teehS:etaD of
ECP2M PCI EXPRESS Card
1.0
Power Supplies
C
311
Title
veR
t
c
e
jorPe
zi
S
teehS:etaD of
ECP2M PCI EXPRESS Card
1.0
Power Supplies
C
311
C32 100NF-0603SMT C32 100NF-0603SMT
C58
1UF-16V-0805SMT
C58
1UF-16V-0805SMT
+
C29
22UF-16V_TANTBSMT
+
C29
22UF-16V_TANTBSMT
C70 1000PF-0402SMT C70 1000PF-0402SMT
FB8
BLM41PG600SN1
FB8
BLM41PG600SN1
C135
10NF-0603SMT
C135
10NF-0603SMT
C44
100NF-0603SMT
C44
100NF-0603SMT
C127
100NF-0603SMT
C127
100NF-0603SMT
C23 10NF-0603SMT C23 10NF-0603SMT
C99
10NF-0603SMT
C99
10NF-0603SMT
C120
100NF-0603SMT
C120
100NF-0603SMT
C25
10NF-0603SMT
C25
10NF-0603SMT
C96
10NF-0603SMT
C96
10NF-0603SMT
C66
100NF-0603SMT
C66
100NF-0603SMT
C72 1000PF-0402SMT C72 1000PF-0402SMT
C33
100NF-0603SMT
C33
100NF-0603SMT
C129
100NF-0603SMT
C129
100NF-0603SMT
VCC Core
ecp2m-672fpbga
U1I
VCC Core
ecp2m-672fpbga
U1I
VCC L12 VCC L13
VCC L14 VCC L15
VCC M11
VCC M12
VCC M15
VCC M16
VCC N11
VCC N16
VCC P11
VCC P16
VCC R11
VCC R12
VCC R15
VCC R16
VCC T12
VCC T13
VCC T14 VCC T15
C62
1UF-16V-0805SMT
C62
1UF-16V-0805SMT
C50 10NF-0603SMT C50 10NF-0603SMT
J101
JUMPER1
J101
JUMPER1
12
C75
100NF-0603SMT
C75
100NF-0603SMT
PP8PP8
12
+
C38
22UF-16V_TANTBSMT
+
C38
22UF-16V_TANTBSMT
C140
10NF-0603SMT
C140
10NF-0603SMT
C24
10NF-0603SMT
C24
10NF-0603SMT
C20
1UF-16V-0805SMT
C20
1UF-16V-0805SMT
C138
10NF-0603SMT
C138
10NF-0603SMT
C114
100NF-0603SMT
C114
100NF-0603SMT
C42 100NF-0603SMT C42 100NF-0603SMT
C115
10NF-0603SMT
C115
10NF-0603SMT
C41 100NF-0603SMT C41 100NF-0603SMT
C52 10NF-0603SMT C52 10NF-0603SMT
+
C130
22UF-16V_TANTBSMT
+
C130
22UF-16V_TANTBSMT
C139
10NF-0603SMT
C139
10NF-0603SMT
C110
100NF-0603SMT
C110
100NF-0603SMT
C22 10NF-0603SMT C22 10NF-0603SMT
C86
100NF-0603SMT
C86
100NF-0603SMT
C82
10NF-0603SMT
C82
10NF-0603SMT
C39
10NF-0603SMT
C39
10NF-0603SMT
C100
100NF-0603SMT
C100
100NF-0603SMT
PP2PP2
12
C91
100NF-0603SMT
C91
100NF-0603SMT
C132
10NF-0603SMT
C132
10NF-0603SMT
C49 10NF-0603SMT C49 10NF-0603SMT
C28 100NF-0603SMT C28 100NF-0603SMT
C131
1UF-16V-0805SMT
C131
1UF-16V-0805SMT
C116
100NF-0603SMT
C116
100NF-0603SMT
Power Supplies
ecp2m-672fpbga
U1J
Power Supplies
ecp2m-672fpbga
U1J
VCCIO0
B12 VCCIO0
B7
VCCIO1
D18
VCCIO0
F11
VCCIO1
F16
VCCIO2
G25
VCCIO0
J13
VCCIO1
J14
VCCIO0
K12
VCCIO1
K15
VCCIO2
L21
VCCIO2
M17
VCCIO2
M25
VCCIO2
N18
VCCIO5
AA11
VCCIO4
AA16
VCCJ AA7
VCCIO4
AC18
VCCIO8 AC24
VCCIO5
AE12
VCCIO5
AE7
VCCIO7
G2
VCCIO7
L6
VCCIO7
M10
VCCIO7
M2
VCCIO7
N9
VCCIO3
P18
VCCIO6
P9
VCCIO6
R10
VCCIO3
R17
VCCIO6
R2
VCCIO3
R25
VCCIO3
T21
VCCIO6
T6
VCCIO5
U12
VCCIO4
U15
VCCIO8 U17
VCCIO5
V13
VCCIO4
V14
VCCIO6
Y2
VCCIO3
Y25
VCCAUX J11
VCCAUX J12 VCCAUX J15
VCCAUX J16 VCCAUX L18
VCCAUX L9
VCCAUX M18 VCCAUX M9
VCCAUX R18 VCCAUX R9
VCCAUX T18
VCCAUX T9
VCCAUX V11
VCCAUX V12
VCCAUX V15
VCCAUX V16
+
C417
22UF-16V_TANTBSMT
+
C417
22UF-16V_TANTBSMT
PP7PP7
12
C84
100NF-0603SMT
C84
100NF-0603SMT
C63 100NF-0603SMT C63 100NF-0603SMT
C121
100NF-0603SMT
C121
100NF-0603SMT
C73 1000PF-0402SMT C73 1000PF-0402SMT
C107
10NF-0603SMT
C107
10NF-0603SMT
C94
10NF-0603SMT
C94
10NF-0603SMT
J100
JUMPER1
J100
JUMPER1
1 2
C118
100NF-0603SMT
C118
100NF-0603SMT
C31 100NF-0603SMT C31 100NF-0603SMT
C141
10NF-0603SMT
C141
10NF-0603SMT
C68
100NF-0603SMT
C68
100NF-0603SMT
C48
10NF-0603SMT
C48
10NF-0603SMT
C83
100NF-0603SMT
C83
100NF-0603SMT
C77 100NF-0603SMT C77 100NF-0603SMT
C65 100NF-0603SMT C65 100NF-0603SMT
C122
100NF-0603SMT
C122
100NF-0603SMT
C21
10NF-0603SMT
C21
10NF-0603SMT
+
C419
22UF-16V_TANTBSMT
+
C419
22UF-16V_TANTBSMT
C35
10NF-0603SMT
C35
10NF-0603SMT
C119
10NF-0603SMT
C119
10NF-0603SMT
C90 100NF-0603SMT C90 100NF-0603SMT
J98
HEADER 3
J98
HEADER 3
1
2
3
+
C112
22UF-16V_TANTBSMT
+
C112
22UF-16V_TANTBSMT
PP4PP4
12
C60 100NF-0603SMT C60 100NF-0603SMT
C34
100NF-0603SMT
C34
100NF-0603SMT
SERDES Supplies
ecp2m-672fpbga U1H
SERDES Supplies
ecp2m-672fpbga U1H
L_VCCRX3 AD13 L_VCCRX2 AD14
L_VCCTX3 AD16 L_VCCTX2 AD17
L_VCCP AD19
L_VCCTX1 AD21
L_VCCTX0 AD22
L_VCCRX1 AD24 L_VCCRX0 AD25
U_VCCRX3 C13 U_VCCRX2 C14
U_VCCTX3 C16 U_VCCTX2 C17
U_VCCP C19
U_VCCTX1 C21 U_VCCTX0 C22
U_VCCRX1 C24 U_VCCRX0 C25
U_VCCIB0
B25
U_VCCIB1
C23
U_VCCIB2
C15
U_VCCIB3
B13
U_VCCOB0
A22
U_VCCOB1
C20
U_VCCOB2
C18
U_VCCOB3
A16
L_VCCOB3
AF16
L_VCCOB1
AD20
L_VCCOB2
AD18
L_VCCOB0
AF22
L_VCCAUX33
AE19
U_VCCAUX33
B19
L_VCCIB0
AE25
L_VCCIB1
AD23
L_VCCIB2
AD15
L_VCCIB3
AE13
C117
10NF-0603SMT
C117
10NF-0603SMT
+
C87
22UF-16V_TANTBSMT
+
C87
22UF-16V_TANTBSMT
C89
100NF-0603SMT
C89
100NF-0603SMT
C43 100NF-0603SMT C43 100NF-0603SMT
C113
1UF-16V-0805SMT
C113
1UF-16V-0805SMT
C92
100NF-0603SMT
C92
100NF-0603SMT
C30
1UF-16V-0805SMT
C30
1UF-16V-0805SMT
C26
10NF-0603SMT
C26
10NF-0603SMT
C133
10NF-0603SMT
C133
10NF-0603SMT
PP3PP3
12
C64 100NF-0603SMT C64 100NF-0603SMT
C37 10NF-0603SMT C37 10NF-0603SMT
C71
1000PF-0402SMT
C71
1000PF-0402SMT
C125
100NF-0603SMT
C125
100NF-0603SMT
C101
10NF-0603SMT
C101
10NF-0603SMT
C74 1000PF-0402SMT C74 1000PF-0402SMT
C88
1UF-16V-0805SMT
C88
1UF-16V-0805SMT
C108
100NF-0603SMT
C108
100NF-0603SMT
C40 10NF-0603SMT C40 10NF-0603SMT
+
C104
22UF-16V_TANTBSMT
+
C104
22UF-16V_TANTBSMT
+
C59
22UF-16V_TANTBSMT
+
C59
22UF-16V_TANTBSMT
C47 5.6nF
0402
C47 5.6nF
0402
C46
5.6nF
0402
C46
5.6nF
0402
C36 100NF-0603SMT C36 100NF-0603SMT
C103
10NF-0603SMT
C103
10NF-0603SMT
C55
10NF-0603SMT
C55
10NF-0603SMT
C105
1UF-16V-0805SMT
C105
1UF-16V-0805SMT
FB2
BLM41PG600SN1
FB2
BLM41PG600SN1
C134
10NF-0603SMT
C134
10NF-0603SMT
C78
100NF-0603SMT
C78
100NF-0603SMT
C98
100NF-0603SMT
C98
100NF-0603SMT
C124
100NF-0603SMT
C124
100NF-0603SMT
PP1PP1
12
C54
10NF-0603SMT
C54
10NF-0603SMT
C79
10NF-0603SMT
C79
10NF-0603SMT
C97 10NF-0603SMT C97 10NF-0603SMT
C67
100NF-0603SMT
C67
100NF-0603SMT
C137
10NF-0603SMT
C137
10NF-0603SMT
C123
100NF-0603SMT
C123
100NF-0603SMT
PLL
ecp2m-672fpbga
U1G
PLL
ecp2m-672fpbga
U1G
LLM0_PLLCAP
T8
RLM0_PLLCAP
V19
RUM0_VCCPLL G19 RUM1_VCCPLL J17
LUM0_VCCPLL H7
LUM1_VCCPLL K6
LLM0_VCCPLL R8 LLM2_VCCPLL P7
RLM0_VCCPLL V18 RLM2_VCCPLL P20
C56
10NF-0603SMT
C56
10NF-0603SMT
FB1
BLM41PG600SN1
FB1
BLM41PG600SN1
C80
10NF-0603SMT
C80
10NF-0603SMT
C95 10NF-0603SMT C95 10NF-0603SMT
C61
100NF-0603SMT
C61
100NF-0603SMT
C418
1UF-16V-0805SMT
C418
1UF-16V-0805SMT
C45
100NF-0603SMT
C45
100NF-0603SMT
C109
10NF-0603SMT
C109
10NF-0603SMT
C420
1UF-16V-0805SMT
C420
1UF-16V-0805SMT
C85
100NF-0603SMT
C85
100NF-0603SMT
C76 100NF-0603SMT C76 100NF-0603SMT
C53
10NF-0603SMT
C53
10NF-0603SMT
C136
10NF-0603SMT
C136
10NF-0603SMT
FB3
BLM41PG600SN1
FB3
BLM41PG600SN1
C128
100NF-0603SMT
C128
100NF-0603SMT
C27
10NF-0603SMT
C27
10NF-0603SMT
C93
100NF-0603SMT
C93
100NF-0603SMT
J99 HEADER 3 J99 HEADER 3
1
2
3
C111
10NF-0603SMT
C111
10NF-0603SMT
C81
10NF-0603SMT
C81
10NF-0603SMT
C102
100NF-0603SMT
C102
100NF-0603SMT
C69
100NF-0603SMT
C69
100NF-0603SMT
C106
100NF-0603SMT
C106
100NF-0603SMT
C126
100NF-0603SMT
C126
100NF-0603SMT
PP5PP5
12
PP6PP6
12
+
C57
22UF-16V_TANTBSMT
+
C57
22UF-16V_TANTBSMT
C51 10NF-0603SMT C51 10NF-0603SMT

17
LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Figure 8. Configuration/Testpoints
5 5
4 4
3
3
2
2
1 1
D D
C C
B B A A
SFLASH_Q_0
SFLASH_Q_1
TCK
LOCAL_TDI
LOCAL_TCK
TDI_BUF
LOCAL_TMS
LOCAL_TDO
TCK
TDO_EC
TDI_EC
GSRN
PROGRAMN
INITN
DONE
DONE
INITN
TMS_BUF
SFLASH_Q_0
FLASH_DIS
GSRN
PROGRAMN
CFG2
CFG1 CFG0
TCK
TMS_EC
TDI_EC
TDO_EC
LOCAL_TCK
LOCAL_TDO
LOCAL_TDI
LOCAL_TMS
WRITEN
PROGRAMN
FPGA_D1
FPGA_CSSPI1N
3_3V
FPGA_D2
FPGA_D0
FPGA_D3
FPGA_D3
CSN
CS1N
FPGA_D[0..7]
INITN
FPGA_D4
FPGA_D4
FPGA_D6
FPGA_D5
FPGA_D5 FPGA_D6 FPGA_CSSPI0N
FPGA_D6
CS1NCSN
FPGA_D7
CSN
FPGA_D7
PROGRAMN
CFG2
DONE
CFG1 CFG0
FPGA_D0
SPIFASTN
FPGA_CCLK
FPGA_D7 FPGA_SISPI
FPGA_CSSPI1N
CS1N
FPGA_D0
FPGA_CCLK
WRITEN
DONE
INITN
FPGA_SISPI FPGA_D1
CFG2
CFG1
CFG0
FPGA_D2
FPGA_SISPI
FPGA_CCLK
FPGA_CCLK FPGA_CCLK
FPGA_CSSPI0N
FPGA_CSSPI0N
FPGA_CSSPI0N
SFLASH_Q_0 SPI0_Q
SFLASH_Q_1
SPI0_Q FPGA_D7
3_3V
TDI_BUF TDI_EC
TDO_ECTDI_ISPCLK
TDO_ISPCLK LOCAL_TDO
TMS_EC
TMS_ISPCLK
FPGA_CSSPI0N
FPGA_D0
3_3V
3_3V
3_3V
3_3V
3_3V 3_3V
2_5V
3_3V
3_3V
3_3V
3_3V 3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
TCK
[8]
PCIE_PERSTN[5]
GSRN[10]
TMS_ISPCLK[8]
TDI_ISPCLK[8] TDO_ISPCLK[8]
Title
veRtcejorPeziS
teehS:etaD of
1605 Valley Center Parkway
Bethlehem, PA 18017
ECP2M PCI EXPRESS Card
1.0
Conguration/Testpoints
C
411
Title
veRtcejorPeziS
tee
h
S:eta
Dof
1605 Valley Center Parkway
Bethlehem, PA 18017
ECP2M PCI EXPRESS Card
1.0
Conguration/Testpoints
C
411
Title
veRtcejorPeziS
tee
h
S:eta
Dof
1605 Valley Center Parkway
Bethlehem, PA 18017
ECP2M PCI EXPRESS Card
1.0
Conguration/Testpoints
C
411
FROM ISPVM CABLE
This LED
indicates activity
on TDI.
FPGA RESETN/GSRN
PROGRAMN
DONE indicator will light when configuration is successfully completed INITN indicator will light if an error occurs during configuration programming
FLASH1
FLASH0
ON
sysCONFIG Connector
ed
o
Mno
i
tarugifnoC2G
F
CCFG1CFG0
ispJTAG
Slave Serial
Master Serial
SPIm SPI Flash
Slave Parallel
Master Parallel
0(ON) 1(OFF)
XXX
1(OFF)
1(OFF)
1(OFF)
1(OFF)1(OFF)
1(OFF) 1(OFF)
0(ON)0(ON) 1(OFF)
0(ON) 0(ON)
0(ON)
0(ON)
0(ON) 0(ON)
RN1D
EXBV8V472JV
4.7K
RN1D
EXBV8V472JV
4.7K
45
J105
HEADER 3X2
J105
HEADER 3X2
2 4 6
1
3 5
R49 10K-0603SMT R49 10K-0603SMT
CONFIG
ecp2m-672fpbga
U1B
CONFIG
ecp2m-672fpbga
U1B
CFG2 AA21 CFG1 AA22
INITN AA23
CFG0 AB23
CCLK AB24
DONE AB25
PROGRAMN AC26
TCK AC3
TMS AC4
TDO V8
TDI W8
PR62A/BUSY
Y24
PR62B/DOUT/CSON
W23
PR63A/DI
V20
PR63B/D7
W21
PR64A/D6
AA24
PR64B/D5
Y23
PR65A/D4
W18
PR65B/D3
W22
PR66A/D2
Y20
PR66B/D1
W19
PR67B/CSN
AB26 PR67A/D0
Y22
PR68A/CS1N
Y21
PR68B/WRITEN
Y19
XRES H19
R41
10K-0603SMT
R41
10K-0603SMT
J103 JUMPER1 J103 JUMPER1
1 2
RN2D
EXBV8V472JV
4.7K
RN2D
EXBV8V472JV
4.7K
45
J13 JUMPER1 J13 JUMPER1
12
RN1C
4.7K
RN1C
4.7K
36
J2 HEADER 2 J2 HEADER 2
1 2
R55
10K-0603SMT
R55
10K-0603SMT
J10
HEADER 2X2
J10
HEADER 2X2
34 12
R47
10K-0603SMT
R47
10K-0603SMT
R51 680R-0603SMT R51 680R-0603SMT
SW3
B3F-1150
Momentary Switch
SW3
B3F-1150
Momentary Switch
1 3
2 4
U14B
SN74LVC125A/SO14
U14B
SN74LVC125A/SO14
3Y
83A 9
3OE_N 10
4Y
11 4A 12
4OE_N 13
VCC 14
SW1
SW DIP-3 CTS 194-3MST
SW1
SW DIP-3 CTS 194-3MST
1
2
3
6
5
4
RN1A
4.7K
RN1A
4.7K
18
C143
100NF-0603SMT
C143
100NF-0603SMT
U9
NC7WZ16-MACO6A/Fairchild TinyLogic
U9
NC7WZ16-MACO6A/Fairchild TinyLogic
IN A1 1
GND
2
IN A2 3
OUT Y2
4
VCC 5
OUT Y1
6
R66
100R-0603SMT
R66
100R-0603SMT
J60 HEADER 3 J60 HEADER 3
1 2 3
J7 JUMPER1 J7 JUMPER1
1 2
R57
4_7K-0603SMT
R57
4_7K-0603SMT
RN2C
4.7K
RN2C
4.7K
36
R54
220R-0603SMT
R54
220R-0603SMT
R48
10K-0603SMT
R48
10K-0603SMT
Y
D9 LED-SMT1206_RED
Y
D9 LED-SMT1206_RED
J3
HEADER 3
J3
HEADER 3
1 2 3
RN1B
4.7K
RN1B
4.7K
27
VCC GND
TDO
TDI ispEN_N
NC
TMS TCK
DONE
INITN
J8 HEADER 10
VCC GND
TDO
TDI ispEN_N
NC
TMS TCK
DONE
INITN
J8 HEADER 10
12
3 4 5
6
7
8
9
10
C144
10NF-0603SMT
C144
10NF-0603SMT
R46
10K-0603SMT
R46
10K-0603SMT
U15
M25P80-FLASH
U15
M25P80-FLASH
S#
1
Q
2
W#
3
GND
4
VCC 8
HOLD# 7
CLK 6
DI 5
R64
0R-0603SMT
R64
0R-0603SMT
R61
10K-0603SMT
R61
10K-0603SMT
RN2A
4.7K
RN2A
4.7K
18
C142
100NF-0603SMT
C142
100NF-0603SMT
R42
10K-0603SMT
R42
10K-0603SMT
J102 JUMPER1 J102 JUMPER1
1 2
J6
HEADER 17X2
J6
HEADER 17X2
2 4 6
8 10 12 14
16 18
20 22 24 26 28
30 32 34
1
3 5
7 9
11
13 15
17 19 21 23 25
27
29 31
33
R
D12 LED-SMT1206_GREEN
R
D12 LED-SMT1206_GREEN
C146
100NF-0603SMT
C146
100NF-0603SMT
U11
MAX6817
U11
MAX6817
IN1
1
GND
2
IN2
3
OUT2 4
VCC 5
OUT1 6
R62
4_7K-0603SMT
R62
4_7K-0603SMT
U12
M25P64-FLASH
U12
M25P64-FLASH
S#
7
Q
8
DU1
3
DU2
4
VCC
2HOLD# 1
DU4
6DU3 5
W# 9
VSS 10
DU5 11
DU6 12 DU7 13
DU8 14
D15
CK 16
J104 JUMPER1 J104 JUMPER1
12
R52
680R-0603SMT
R52
680R-0603SMT
C147
100NF-0603SMT
C147
100NF-0603SMT
R594_7K-0603SMT R594_7K-0603SMT
R40 10K-0603SMT R40 10K-0603SMT
J5 HEADER 3 J5 HEADER 3
1 2 3
R222 10K-0603SMT R222 10K-0603SMT
G
D11
LED-SMT1206_GREEN
G
D11
LED-SMT1206_GREEN
R45
10K-0603SMT
R45
10K-0603SMT
R56
10K-0603SMT
R56
10K-0603SMT
R63
220R-0603SMT
R63
220R-0603SMT
R50 10K-0603SMT R50 10K-0603SMT
R60
10K-0603SMT
R60
10K-0603SMT
RN2B
4.7K
RN2B
4.7K
27
SW2
B3F-1150
Momentary Switch
SW2
B3F-1150
Momentary Switch
13
2 4
R53 680R-0603SMT R53 680R-0603SMT
U14A
SN74LVC125A/SO14
U14A
SN74LVC125A/SO14
1OE_N 1
1A 2
1Y
3
2OE_N 4
2A 5
2Y
6
GND
7
U10
M25P80-FLASH
U10
M25P80-FLASH
S#
1
Q
2
W#
3
GND
4
VCC 8
HOLD# 7
CLK 6
DI 5
R221
10K-0603SMT
R221
10K-0603SMT
J11
HEADER 2X2
J11
HEADER 2X2
34 1
2
R584_7K-0603SMT R584_7K-0603SMT
C145
100NF-0603SMT
C145
100NF-0603SMT
R
D8
LED-SMT1206_RED
R
D8
LED-SMT1206_RED
Q5
2N2222/SOT23
Q5
2N2222/SOT23
3
1
2
J4
HEADER 3
J4
HEADER 3
1 2 3
R43 4_7K-0603SMTR43 4_7K-0603SMT
R44 10K-0603SMTR44 10K-0603SMT
J9 JUMPER1 J9 JUMPER1
1 2
Y
D10
LED-SMT1206_RED
Y
D10
LED-SMT1206_RED
R65
100R-0603SMT
R65
100R-0603SMT
U13
NC7WZ16-MACO6A/Fairchild TinyLogic
U13
NC7WZ16-MACO6A/Fairchild TinyLogic
IN A1 1
GND
2
IN A2 3
OUT Y2
4
VCC 5
OUT Y1
6
J12 JUMPER1 J12 JUMPER1
1 2

18
LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Figure 9. SERDES
5
5
4
4
3 3
2 2
1
1
DD CC BB
A A
PETn0 PETp0
PETp1PETn1
PETp2PETn2
PETp3PETn3
U_HDINP1
50
U_HDINN1
50
U_HDINP2
50
U_HDINN2
50
U_HDINP3
50
U_HDINP0
50
U_HDINN3
50
U_HDINN0
50
U_HDOUTP1
50
U_HDOUTN1
50
U_HDOUTP2
50
U_HDOUTN250
U_HDOUTP3
50
U_HDOUTN3
50
U_HDOUTP050
U_HDOUTN050
PERp0
PERn0 PERp1
PERn1
PETp3
PERp2
PERn2
PERp3 PERn3
PCIE_3V3
PETp0
PETn0
PETp1
PETn1 PETp2
PETn2
PETn3
PCIE_3V3
L_HDINN0 L_HDINN1
L_HDINP1
L_HDINN2 L_HDINP2
L_HDOUTN0
L_HDOUTN1 L_HDOUTP1
L_HDOUTN2
L_HDOUTP2
L_HDOUTP0
L_HDINP0
L_HDINP3SMPTE_360_INP1
SMPTE_360_INN1 L_HDINN3
L_HDOUTP3 L_HDOUTN3
PCIE_CLKN
PCIE_CLKP
U_HDINP0
U_HDINN0 U_HDINP1
U_HDINN1
U_HDINP2 U_HDINN2 U_HDINP3 U_HDINN3
x1 x4
x4 x1
U_HDOUTP3
U_HDOUTN3 U_HDOUTP2
U_HDOUTN2
U_HDOUTP1
U_HDOUTN1 U_HDOUTP0 U_HDOUTN0
L_HDINP3
L_HDINN3
L_HDINN2 L_HDINP2
L_HDINN1
L_HDINP1
L_HDINN0 L_HDINP0
L_HDOUTN3
L_HDOUTP3
L_HDOUTP2
L_HDOUTN2 L_HDOUTN1
L_HDOUTP1
L_HDOUTN0
L_HDOUTP0
PCIE_CLKN
PCIE_CLKP
SMA_REFCLKP
SMA_REFCLKN
L_REFCLKP
L_REFCLKN
PETn0
PETp0 PETp3
PETn3 PETp2
PETn2 PETp1 PETn1 PERp3
PERn3
PERp0
PERn0
PERn1 PERp1
PERp2
PERn2
U_REFCLKP U_REFCLKN
L_REFCLKP L_REFCLKN
12_0V
PCIE_CLKN PCIE_CLKP
PCIE_PERSTN
[4] PCIE_WAKEN [6]
PCIE_SMDAT [6] PCIE_SMCLK [6]
U_REFCLKN
[8]
U_REFCLKP[8] L_REFCLKN
[8]
L_REFCLKP[8]
U_REFCLKN [8]
U_REFCLKP [8]
PCIE_CLKN
PCIE_CLKP
Title
veR
t
cejor
Pez
iS
t
ee
hS:e
t
aD of
ECP2M PCI EXPRESS Card
1.0
SERDES
C
511
Title
v
eRtcejorPeziS
t
ee
hS:e
t
a
Dof
ECP2M PCI EXPRESS Card
1.0
SERDES
C
511
Title
v
eRtcejorPeziS
t
ee
hS:e
t
a
Dof
ECP2M PCI EXPRESS Card
1.0
SERDES
C
511
HDINHDOUT
PCIe Terminations
Place Capacitors and Resistors as Physically close to
device pin as possible
3G SMAs
VIDEO BNCs
X4 PCIe Board Fingers
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
200K 200K
PRSNT SELECT
AC Coupled receiver
+ 200K Ohm to GND
Populate for PCIe Clock
from Edge Finger
Place near U1
STUFF OPTION A: REPLACE C148,C149,C150,C151
C152, C153,C154, C155 WITH 0-OHM SHUNTS
STUFF OPTION A: R71,R72,R73,R74,
R77,R75,R78,R76
==OPEN
R78
200K-0402SMT
R78
200K-0402SMT
C153100NFX5R-0402SMT C153100NFX5R-0402SMT
J97 JUMPER1 J97 JUMPER1
1 2
R216 100R-0603SMTR216 100R-0603SMT
C165
0.018UF-0402SMT
C165
0.018UF-0402SMT
J28 BNC-Trompeter/UCBBJE20-7 J28 BNC-Trompeter/UCBBJE20-7
1
2
C162100NFX5R-0402SMT C162100NFX5R-0402SMT
J30
Rosenberger 32K153-400E3
J30
Rosenberger 32K153-400E3
1
2
R69 0R-0603SMTR69 0R-0603SMT
C156
100NFX5R-0402SMT C156 100NFX5R-0402SMT
J29
Rosenberger 32K153-400E3
J29
Rosenberger 32K153-400E3
1
2
C150
100NFX5R-0402SMT C150 100NFX5R-0402SMT
R80 0R-0603SMTR80 0R-0603SMT
C161100NFX5R-0402SMT C161100NFX5R-0402SMT
J33
Rosenberger 32K153-400E3
J33
Rosenberger 32K153-400E3
1
2
C154100NFX5R-0402SMT C154100NFX5R-0402SMT
R68 51R-0603SMT R68 51R-0603SMT
C160
100NFX5R-0402SMT C160 100NFX5R-0402SMT
R215 100R-0603SMTR215 100R-0603SMT
J32
Rosenberger 32K153-400E3
J32
Rosenberger 32K153-400E3
1
2
C152100NFX5R-0402SMT C152100NFX5R-0402SMT C158100NFX5R-0402SMT C158100NFX5R-0402SMT
J25
Rosenberger 32K153-400E3
J25
Rosenberger 32K153-400E3
1
2
CN1
PCI Express x4 Edge Finger Conn.
CN1
PCI Express x4 Edge Finger Conn.
PRSNT1#
A1
+12V
A2
+12V
A3
GND
A4
JTAG2
A5
JTAG3
A6
JTAG4
A7
JTAG5
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
GND
A12
REFCLK+
A13
REFCLK-
A14
GND
A15
PERp0
A16
PERn0
A17
GND
A18
RSVD_A19
A19
GND
A20
PERp1
A21
PERn1
A22
GND
A23
GND
A24
PERp2
A25
PERn2
A26
GND
A27
GND
A28
PERp3
A29
PERn3
A30
GND
A31
+12V B1 +12V B2
RSVD_B3 B3
GND B4
SMCLK B5
SMDAT B6
GND B7
+3.3V B8
JTAG1 B9
3.3Vaux B10
WAKE# B11
RSVD_B12 B12
GND B13
PETp0 B14 PETn0 B15
GND B16
PRSNT3# B17
GND B18
PETp1 B19 PETn1 B20
GND B21
GND B22
PETp2 B23 PETn2 B24
GND B25 GND B26
PETp3 B27 PETn3 B28
GND B29
RSVD_B30 B30
PRSNT4# B31
GND B32
RSVD_A32
A32
C155100NFX5R-0402SMT C155100NFX5R-0402SMT
C157
100NFX5R-0402SMT C157 100NFX5R-0402SMT
J24
Rosenberger 32K153-400E3
J24
Rosenberger 32K153-400E3
1
2
C149100NFX5R-0402SMT C149100NFX5R-0402SMT
J31 BNC-Trompeter/UCBBJE20-7 J31 BNC-Trompeter/UCBBJE20-7
1
2
J19
Rosenberger 32K153-400E3
J19
Rosenberger 32K153-400E3
1
2
R79 0R-0603SMTR79 0R-0603SMT
C159
100NFX5R-0402SMT C159 100NFX5R-0402SMT
J27
Rosenberger 32K153-400E3
J27
Rosenberger 32K153-400E3
1
2
R77
200K-0402SMT
R77
200K-0402SMT
J14
Rosenberger 32K153-400E3
J14
Rosenberger 32K153-400E3
1
2
J26
Rosenberger 32K153-400E3
J26
Rosenberger 32K153-400E3
1
2
C151
100NFX5R-0402SMT C151 100NFX5R-0402SMT
C163
100NFX5R-0402SMT C163 100NFX5R-0402SMT
TP13
TESTPOINT
TP13
TESTPOINT
1
J18
Rosenberger 32K153-400E3
J18
Rosenberger 32K153-400E3
1
2
R72
200K-0402SMT
R72
200K-0402SMT
J22
Rosenberger 32K153-400E3
J22
Rosenberger 32K153-400E3
1
2
C164
0.018UF-0402SMT
C164
0.018UF-0402SMT
R67 0R-0603SMTR67 0R-0603SMT
R75
200K-0402SMT
R75
200K-0402SMT
J21
Rosenberger 32K153-400E3
J21
Rosenberger 32K153-400E3
1
2
R71
200K-0402SMT
R71
200K-0402SMT
J23 BNC-Trompeter/UCBBJE20-7 J23 BNC-Trompeter/UCBBJE20-7
1
2
J15
Rosenberger 32K153-400E3
J15
Rosenberger 32K153-400E3
1
2
R76
200K-0402SMT
R76
200K-0402SMT
C148
100NFX5R-0402SMT C148 100NFX5R-0402SMT
J20 BNC-Trompeter/UCBBJE20-7 J20 BNC-Trompeter/UCBBJE20-7
1
2
R74
200K-0402SMT
R74
200K-0402SMT
SERDES
ecp2m-672fpbga U1A
SERDES
ecp2m-672fpbga U1A
U_HDOUTP3 A17 U_HDOUTP2 A18 U_HDOUTP1 A20 U_HDOUTP0 A21
U_HDOUTN3 B17 U_HDOUTN2 B18 U_HDOUTN1 B20 U_HDOUTN0 B21
L_HDOUTP3 AF17
L_HDOUTN3 AE17
L_HDOUTP2 AF18
L_HDOUTN2 AE18
L_HDOUTP1 AF20
L_HDOUTN1 AE20
L_HDOUTP0 AF21
L_HDOUTN0 AE21
U_HDINP3
A14
U_HDINN3
B14
U_HDINP2
A15
U_HDINN2
B15
U_HDINP1
A23
U_HDINN1
B23
U_HDINP0
A24
U_HDINN0
B24
U_REFCLKP
D19
U_REFCLKN
E19
L_HDINP3
AF14
L_HDINN3
AE14
L_HDINP2
AF15
L_HDINN2
AE15
L_HDINP1
AF23
L_HDINN1
AE23
L_HDINP0
AF24
L_HDINN0
AE24
L_REFCLKP
AC19
L_REFCLKN
AB19
J16
HEADER 2X2
J16
HEADER 2X2
3 4 1 2
R70 51R-0603SMT R70 51R-0603SMT
R73
200K-0402SMT
R73
200K-0402SMT

19
LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Figure 10. DDR2 FPGA Controller
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
DDR2_DQ4
DDR2_DQ12 DDR2_DQ13
DDR2_DQ15 DDR2_DQ5
DDR2_DQ6 DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ0 DDR2_DQ1
DDR2_DQ2
DDR2_DQ3 DDR2_DQ11 DDR2_DQ10 DDR2_DQ14
DQ10 DQ11 DQ12 DQ13
DQ14
DQ8
DQ0 DQ1 DQ2 DQ3
DQ15
DQ9
DQ7
DQ4
DQ5
DQ6
A7 A6
A5
A4
A3
A2
A1
A0 A9
A10
A11 A12
A8
DQS1
DDR2_DQS1
DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ5
DDR2_DQ6
DDR2_DQ4 DDR2_DQ7 DDR2_DQ8
DDR2_DQ[0:15]
DDR2_A5
DDR2_A3
DDR2_A0
DDR2_A8
DDR2_A4 DDR2_A1 DDR2_A7
DDR2_A6
DDR2_A2 DDR2_A9 DDR2_A10 DDR2_A12 DDR2_A11
DDR2_A[0:12]
DDR2_ODT0 DDR2_RAS#
DDR2_WE#
DDR2_CS0#
DDR2_CKE0#
DDR2_BA0
DDR2_BA1
DDR2_K# DDR2_K
DDR2_CAS#
ODT0
RAS#
WE#
CS0#
CKE0#
BA0
BA1
CAS#
K# K
DDR_VREF1
A0
A1
A2
A3
A4
A5
A6
A7 A8
A9
A10 A11 A12 DQS0 DQS1 DQ0
DQ1
DQ2
DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10
DQ11
DQ12
DQ13
DQ14 DQ15
DM0 DM1 BA0
BA1
RAS# CAS#
WE#
CS0#
K
K#
CKE0#
ODT0
DDR_VREF1
DQS0# DQS1#
DDR2_DQS0 DQS0
DQS1#
DQS0#
DDR2_DQS1#
DDR2_DQS0#
DDR2_DM0 DDR2_DM1
DM0 DM1
DDR2_DQS1
DDR2_DQS1#
DDR2_DQS0#
DDR2_DQS0
DDR2_DQ14 DDR2_DQ12
DDR2_DQ13
DDR2_DQ15 DDR2_DQ11
DDR2_DQ10 DDR2_DQ9
2_5V
1_8V
1_8V
FPGA_VTT
FPGA_VTT
FPGA_VTT
1_8V
FPGA_VTT
DDR2_DQ[0:15][7]
DDR2_BA0 [7] DDR2_BA1 [7] DDR2_K [7] DDR2_K# [7] DDR2_CKE0 [7]
DDR2_A[0:12] [7]
DDR2_WE# [7]
DDR2_RAS# [7]
DDR2_CAS# [7] DDR2_ODT0 [7] DDR2_CS0# [7]
OSC_IN_1 [8]
PCIE_WAKEN [5]
PCIE_SMCLK [5]
PCIE_SMDAT [5]
ISPCLK_RST [8]
PLL_BYPASS [8]
PS0 [8] PS1 [8] GOE [8]
SGATE [8]
REFSEL [8] OEX [8]
OEY [8]
ISPCLK_LOCK [8]
TestArray1 [10]
TestArray2 [10]
TestArray3 [10] TestArray4 [10]
TestArray5 [10]
TestArray6 [10] TestArray7 [10] TestArray8 [10]
TestArray15
[10]
TestArray9[10] TestArray16[10]
TestArray10[10]
TestArray11[10]
TestArray12
[10]
TestArray13[10]
TestArray14
[10]
DDR2_DQS0#[7]
DDR2_DQS0[7] DDR2_DQS1[7]
DDR2_DQS1#[7]
DDR2_DM0 [7] DDR2_DM1 [7]
Title
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ECP2M PCI EXPRESS Card
1.0
DDR2 FPGA Controller
C
611
Title
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ECP2M PCI EXPRESS Card
1.0
DDR2 FPGA Controller
C
611
Title
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ECP2M PCI EXPRESS Card
1.0
DDR2 FPGA Controller
C
611
ALL Memory controller buses, clocks, and control traces must be 50 Ohm
Transmission lines
All these 741X083/33-ohm
devices should be placed near the FPGA.
This RT140287/50-ohm pack
should be placed near the FPGA.
All these 741X083/22-ohm devices should be placed near the FPGA.
R86
0R-0603SMT
R86
0R-0603SMT
SP3SP3
1
+
C168
47UF-16V_TANTBSMT
+
C168
47UF-16V_TANTBSMT
RN3 22 741X083RN3 22 741X083
1 2 3 4
8
7
6
5
Bottom
Bank5
Bank4
ecp2m-672fpbga
U1C
Bottom
Bank5
Bank4
ecp2m-672fpbga
U1C
PB14A
AA10
PB16B
AB10
PB24A
AC11
PB14B
AC8
PB15B
AC9
PB13B
AD6 PB13A
AE5
PB17A
AF3
PB17B
AF4
PB18A
AF5
PB18B
AF6
PB15A
W12
PB16A
W13
PB2A
AB6
PB2B
Y8
PB3A
AD1
PB3B
AD2
PB4A
AC5
PB4B
AA8
PB5A
AC6
PB5B
W9
PB6A
AB7
PB6B
Y9
PB7A
AD3
PB7B
AD4
PB8A
AA9
PB8B
W10
PB9A
AC7
PB9B
Y10
PB10A
AE2
PB10B
AD5
PB12A
W11
PB12B
AB8
PB11A
AE4
PB11B
AE3
PB24B
AB12
PB23B
AC10
PB19B
AB11
PB21B
AA12
PB22B
AF8
PB20B
AF7
PB22A
AE8
PB23A
AD9
PB21A
AD8
PB20A
AD7
PB19A
Y12
PB25A
AD10
PB25B
Y13
PB26A
AF9
PB26B
AE9
PB33A
AA13
PB33B
AB13
PB34A/VREF2_5
W14
PB34B/VREF1_5
AC12
PB35A/PCLKT5_0
AF12
PB35B/PCLKC5_0
AD12
PB27A
AF10
PB27B
AE10
PB28A
AD11
PB28B
AF11
PB40A/PCLKT4_0 AC13
PB40B/PCLKC4_0 Y14
PB41B/VREF1_4 AC14
PB42A AB14
PB42B AA14 PB48A AC15 PB49A AB15
PB49B AC16 PB50B AB16 PB51A AA15
PB52A Y15
PB52B AC17 PB54A W15 PB54B AB17
PB57A AB20
PB58A AC20
PB59B W16
PB60A AA17
PB61A AA18 PB61B Y17 PB63A AC21
PB65A W17 PB65B AA19
PB68B Y18
PB69A AC22 PB69B AB21
PB70B AD26 PB71A AC23
PB71B AC25 PB72B W20 PB73A V17
PB73B AA20
R21851R-0603SMT R21851R-0603SMT
SP5SP5
1
R854_7K-0603SMT R854_7K-0603SMT
RN4
22
741X083 RN4
22
741X083
1
2
3 4
8 7 6 5
RN522741X083 RN522741X083
1 2 3 4
8 7 6 5
R22051R-0603SMT R22051R-0603SMT
C170
1UF-16V-0805SMT
C170
1UF-16V-0805SMT
R87 0R-0603SMTR87 0R-0603SMT
SP2SP2
1
C171
100NF-0603SMT
C171
100NF-0603SMT
R1
R1
R1=50 Ohm
RP1
CTS-RT1402B7
R1
R1
R1=50 Ohm
RP1
CTS-RT1402B7
A2 A2
B2 B2
C2 C2
D2 D2
E2 E2
F2 F2
G2 G2
H2 H2
J2 J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3
J3
A1 A1
B1 B1
C1 C1 D1 D1
E1 E1
F1 F1
G1 G1
H1 H1
J1 J1
+
C172
100UF-FKSMT
+
C172
100UF-FKSMT
SP4SP4
1
C175
100NF-0603SMT
C175
100NF-0603SMT
C169
100NF-0603SMT
C169
100NF-0603SMT
RN922741X083 RN922741X083
1 2
3
4
8
7 6 5
R21751R-0603SMT R21751R-0603SMT
RN14 33 741X083 RN14 33 741X083
1
2 3 4
8 7
6 5
RN822741X083 RN822741X083
1
2
3
4
8 7
6
5
SP6SP6
1
C176
10NF-0603SMT
C176
10NF-0603SMT
SP8SP8
1
C166
10NF-0603SMT
C166
10NF-0603SMT
PP9PP9
12
C177 100NF-0603SMT C177 100NF-0603SMT
SP7SP7
1
SP1SP1
1
SP10SP10
1
C178 10NF-0603SMT C178 10NF-0603SMT
R84
1K-0603SMT
R84
1K-0603SMT
RN10 33 741X083RN10 33 741X083
1 2 3 4
8 7
6 5
+
C174
10UF-16V_TANTBSMT
+
C174
10UF-16V_TANTBSMT
RN12 33 741X083RN12 33 741X083
1 2 3 4
8
7 6
5
C179 100NF-0603SMT C179 100NF-0603SMT
SP12SP12
1
R81
1K-0603SMT
R81
1K-0603SMT
RN11 33 741X083 RN11 33 741X083
1 2
3
4
8 7 6
5
C180
10NF-0603SMT
C180
10NF-0603SMT
SP9SP9
1
U16
LP2996-SO8
U16
LP2996-SO8
GND
1
SD
2
VSENSE 3
VREF
4
VDDQ
5
AVIN 6
PVIN 7
VTT 8
RN722741X083 RN722741X083
1
2
3 4
8 7 6 5
RN13 33 741X083RN13 33 741X083
1
2
3 4
8
7 6 5
R82 1K_ADJ/SMT3MM R82 1K_ADJ/SMT3MM
C173
1UF-16V-0805SMT
C173
1UF-16V-0805SMT
SP11SP11
1
R21951R-0603SMT R21951R-0603SMT
C181
100NF-0603SMT
C181
100NF-0603SMT
R83 OPEN-0603SMT R83 OPEN-0603SMT
C167
100NF-0603SMT
C167
100NF-0603SMT
RN622741X083 RN622741X083
1 2 3
4
8 7 6 5

20
LatticeECP2M PCI Express x4
Lattice Semiconductor Evaluation Board User’s Guide
Figure 11. DDR2 Device/Termination
5 5
4 4
3 3
2 2
1 1
DD C C BB A A
DDR2_DQS0
DDR2_DQ1 DDR2_DQ4
DDR2_DQ6 DDR2_DQ2 DDR2_DQ0
DDR2_DQ5 DDR2_DQ7 DDR2_DQ3
DDR2_DQ8
DDR2_DQ[0:15]
DDR2_DQ9 DDR2_DQ14
DDR2_DQ13
DDR2_DQ11
DDR2_DQ10
DDR2_DQ15 DDR2_DQ12 DDR2_DQS1 DDR2_A5 DDR2_A3
DDR2_A0
DDR2_A8 DDR2_A4 DDR2_A1 DDR2_A7 DDR2_A6
DDR2_A2
DDR2_A9
DDR2_A10
DDR2_A12
DDR2_A11
DDR2_DM0
DDR2_DM1
VDDL
DDR2_ODT0 DDR2_RAS#
DDR2_WE#
DDR2_CS0#
DDR2_CKE0#
DDR2_BA0 DDR2_BA1
DDR2_K#
DDR2_K
DDR2_CAS#
DDR2_BA1 DDR2_BA0 DDR2_RAS# DDR2_WE# DDR2_CAS#
DDR2_A5
DDR2_A3 DDR2_A0 DDR2_A8 DDR2_A4
DDR2_A1 DDR2_A7 DDR2_A6
DDR2_A2
DDR2_A9
DDR2_A12
DDR2_A11
DDR2_A10
DDR2_A[0:12]
DDR2_CS0#
DDR2_ODT0
DDR2_DM0
DDR2_DM1
DDR2_K
DDR2_K#
DDR2_CKE0#
DDR2_A[0:12]
DDR2_DQS0#
DDR2_DQS1#
1_8V
1_8V
2_5V
2_5V
1_8V
1_8V
DDR_VTT
1_8V
1_8V
DDR_VTT
DDR_VTT
DDR_VTT
DDR_VTT DDR_VTT
DDR2_DQ[0:15] [6] DDR2_A[0:12] [6] DDR2_DQS0 [6] DDR2_DM0 [6]
DDR2_DM1 [6] DDR2_K [6] DDR2_K# [6] DDR2_CKE0 [6]
DDR2_WE# [6]
DDR2_RAS# [6]
DDR2_CAS# [6]
DDR2_ODT0 [6]
DDR2_CS0# [6] DDR2_BA0 [6]
DDR2_BA1 [6]
DDR2_DQS0# [6]
DDR2_DQS1 [6] DDR2_DQS1# [6]
Title
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S
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ECP2M PCI EXPRESS Card
1.0
DDR2 Device/Termination
C
711
Title
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S
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ECP2M PCI EXPRESS Card
1.0
DDR2 Device/Termination
C
711
Title
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S
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S
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ECP2M PCI EXPRESS Card
1.0
DDR2 Device/Termination
C
711
VTT
RESISTOR
VTT
X1
needs to be matched length for all traces
U1 Pin
DDR2 Device Pin
X1
X2
Termination
at end of line
C206 100NF-0603SMT C206 100NF-0603SMT
+
C185
47UF-16V_TANTBSMT
+
C185
47UF-16V_TANTBSMT
+
C194
100UF-FKSMT
+
C194
100UF-FKSMT
PP11PP11
12
C203
100NF-0603SMT
C203
100NF-0603SMT
C207
10NF-0603SMT
C207
10NF-0603SMT
C190 100NF-0603SMT C190 100NF-0603SMT
U18B
DDR2-SDRAM-84FBGA
U18B
DDR2-SDRAM-84FBGA
VDD
A1
VDD
E1
VDD
J9
VDD
M9
VDD
R1
VSS
A3
VSS
E3
VSS
J3
VSS
N1
VSS
P9
VDDQ
A9
VDDQ
C1
VDDQ
C3
VDDQ
C7
VDDQ
C9
VDDQ
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VSSQ
A7
VSSQ
B2
VSSQ
B8
VSSQ
D2
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VDDL
J1 VREF
J2
VSSDL
J7
C197
10NF-0603SMT
C197
10NF-0603SMT
C191 10NF-0603SMT C191 10NF-0603SMT
C208 100NF-0603SMT C208 100NF-0603SMT
R96 51R-0603SMTR96 51R-0603SMT
C201
1UF-16V-0805SMT
C201
1UF-16V-0805SMT
R95 51R-0603SMTR95 51R-0603SMT
C209 10NF-0603SMT C209 10NF-0603SMT
C192 100NF-0603SMT C192 100NF-0603SMT
C199
1UF-16V-0805SMT
C199
1UF-16V-0805SMT
+
C200
22UF-16V_TANTBSMT
+
C200
22UF-16V_TANTBSMT
R94
1K-0603SMT
R94
1K-0603SMT
C210
100NF-0603SMT
C210
100NF-0603SMT
+
C198
22UF-16V_TANTBSMT
+
C198
22UF-16V_TANTBSMT
+
C196
10UF-16V_TANTBSMT
+
C196
10UF-16V_TANTBSMT
FB4
BLM41PG600SN1
FB4
BLM41PG600SN1
C212
1UF-16V-0805SMT
C212
1UF-16V-0805SMT
C213
100NF-0603SMT
C213
100NF-0603SMT
R90
1K-0603SMT
R90
1K-0603SMT
R89
0R-0603SMT
R89
0R-0603SMT
U17
LP2996-SO8
U17
LP2996-SO8
GND
1
SD
2
VSENSE 3
VREF
4
VDDQ
5
AVIN 6
PVIN 7
VTT 8
C214
10NF-0603SMT
C214
10NF-0603SMT
+
C211
22UF-16V_TANTBSMT
+
C211
22UF-16V_TANTBSMT
R1R1
R1=50 Ohm
RP2
CTS-RT1402B7
R1R1
R1=50 Ohm
RP2
CTS-RT1402B7
A2 A2
B2 B2
C2 C2
D2 D2
E2 E2
F2 F2
G2 G2
H2 H2
J2 J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3
J3
A1 A1 B1 B1
C1 C1 D1 D1
E1 E1
F1 F1
G1 G1
H1 H1
J1 J1
U18A
DDR2-SDRAM-84FBGA
U18A
DDR2-SDRAM-84FBGA
NC_A2 A2
DQ14 B1 DQ15 B9
DQ9 C2
DQ8 C8
DQ12 D1
DQ11 D3 DQ10 D7 DQ13 D9
DQ6 F1
DQ7 F9
DQ1 G2 DQ0 G8
DQ4 H1 DQ3 H3 DQ2 H7
DQ5 H9
NC_E2 E2
LDQS#/NU E8
LDM F3
LDQS F7
CK J8
CK# K8
CKE K2
WE# K3
RAS# K7
ODT K9
BA0 L2
BA1 L3
CAS# L7
CS# L8
RFU_L1 L1
A0 M8 A1 M3 A2 M7 A3 N2 A4 N8
A5 N3
A6 N7
A7 P2 A8 P8
A9 P3
A10 M2
A11 P7
A12 R2
RFU_R3 R3
RFU_R7 R7
NC_R8 R8
UDM B3
UDQS B7
UDQS#/NU A8
R92 1K_ADJ/SMT3MM R92 1K_ADJ/SMT3MM
R1R1
R1=50 Ohm
RP3
CTS-RT1402B7
R1R1
R1=50 Ohm
RP3
CTS-RT1402B7
A2 A2
B2 B2
C2 C2
D2 D2
E2 E2
F2 F2
G2 G2
H2 H2
J2 J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3
J3
A1 A1 B1 B1
C1 C1
D1 D1
E1 E1
F1 F1
G1 G1
H1 H1
J1 J1
C195
1UF-16V-0805SMT
C195
1UF-16V-0805SMT
C215
100NF-0603SMT
C215
100NF-0603SMT
C186
100NF-0603SMT
C186
100NF-0603SMT
PP10PP10
12
R93
OPEN-0603SMT
R93
OPEN-0603SMT
R91
0R-0603SMT
R91
0R-0603SMT
R88
4_7K-0603SMT
R88
4_7K-0603SMT
C204
100NF-0603SMT
C204
100NF-0603SMT
C184
100NF-0603SMT
C184
100NF-0603SMT
C187 10NF-0603SMT C187 10NF-0603SMT
C193
100NF-0603SMT
C193
100NF-0603SMT
C188
100NF-0603SMT
C188
100NF-0603SMT
C205 10NF-0603SMT C205 10NF-0603SMT
C183
1UF-16V-0805SMT
C183
1UF-16V-0805SMT
C182
100NF-0603SMT
C182
100NF-0603SMT
C202
10NF-0603SMT
C202
10NF-0603SMT
C189 10NF-0603SMT C189 10NF-0603SMT