NEC uPD75P3116 User manual

1994
DATA SHEET
The µ PD75P3116 replaces the µ PD753108’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the
µ PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
development stage using the
µ PD753104, 753106, or 753108, and for use in small-scale production.
Detailed information about functions is provided in the following User’s Manual. Be sure to read it before
designing:
µ PD753108 User’s Manual: U10890E
FEATURES
Compatible with µ PD753108
Memory capacity:
• PROM: 16384 ×8 bits
• RAM: 512 ×4 bits
Can be operated in same power supply voltage range as the mask version µ PD753108
• VDD = 1.8 to 5.5 V
On-chip LCD controller/driver
QTOPTM microcontroller
Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.
This support includes writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number Package
µ PD75P3116GC-AB8 64-pin plastic QFP (14 ×14)
µ PD75P3116GK-8A8 64-pin plastic LQFP (12 ×12)
µ PD75P3116GC-8BS 64-pin plastic LQFP (14 ×14)
Caution This device does not provide an internal pull-up resistor connection function by means of mask
option.
µ PD75P3116
MOS INTEGRATED CIRCUIT
4-BIT SINGLE-CHIP MICROCONTROLLER
The mark shows major revised points.
Document No. U11369EJ3V0DS00 (3rd edition)
Date Published March 2002 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

µ PD75P3116
2Data Sheet U11369EJ3V0DS
FUNCTION OUTLINE
Item Function
Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µ s (main system clock: @ 4.19 MHz)
• 0.67, 1.33, 2.67, or 10.7 µ s (main system clock: @ 6.0 MHz)
• 122 µ s (subsystem clock: @ 32.768 kHz)
Internal memory PROM 16384 ×8 bits
RAM 512 ×4 bits
General-purpose registers • 4-bit manipulation: 8 ×4 banks
• 8-bit manipulation: 4 ×4 banks
I/O ports CMOS input 8 Internal pull-up resistor connection can be specified by software setting: 7
CMOS I/O 20 Internal pull-up resistor connection can be specified by software setting: 12
Shared with segment pins: 8
N-ch open-drain I/O 4 13 V withstanding voltage
Total 32
LCD controller/driver • Segment number selection: 16/20/24 segments (switchable to CMOS I/O ports
in a batch of 4 pins, max. 8 pins)
• Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
Timers 5 channels: • 8-bit timer/event counter: 3 channels
(Can be used as 16-bit timer/event counter, carrier generator,
and timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface • 3-wire serial I/O mode ··· MSB/LSB first switchable
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB) 16 bits
Clock output (PCL) Φ, 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)
Φ, 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)
Buzzer output (BUZ) • 2,4,and32 kHz( mainsystem clock:@ 4.19MHz orsubsystem clock:@ 32.768kHz )
• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)
Vectored interrupts • External: 3
• Internal: 5
Test inputs • External: 1
• Internal: 1
System clock oscillator • Ceramic/crystal oscillator for main system clock
• Crystal oscillator for subsystem clock
Standby function STOP/HALT mode
Power supply voltage VDD = 1.8 to 5.5 V
Package • 64-pin plastic QFP (14 ×14)
• 64-pin plastic LQFP (12 ×12)
• 64-pin plastic LQFP (14 ×14)

µ PD75P3116
3
Data Sheet U11369EJ3V0DS
CONTENTS
1. PIN CONFIGURATION (TOP VIEW)................................................................................................. 4
2. BLOCK DIAGRAM ............................................................................................................................ 6
3. PIN FUNCTIONS ............................................................................................................................... 7
3.1 Port Pins ................................................................................................................................................... 7
3.2 Non-Port Pins ........................................................................................................................................... 9
3.3 Pin I/O Circuits ......................................................................................................................................... 11
3.4 Recommended Connection of Unused Pins ......................................................................................... 13
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 14
4.1 Differences Between Mk I Mode and Mk II Mode................................................................................... 14
4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 15
5. DIFFERENCES BETWEEN µ PD75P3116 AND µ PD753104, 753106, 753108 ............................... 16
6. MEMORY CONFIGURATION ........................................................................................................... 17
7. INSTRUCTION SET .......................................................................................................................... 19
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28
8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28
8.2 Program Memory Write Procedure ......................................................................................................... 29
8.3 Program Memory Read Procedure ......................................................................................................... 30
8.4 One-Time PROM Screening .................................................................................................................... 31
9. ELECTRICAL SPECIFICATIONS .....................................................................................................32
10. CHARACTERISTIC CURVES (REFERENCE VALUES).................................................................. 47
11. PACKAGE DRAWINGS ................................................................................................................... 49
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 52
APPENDIX A. LIST OF µ PD75308B, 753108, AND 75P3116 FUNCTIONS......................................... 54
APPENDIX B. DEVELOPMENT TOOLS................................................................................................ 56
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 65

µ PD75P3116
4Data Sheet U11369EJ3V0DS
1. PIN CONFIGURATION (TOP VIEW)
• 64-pin plastic QFP (14 ×14): µ PD75P3116GC-AB8
• 64-pin plastic LQFP (12 ×12):
µ PD75P3116GK-8A8
• 64-pin plastic LQFP (14 ×14):
µ PD75P3116GC-8BS
Note Always connect the VPP pin directly to VDD during normal operation.
48 S12
47 S13
46 S14
45 S15
44 P93/S16
43 P92/S17
42 P91/S18
41 P90/S19
40 P83/S20
39 P82/S21
38 P81/S22
37 P80/S23
36 P23/BUZ
35 P22/PCL/PTO2
34 P21/PTO1
33 P20/PTO0
64
COM3
63
COM2
62
COM1
61
COM0
60
S0
59
S1
58
S2
57
S3
56
S4
55
S5
54
S6
53
S7
52
S8
51
S9
50
S10
49
S11
1
BIAS 2
VLC0 3
VLC1 4
VLC2 5
P30/LCDCL/MD0 6
P31/SYNC/MD1 7
P32/MD2 8
P33/MD3 9
Vss 10
P50/D4 11
P51/D5 12
P52/D6 13
P53/D7 14
P60/KR0/D0 15
P61/KR1/D1 16
P62/KR2/D2 17
P63/KR3/D3
18
RESET
19
XT1
20
XT2
21
VPP
22
X1
23
X2
24
VDD
25
P00/INT4
26
P01/SCK
27
P02/SO/SB0
28
P03/SI/SB1
29
P10/INT0
30
P11/INT1
31
P12/INT2/TI1/TI2
32
P13/TI0
Note

µ PD75P3116
5
Data Sheet U11369EJ3V0DS
PIN IDENTIFICATIONS
P00 to P03: Port 0 COM0 to COM3: Common output 0 to 3
P10 to P13: Port 1 VLC0 to VLC2: LCD power supply 0 to 2
P20 to P23: Port 2 BIAS: LCD power supply bias control
P30 to P33: Port 3 LCDCL: LCD clock
P50 to P53: Port 5 SYNC: LCD synchronization
P60 to P63: Port 6 TI0 to TI2: Timer input 0 to 2
P80 to P83: Port 8 PTO0 to PTO2: Programmable timer output 0 to 2
P90 to P93: Port 9 BUZ: Buzzer clock
KR0 to KR3: Key return 0 to 3 PCL: Programmable clock
SCK: Serial clock INT0, 1, 4: External vectored interrupt 0, 1, 4
SI: Serial input INT2: External test input 2
SO: Serial output X1, X2: Main system clock oscillation 1, 2
SB0, SB1: Serial data bus 0, 1 XT1, XT2: Subsystem clock oscillation 1, 2
RESET: Reset VPP: Programming power supply
MD0 to MD3: Mode selection 0 to 3 VDD: Positive power supply
D0 to D7: Data bus 0 to 7 Vss: Ground
S0 to S23: Segment output 0 to 23

µ PD75P3116
6Data Sheet U11369EJ3V0DS
2. BLOCK DIAGRAM
P20 to P23
P00 to P03
S0 to S1516
4
4
4
4
4
4
4
4
COM0 to COM34
BIAS
f LCD
V PP V DD RESETVss
CPU clock Φ
Standby
control
X2X1 XT2XT1
System clock
generator
Main Sub
Clock
divider
Clock
output
control
fx/2
N
PCL/PTO2/P22
General-
purpose
register
Data
memory
(RAM)
512 ×4 bits
Bank
SBS
SP (8)
CY
ALU
Program
counter (14)
Program
memory
(PROM)
16384 ×8 bits Decode
and
control
P10 to P13
P30/MD0 to
P33/MD3
P50/D4 to
P53/D7
P60/D0 to
P63/D3
P80 to P83
Port 0
Port 1
Port 2
Port 3
Port 5
Port 6
Port 8
Port 9 P90 to P93
LCD
controller/driver
4S16/P93 to
S19/P90
4S20/P83 to
S23/P80
V LC0
V LC1
V LC2
SYNC/P31
LCDCL/P30
Clocked
serial
interface
SI/SB1/P03
INTCSI
Interrupt
control
INT0/P10
SO/SB0/P02
SCK/P01
TOUT0
INT1/P11
INT4/P00
INT2/P12/TI1/TI2
P60/KR0 to
P63/KR3
Bit sequential
buffer (16)
4
INT1
8-bit
timer/event
counter #1
8-bit
timer/event
counter #2
Cascaded
16-bit
timer/
event
counter
INTT2
INTT1
TI1/TI2/
P12/INT2
PTO1/P21
TOUT0
PTO2/
PCL/P22
INTT0 TOUT0
8-bit
timer/event
counter #0
TI0/P13
PTO0/P20
Basic
interval
timer/
watchdog
timer
INTBT
BUZ/P23 Watch
timer
INTW f LCD

µ PD75P3116
7
Data Sheet U11369EJ3V0DS
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name I/O Alternate Function 8-Bit Status I/O Circuit
Function I/O After Reset TypeNote 1
P00 Input INT4 4-bit input port (Port 0) — Input <B>
Connection of an internal pull-up resistor can be
P01 SCK specified by a software setting in 3-bit units. <F>-A
P02 SO/SB0 <F>-B
P03 SI/SB1 <M>-C
P10 Input INT0 4-bit input port (Port 1) — Input <B>-C
Connection of an internal pull-up resistor can be
P11 INT1 specified by a software setting in 4-bit units.
P10/INT0 can be used to select a noise eliminator.
P12 TI1/TI2/INT2
P13 TI0
P20 I/O PTO0 4-bit I/O port (Port 2) — Input E-B
Connection of an internal pull-up resistor can be
P21 PTO1 specified by a software setting in 4-bit units.
P22 PCL/PTO2
P23 BUZ
P30 I/O LCDCL/MD0 Programmable 4-bit I/O port (Port 3) — Input E-B
Input and output can be specified in 1-bit units.
P31 SYNC/MD1 Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit units.
P32 MD2
P33 MD3
P50Note 2 I/O D4 N-ch open-drain 4-bit I/O port (Port 5) — High M-E
When set to open-drain, the withstanding voltage impedance
P51Note 2 D5 is 13 V.
P52Note 2 D6
P53Note 2 D7
Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.
2. The low-level input leakage current increases when input instructions or bit manipulation instructions are
executed.

µ PD75P3116
8Data Sheet U11369EJ3V0DS
3.1 Port Pins (2/2)
Pin Name I/O Alternate Function 8-Bit Status I/O Circuit
Function I/O After Reset TypeNote 1
P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input <F>-A
Input and output can be specified in 1-bit units.
P61 KR1/D1 Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit units.
P62 KR2/D2
P63 KR3/D3
P80 I/O S23 4-bit I/O port (Port 8) √Input H
Connection of an internal pull-up resistor can be
P81 S22 specified by a software setting in 4-bit unitsNote 2.
P82 S21
P83 S20
P90 I/O S19 Programmable 4-bit I/O port (Port 9) Input H
Connection of an internal pull-up resistor can be
P91 S18 specified by a software setting in 4-bit unitsNote 2.
P92 S17
P93 S16
Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.
2. Do not connect an internal pull-up resistor by software when these pins are used as segment signal outputs.

µ PD75P3116
9
Data Sheet U11369EJ3V0DS
3.2 Non-Port Pins (1/2)
Pin Name I/O Alternate Function Status I/O Circuit
Function After Reset TypeNote 1
TI0 Input P13 External event pulse input to timer/event counter Input <B>-C
TI1 P12/INT2/TI2
TI2 P12/INT2/TI1
PTO0 Output P20 Timer/event counter output Input E-B
PTO1 P21
PTO2 P22/PCL
PCL P22/PTO2 Clock output
BUZ P23 Frequency output (for buzzer or system clock trimming)
SCK I/O P01 Serial clock I/O Input <F>-A
SO/SB0 P02 Serial data output <F>-B
Serial data bus I/O
SI/SB1 P03 Serial data input <M>-C
Serial data bus I/O
INT4 Input P00 Edge detection vectored interrupt input <B>
(valid for detecting both rising and falling edges)
INT0 Input P10 Edge detection vectored interrupt With noise eliminator/ Input <B>-C
input (detection edge is selectable) asynchronous is
INT0/P10 can be used to select a selectable
INT1 P11 noise eliminator. Asynchronous
INT2 Input P12/TI1/TI2 Rising edge detection testable input Asynchronous
KR0 to KR3 I/O P60 to P63 Parallel falling edge detection testable input Input <F>-A
X1 Input — Ceramic/crystal resonator connection for main system — —
clock oscillation. If using an external clock, input the signal
X2 — to X1 and input the inverted signal to X2.
XT1 Input — Crystal resonator connection for subsystem clock oscillation. — —
If using an external clock, input the signal to XT1 and input
XT2 — the inverted signal to XT2. XT1 can be used as a 1-bit (test)
input.
RESET Input — System reset input (low-level active) — <B>
MD0 to MD3 Input P30 to P33 Mode selection for program memory (PROM) write/verify Input E-B
D0 to D3 I/O P60/KR0 to P63/KR3 Data bus for program memory (PROM) write/verify Input <F>-A
D4 to D7 P50 to P53 M-E
VPPNote 2 — — Programmable power supply voltage applied for program — —
memory (PROM) write/verify.
During normal operation, connect directly to VDD.
Apply +12.5 V for PROM write/verify.
VDD — — Positive power supply — —
Vss — — Ground potential — —
Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.
2. The VPP pin does not operate correctly when it is not connected to the VDD pin during normal operation.

µ PD75P3116
10 Data Sheet U11369EJ3V0DS
3.2 Non-Port Pins (2/2)
Pin Name I/O Alternate Function Status I/O Circuit
Function After Reset Type
S0 to S15 Output — Segment signal output Note 1 G-A
S16 to S19 Output P93 to P90 Segment signal output Input H
S20 to S23 Output P83 to P80 Segment signal output Input H
COM0 to COM3 Output — Common signal output Note 1 G-B
VLC0 to VLC2 — — Power supply for driving LCD — —
BIAS Output — Output for external split resistor cut Note 2 —
LCDCLNote 3 Output P30/MD0 Clock output for driving external expansion driver Input E-B
SYNCNote 3 Output P31/MD1 Clock output for synchronization of external expansion driver Input E-B
Notes 1. VLCX (X = 0, 1, 2) is selected as the input source for the display outputs as shown below.
S0 to S23: VLC1, COM0 to COM2: VLC2, COM3: VLC0
2. When the split resistor is incorporated: Low level
When the split resistor is not incorporated: High impedance
3. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

µ PD75P3116
11
Data Sheet U11369EJ3V0DS
3.3 Pin I/O Circuits
The I/O circuits for the µ PD75P3116’s pins are shown in abbreviated form below.
IN
V DD
P-ch
N-ch
V DD
P-ch
N-ch
OUT
Data
Output
disable
IN
V DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Type D
Output
disable
P.U.R. : Pull-Up Resistor
Type A
V DD
P-ch P.U.R.
enable
P.U.R.
P.U.R. : Pull-Up Resistor
IN
V DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Type D
Output
disable
P.U.R. : Pull-Up Resistor
Type B
CMOS standard input buffer Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
Schmitt-triggered input with hysteresis characteristics.
(Continued)
Type A Type D
Type E-BType B
Type B-C Type F-A

µ PD75P3116
12 Data Sheet U11369EJ3V0DS
(Continued)
Type F-B Type H
Type M-CType G-A
Type G-B Type M-E
Output
disable
VDD
P-ch
N-ch
IN/OUT
Data
VDD
P-ch
P.U.R.
enable
P.U.R.
Output
disable
(N)
Output
disable
(P)
P.U.R. : Pull-Up Resistor
IN/OUT
Type G-A
Type E-B
SEG
data
Output
disable
Data
VDD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Output
disable
P.U.R. : Pull-Up Resistor
N-ch
Pull-up resistor that operates only when an input
instruction is executed. (The current flows from
VDD to a pin when the pin is at low level.)
Note
OUT
N-ch
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
N-ch
VLC0
VLC1
SEG
data
VLC2
N-chP-ch
P-ch
N-ch
N-ch
N-chP-ch
P-chN-ch
OUT
VLC0
VLC1
VLC2
COM
data Voltage
controller
Output
disable
Data N-ch
IN/OUT
(+13 V
withstanding
voltage)
VDD
P-ch
Input instruction
Note
P.U.R.
(+13 V
withstand-
ing
voltage)
P-ch
N-ch

µ PD75P3116
13
Data Sheet U11369EJ3V0DS
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Unused Pin Connections
Pin Recommended Connection
P00/INT4 Connect to Vss or VDD.
P01/SCK Input: Independently connect to Vss or VDD via a resistor.
P02/SO/SB0 Output: Leave open.
P03/SI/SB1 Connect to Vss.
P10/INT0 and P11/INT1 Connect to Vss or VDD.
P12/TI1/TI2/INT2
P13/TI0
P20/PTO0 Input: Independently connect to Vss or VDD via a resistor.
P21/PTO1 Output: Leave open.
P22/PTO2/PCL
P23/BUZ
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
P50/D4 to P53/D7 Input: Connect to Vss.
Output: Connect to Vss.
P60/KR0/D0 to P63/KR3/D3 Input: Independently connect to Vss or VDD via a resistor.
Output: Leave open.
S0 to S15 Leave open.
COM0 to COM3
S16/P93 to S19/P90 Input: Independently connect to Vss or VDD via a resistor.
S20/P83 to S23/P80 Output: Leave open.
VLC0 to VLC2 Connect to Vss.
BIAS Connect to Vss only when none of VLC0, VLC1 or VLC2 is used.
In other cases, leave open.
XT1Note Connect to Vss.
XT2Note Leave open.
VPP Always connect to VDD directly.
Note When the subsystem clock is not used, select SOS.0 = 1 (on-chip feedback
resistor not used).

µ PD75P3116
14 Data Sheet U11369EJ3V0DS
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting the stack bank selection (SBS) register for the µ PD75P3116 enables the program memory to be switched
between the Mk I mode and Mk II mode. This function is applicable when using the
µ PD75P3116 to evaluate the
µ PD753104, 753106, or 753108.
When bit 3 of SBS is set to 1: Sets the Mk I mode (supports the Mk I mode for the
µ PD753104, 753106, and 753108)
When bit 3 of SBS is set to 0: Sets the Mk II mode (supports the Mk II mode for the µ PD753104, 753106, and 753108)
4.1 Differences Between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode for the
µ PD75P3116.
Table 4-1. Differences Between Mk I Mode and Mk II Mode
Item Mk I Mode Mk II Mode
Program counter PC13-0
Program memory (bytes) 16384
Data memory (bits) 512 ×4
Stack Stack bank Selectable via memory banks 0 and 1
No. of stack bytes 2 bytes 3 bytes
Instruction BRA !addr1 instruction Not available Available
CALLA !addr1 instruction
Instruction CALL !addr instruction 3 machine cycles 4 machine cycles
execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles
Supported mask ROM products When set to Mk I mode: When set to Mk II mode:
µ PD753104, 753106, and 753108 µ PD753104, 753106, and 753108
Caution The Mk II mode supports a program area exceeding 16 KB for the 75X and 75XL Series. Therefore, this
mode is effective for enhancing software compatibility with products that have a program area of more
than 16 KB.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.

µ PD75P3116
15
Data Sheet U11369EJ3V0DS
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format
of the stack bank selection register.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 100×BNote at the beginning of the program. When using the Mk II mode,
be sure to initialize it to 000×BNote.
Note Set the desired value for ×.
Figure 4-1. Format of Stack Bank Selection Register
Caution SBS3 is set to 1 after RESET input, and consequently the CPU operates in the Mk I mode. When using
instructions for the Mk II mode, set SBS3 to 0 and set the Mk II mode before using the instructions.
SBS3 SBS2 SBS1 SBS0F84H
Address 3 2 1 0
SBS
0
0
1
1
0
1
0
1
Symbol
Stack area specification
Memory bank 0
Memory bank 1
Setting prohibited
0 Be sure to enter “0” for bit 2.
0
1
Mk II mode
Mk I mode
Mode selection specification

µ PD75P3116
16 Data Sheet U11369EJ3V0DS
5. DIFFERENCES BETWEEN µ PD75P3116 AND µ PD753104, 753106, 753108
The µ PD75P3116 replaces the internal mask ROM in the µ PD753104, 753106, and 753108 with a one-time PROM
and features expanded ROM capacity. The
µ PD75P3116’s Mk I mode supports the Mk I mode in the µ PD753104, 753106,
and 753108 and the µ PD75P3116’s Mk II mode supports the Mk II mode in the µ PD753104, 753106, and 753108.
Table 5-1 lists differences between the
µ PD75P3116 and the µ PD753104, 753106, and 753108. Be sure to check the
differences between these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For details of the CPU functions and internal hardware, refer to the User’s Manual.
Table 5-1. Differences Between
µ PD75P3116 and µ PD753104, 753106, and 753108
Item µ PD753104 µ PD753106 µ PD753108 µ PD75P3116
Program counter 12 bits 13 bits 14 bits
Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM
4096 6144 8192 16384
Data memory (×4 bits) 512
Mask options Pull-up resistor for Available Not available
Port 5 (On chip/not on chip can be specified.) (Not on chip)
Split resistor for
LCD driving power supply
Wait time after Available Not available
RESET (Selectable between 217/fXand 215/fX)Note (Fixed to 215/fX)Note
Feedback resistor Available Not available
of subsystem clock (Use/not use can be selected.) (Enable)
Pin configuration Pins 5 to 8 P30 to P33 P30/MD0 to P33/MD3
Pins 10 to 13 P50 to P53 P50/D4 to P53/D7
Pins 14 to 17 P60/KR0 to P63/KR3 P60/KR0/D0 to P63/KR3/D3
Pin 21 IC VPP
Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask
layouts.
Note 217/fX: 21.8 ms at 6.0 MHz operation, 31.3 ms at 4.19 MHz operation
215/fX: 5.46 ms at 6.0 MHz operation, 7.81 ms at 4.19 MHz operation
Caution There are differences in the amount of noise tolerance and noise radiation between flash memory
versions and mask ROM versions. When considering changing from a flash memory version to a mask
ROM version during the process from experimental manufacturing to mass production, make sure to
sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM
versions.

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Data Sheet U11369EJ3V0DS
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
Note Can only be used in the Mk II mode.
Remark Forinstructionsotherthanthosenotedabove,theBRPCDEand BR PCXAinstructionscanbeusedtobranch
to addresses with changes in the PC’s lower 8 bits only.
MBE
MBE
MBE
MBE
MBE
MBE
MBE
RBE
RBE
RBE
RBE
RBE
RBE
RBE
Internal reset start address (higher 6 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (higher 6 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (higher 6 bits)
INT0 start address (lower 8 bits)
INT1 start address (higher 6 bits)
INT1 start address (lower 8 bits)
INTCSI start address (higher 6 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (higher 6 bits)
INTT0 start address (lower 8 bits)
INTT1/INTT2 start address (higher 6 bits)
INTT1/INTT2 start address (lower 8 bits)
Reference table for GETI instruction
0000H
0002H
0004H
0006H
0008H
000AH
000CH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
CALLF
!faddr instruction
entry address
Branch addresses for
the following instructions
•BR !addr
•CALL !addr
•BRA !addr1
•CALLA !addr1
•BR BCDE
•BR BCXA
Branch/call
address
by GETI
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
765 0
Note
Note

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18 Data Sheet U11369EJ3V0DS
Figure 6-2. Data Memory Map
Note Memory bank 0 or 1 can be selected as the stack area.
(32 ×4)
256 ×4
(224 ×4)
128 ×4
0
1
15
000H
01FH
020H
0FFH
100H
1E0H
1DFH
1F7H
1F8H
F80H
FFFH
General-purpose register area
Display data memory
Data area
static RAM
(512 ×4)
Stack areaNote
Peripheral hardware area
Data memory Memory bank
Not incorporated
1FFH
256 ×4
(224 ×4)
(24 ×4)
(8 ×4)

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Data Sheet U11369EJ3V0DS
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the
instruction’s operand representations (for further details, refer to the RA75X Assembler Package Language User’s
Manual (U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and
+ or – symbols are keywords that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further details, refer to the
User’s Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation Coding Format
reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1 BC, DE, HL, XA’, BC’, DE’, HL’
rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem 8-bit immediate data or labelNote
bit 2-bit immediate data or label
fmem FB0H to FBFH, FF0H to FFFH immediate data or label
pmem FC0H to FFFH immediate data or label
addr 0000H to 3FFFH immediate data or label
addr1 0000H to 3FFFH immediate data or label (Mk II mode only)
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H to 7FH immediate data (however, bit 0 = 0) or label
PORTn Port 0 to Port 3, Port 5, Port 6, Port 8, Port 9
IE××× IEBT, IECSI, IET0 to IET2, IE0 to IE2, IE4, IEW
RBn RB0 to RB3
MBn MB0, MB1, MB15
Note When processing 8-bit data, only even-numbered addresses can be specified.

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20 Data Sheet U11369EJ3V0DS
(2) Operation conventions
A: A register; 4-bit accumulator
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
X: X register
XA: Register pair (XA); 8-bit accumulator
BC: Register pair (BC)
DE: Register pair (DE)
HL: Register pair (HL)
XA’: Expansion register pair (XA’)
BC’: Expansion register pair (BC’)
DE’: Expansion register pair (DE’)
HL’: Expansion register pair (HL’)
PC: Program counter
SP: Stack pointer
CY: Carry flag; bit accumulator
PSW: Program status word
MBE: Memory bank enable flag
RBE: Register bank enable flag
PORTn: Port n (n = 0 to 3, 5, 6, 8, 9)
IME: Interrupt master enable flag
IPS: Interrupt priority selection register
IE×××: Interrupt enable flag
RBS: Register bank selection register
MBS: Memory bank selection register
PCC: Processor clock control register
.: Delimiter for address and bit
(××): Data addressed with ××
××H: Hexadecimal data