NXP Semiconductors freescale MC92604 User manual

MC92604
Dual GEt Design
Verification Board
User’s Guide
MC92604DVBUG
Rev. 1, 06/2005

Blank

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor iii
Contents
Contents
Paragraph Page
Number Title Number
Chapter 1
General Information
1.1 Introduction...................................................................................................................... 1-1
1.2 Design Verification Board Features................................................................................. 1-2
1.3 Specifications................................................................................................................... 1-2
1.4 Abbreviation List ............................................................................................................. 1-3
1.5 Related Documentation.................................................................................................... 1-3
1.6 Block Diagram................................................................................................................. 1-4
1.7 Board Components .......................................................................................................... 1-5
1.8 Contact Information......................................................................................................... 1-5
Chapter 2
Hardware Preparation and Installation
2.1 Unpacking Instructions .................................................................................................... 2-1
2.2 MC92604DVB Package Contents ................................................................................... 2-1
2.3 Hardware Preparation ...................................................................................................... 2-2
2.3.1 Setting the Power Supply and Voltage Regulators ...................................................... 2-3
2.3.2 Setting the Voltage Regulators..................................................................................... 2-3
2.4 Reference Clock Source................................................................................................... 2-3
2.4.1 Using the Onboard Oscillators..................................................................................... 2-4
2.4.2 External Reference Clock Source................................................................................ 2-4
2.4.3 Supplying a Clock to the MC92604 ............................................................................ 2-5
2.4.4 3.3V_CLK_OUTnSMA Connectors .......................................................................... 2-5
2.4.5 Clock Frequency Selection .......................................................................................... 2-5
2.5 Interface Components ...................................................................................................... 2-6
2.5.1 Parallel Inputs and Outputs.......................................................................................... 2-6
2.5.1.1 Parallel Inputs .......................................................................................................... 2-7
2.5.1.2 Parallel Outputs ....................................................................................................... 2-7
2.5.2 +VDDQ and Ground (GND) Access Connections........................................................ 2-7
2.5.3 Serial Inputs and Outputs............................................................................................. 2-7
2.6 Special Application Connections..................................................................................... 2-8
2.7 Special Test Connection................................................................................................... 2-8
2.8 Test Traces ....................................................................................................................... 2-8

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
iv Freescale Semiconductor
Paragraph Page
Number Title Number
Chapter 3
Laboratory Equipment and Quick Setup Evaluation
3.1 Recommended Laboratory Equipment ............................................................................ 3-1
3.2 Quick Setup Data-Eye Diagram ...................................................................................... 3-3
3.2.1 Quick Setup Data-Eye Generation and Observation ................................................... 3-3
3.2.1.1 Equipment Setup...................................................................................................... 3-3
3.2.1.2 Parallel Input Connections....................................................................................... 3-4
3.2.1.3 Basic Eye Observation—Test Procedure................................................................. 3-6
3.2.2 Quick Setup Bit Error Rate Checking.......................................................................... 3-8
3.2.2.1 Equipment Setup...................................................................................................... 3-8
3.2.2.2 Parallel I/O Connections.......................................................................................... 3-8
3.2.2.3 Quick Setup BERC Test Procedure ......................................................................... 3-9
Chapter 4
Test Setups
4.1 Serial Link Verification Using a Serial Bit Error Rate Tester (BERT) ............................ 4-1
4.1.1 Test Setup for Full-Speed Mode .................................................................................. 4-2
4.1.2 Test Setup for Half-Speed Modes................................................................................ 4-3
4.2 Jitter Testing..................................................................................................................... 4-4
4.2.1 Jitter Test System Calibration ...................................................................................... 4-4
4.2.2 Reference Clock Jitter Transfer Test............................................................................ 4-5
4.2.3 Reference Clock Jitter Tolerance Test ......................................................................... 4-6
4.2.4 Data Jitter Tolerance Test............................................................................................. 4-7
Appendix A
Connector Signals
A.1 Input: 2×10 (0.100") Connectors.................................................................................... A-1
A.1.1 Control Signal Input Connectors ................................................................................ A-1
A.1.2 Transmitter Parallel Data Input Connectors ............................................................... A-3
A.2 Output: 2×20 (0.100") Connectors................................................................................. A-5
A.3 JTAG Connector ............................................................................................................. A-6
A.4 MDIO Connector ............................................................................................................ A-7
A.5 SFP_CTRL Connector.................................................................................................... A-8
Appendix B
Parts List
B.1 Design Verification Board Parts List ...............................................................................B-1

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor v
Paragraph Page
Number Title Number
Appendix C
Prescaler for Jitter Measurement
C.1 Divide-by-xx Prescaler Description .................................................................................C-1
C.2 Prescaler Components......................................................................................................C-2
Appendix D
Revision History

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
vi Freescale Semiconductor
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MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 1-1
Chapter 1
General Information
1.1 Introduction
This user’s guide describes the MC92604DVB design verification board for the MC92604 integrated
circuit. The design verification board (DVB) facilitates the full evaluation of the MC92604 Dual Gigabit
Ethernet transceiver (GEt). It should be read in conjunction with the MC92604 Dual Gigabit Ethernet
Transceiver Reference Guide. This design verification board is intended for evaluation and testing
purposes only. Freescale does not guarantee its performance in a production environment.
This board was designed to be used with laboratory equipment (pattern generators, data analyzers, BERT,
scopes, etc.) or connected to other evaluation boards. Access to the MC92604 device (verification chip) is
through connectors to each pin, to allow complete in-depth ‘design verification’ testing of the chip design.
This allows the user to check any or all features/functions of the MC92604 GEt device.
The two parallel data input ports and all configuration/control signal pins, are accessed through common
2×10, 0.100" male connectors (headers). The parallel data output ports are accessed through 2×20, 0.100"
connectors. Device JTAG and MDIO port signals are also accessed with separate connectors.
The MC92604 high-speed serial receivers and transmitters are accessed via SMA coaxial connectors for
signal integrity measurements. Gigabit Ethernet fiber media evaluations can be made with the provided
small form-factor pluggable (SFP) socket on the DVB, and an MSA (multi-source agreement) compliant
transceiver. To use this SFP socket, four short coax cables are required to connect the SFP socket to the
device’s transmitter and receiver SMA connectors.
A single 5.0-V power source is required for the DVB operation. All necessary voltages are generated by
regulators onboard. The reference clock for the MC92604 chip may be provided using either an external
clock or the onboard crystal oscillator. Clock drivers on the DVB provide additional clock signals for
triggering analyzer instrumentation and scopes.

General Information
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
1-2 Freescale Semiconductor
1.2 Design Verification Board Features
The functional, physical, and performance features of the MC92604DVB are as follows:
• A single external 5.0-V to onboard regulators supply power to all onboard circuitry.
• Reference clock source is a 250-MHz crystal oscillator or an external clock source.
• IEEE Std 802.3-2002® compliant GMII or TBI interfaces accessible through standard 0.100",
2 row connectors for data generators and analyzers.
• The full-duplex differential data links accessible through SMA connectors.
• Two pairs of 50-Ωtest traces with SMA connections facilitate TDR measurements of the
characteristic impedance of representative board traces.
• Connectors provided for JTAG and MDIO ports
• SFP socket provided for MSA-compliant fiber modules
• IEEE Std 1394b (bilingual) socket provided for standard cable links
1.3 Specifications
The MC92604DVB design verification board specifications are provided in Table 1-1.
Table 1-1. MC92604DVB Design Verification Board Specifications
Characteristics Specifications
Board revision A
External power supply +5 V DC ± 0.5 V DC < 1.5 A typical
Support circuit regulator 3.3 V ± 0.3 V DC
MC92604 core and link I/O regulator 1.8 V ± 0.15 V DC
Interface I/O (VDDQ) regulator 2.5 V ± 0.2 or 3.3 V ± 0.3 V DC
MC92604 package 196 MAPBGA
Operating temperature 0°−30°C
Material FR-4
Dimensions Height 11.2", 287 mm
Width 9.35", 238 mm
Thickness 0.062", 1.6 mm
Conducting layers Four ground planes, one split power plane, three signal routing layers, top and
bottom component layers with some additional signal routing.

General Information
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 1-3
1.4 Abbreviation List
Table 1-2 contains abbreviations used in this document.
1.5 Related Documentation
Related documentation includes the following:
•MC92604 Dual Gigabit Ethernet Transceiver Reference Guide (MC92604RM)
• MC92604DVB schematics
• MC100ES6222 data sheet
• MPC9456 data sheet
• IEEE Std 802.3-2002, Part 3: Carrier sense multiple access with collision detection (CSMA/CD)
access method and physical layer specifications
Table 1-2. Acronyms and Abbreviated Terms
Term Meaning
‘1’ High logic level (nominally 2.5 or 3.3 V)
‘0’ Low logic level (nominally 0.0 V)
BIST Built-in self-test
DVB Design verification board
I/F Interface
MDIO Management data input/output port
MSA Multi-source agreement
N/C No connection
PN Pseudo-noise
PRBS Pseudo random bit sequence
SFP Small form-factor pluggable (fiber optics module)
TAP Test access port
TDR Time delay reflectometry
UIp-p Peak-to-peak unit interval

General Information
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
1-4 Freescale Semiconductor
1.6 Block Diagram
Figure 1-1. MC92604DVB Design Verification Board Block Diagram
MC92604
2×20, 0.100"
2×10, 0.100" Connectors
A_XCLK
+3.3-V
Regulator
+2.5- to 3.5-V
Regulator
+5 V
MC100 MPC9456
Horizontal 50-Ω
Te s t Tr a c e s
Vertical 50-Ω
Te s t Tr a c e s
JTAG
Control
RECV_B
RECV_A
XMIT_A
XMIT_B
MDIO
2×10, 0.100"
SW1
Connectors
CLK_IN
RLINK_A
RLINK_B
XLINK_A
XLINK_B
TST1 TST2
TST5 TST6
TST3 TST7
TST4 TST8
0.100" Connector
+VDDQ/GND
R22V1
R12V
+3.3 V
TPA
GND
+1.8-V
Regulator
R22V
3.3V_CLK_OUT2
3.3V_CLK_OUT3
X-TAL
Osc 3.3V_CLK_OUT4
CLK_B_PG
CLK_A_PG
ES6222
3.3V_CLK_OUT1
LA1
LA2
PG11
PG8
PG9
+V
DDQ
+1.8 V
GEt
B_XCLK
Connectors
SFP
1394b
2×8, 0.100"
Connector
X-TAL
Osc
REF_CLK
RECV_B
Status LEDs
RECV_A
Status LEDs
T8
T7
T6
T3,4
J2
J1
PG11
PG14
PG1 PG3
PG2 PG13
PG4
PG10
PG12
DIFF_CLK_OUT5
DIFF_CLK_OUT6

General Information
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 1-5
1.7 Board Components
Table 1-3 is a list of major components of the MC92604DVB design verification board. A complete parts
listing can be found in Appendix B, “Parts List.”
1.8 Contact Information
For questions concerning the MC92604 design verification kit or to place an order for a kit, contact your
local Freescale field applications engineer.
Table 1-3. Major Board Components
Component Description
MC92604ZT Freescale dual gigabit ethernet transceiver SerDes
2 x 10, 0.100" connectors PG1–PG4, PG8–PG11, and PG13 provide access to the parallel inputs and control signals.
2 x 20, 0.100" connectors LA1–LA2 provide access to the parallel outputs.
2 x 8, 0.100" connectors PG12 and PG14 provide access to the SFP connector and +VDD/ground planes,
respectively.
SMA connectors SMA1–SMA8: Serial transmit and receive connections
TST1–TST8: Impedance test trace connections
CLK_OUT1–CLK_OUT6: Reference clock outputs
CLK_IN: External reference clock input
CLK_A_PG, CLK_B_PG: Input clock connectors
SPF connector J2: Provide connections for SFP MSA optical modules
IEEE Std 1394b bilingual
connector
J1: Provide serial interface to ‘Firewire’ type a or b cable
LT1587 voltage regulators VR33, VR18, and VR1: +3.3 V, +1.8 V, and +VDD voltage regulators
Potentiometers R12V, R22V, R22V1: Potentiometers for setting +3.3 V, +1.8 V, and +VDD voltage levels
XTAL oscillator Y1, Y2: Onboard 250-MHz crystal oscillator
MC100ES6222 clock buffer U2: Divide-by-1 or divide-by-2 clock buffer
MPC9456 clock buffer U3: +3.3-V LVCMOS clock buffer

General Information
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
1-6 Freescale Semiconductor

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 2-1
Chapter 2
Hardware Preparation and Installation
This chapter provides unpacking, hardware preparation, configuration-installation instructions, and
description of the interface components for the MC92604DVB.
2.1 Unpacking Instructions
Unpack the board from the shipping carton. Refer to the packing list and verify that all items are present.
Save the packing material for storing and reshipping of the equipment.
2.2 MC92604DVB Package Contents
Table 2-1 describes the contents of the MC92604DVB kit.
Table 2-1. MC92604DVB Kit Contents
Qty. Item
1MC92604DVB design verification board
1MC92604DVBUG Dual GEt Design Verification Board User’s Guide
1MC92604 Dual Gigabit Ethernet Transceiver Reference Guide
1Complete set of MC92604DVB design verification board schematics
60 0.100" shunts
6Square pin receptacle patch cords

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
2-2 Freescale Semiconductor
2.3 Hardware Preparation
Operation of the MC92604DVB requires proper setup of the power supply and voltage regulators as well
as the reference clock. Figure 2-1 depicts the location of the major components on the board. The
following sections describe the proper setup for the MC92604DVB.
Figure 2-1. Top Side Part Location Diagram
MC92604
+5-V Power
Connectors
Voltage
Horizontal
50-Ω
Te s t Tra c e s
Regulators
Crystal
Oscillator
Clock
Buffers
DIP
Switch
50-Ω
Ver tical
Te s t Tra c e s
2×10
Connectors
2×8
Connector
+3.3-V Power
Connection
2×20
Connectors
2×8
Connector
2×10
Connectors
Serial
Differential
SMA
Connectors
Buffered
Clock
Outputs
VDDQ Power
Connection
+1.8-V Power
Connectors
External
Clock Inputs
SMA Connectors
for SFP Module
SMA Connectors
for 1394 Socket
1394
Socket
SFP Module
Socket
Receiver
Status
LEDs
Diff Clock Buffered Outputs
NOTE:
Freescale has begun the transition of marking Printed Circuit Boards (PCBs) with the Freescale
Semiconductor signature/logo. PCBs may have either Motorola or Freescale markings during the
transition period. These changes will have no impact on form, fit, or function of the current product.

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 2-3
2.3.1 Setting the Power Supply and Voltage Regulators
The MC92604DVB requires a single +5.0-V supply. Fully operational, the board will draw a maximum
current less than 1.5 amps from the +5.0-V supply. Actual current consumption depends on the user set
voltage levels, clock frequencies, use of an SFP module, and the MC92604 operating mode. The board
contains two +5.0-V connection posts and two ground connection posts. These duplicate connections
simplify using a four-wire supply: supply and ground, force and sense.
2.3.2 Setting the Voltage Regulators
The +5.0-V supply is used to power 3 on-board voltage regulators, VR33, VR18, and VR1. These
regulators generate +3.3, +1.8, and +2.5/3.3 V (VDDQ), respectively. The +3.3-V supply provides power
to the oscillator, clock buffer chips, LED drivers, and power source for the SFP socket. This supply can be
varied over the range +3.3 V ± 0.3 V using the R12V potentiometer.
The +1.8-V supply is used to power the MC92604 core logic, transceivers, and on-chip phase-locked loop
(PLL). This regulator can be adjusted over the range +1.8 V ± 0.15 V using R22V.
The VDDQ supply powers the MC92604 control signal, parallel input, and output interface circuitry. This
voltage level is determined by the desired logic interface. The supply can be adjusted using the R22V1
potentiometer from a nominal +2.5 to +3.3 V.
The +3.3-V, +1.8-V, and +VDDQ supplies are accessible via connection posts. Note that these regulators
should be set to voltage limits within the operating ranges described in the MC92604 Dual Gigabit
Ethernet Transceiver Reference Guide. Failure to operate within these ranges could cause damage to the
MC92604. Freescale will not guarantee MC92604 operation beyond the ranges specified. The R12V,
R22V, and R22V1 potentiometers will be factory set for +3.3, +1.8, and +3.3 V, respectively.
2.4 Reference Clock Source
Through a combination of clock buffers, a reference clock is supplied to the MC92604 and several SMA
output connectors. The input reference clock for the MC92604 can be supplied using either an onboard
crystal oscillator, or by directly driving an external reference clock into the board’s clock buffer circuit via
the SMA connector, CLK_IN.
When selecting reference oscillators or external reference frequencies, only those frequencies listed in the
MC92604 Dual Gigabit Ethernet Transceiver Reference Guide, are considered valid. Freescale does not
guarantee operation of the MC92604 at frequencies other than those listed in the reference Guide. DIP
switch settings select either the onboard oscillator or the external reference, as well as the enable for the
clock buffer chips.
The clock circuitry for the MC92604DVB is shown in Figure 2-2.

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
2-4 Freescale Semiconductor
Figure 2-2. DVB Clock Circuitry
2.4.1 Using the Onboard Oscillators
There are two available positions for using onboard oscillators. A standard 14-pin DIP socket is available
on the board to allow the user to easily change frequencies by swapping in crystal oscillators with other
values. The onboard oscillators must be two times (2×) the desired MC92604 reference clock frequency.
The default reference clock frequency oscillator supplied with the board is 250 MHz.
Crystal oscillators used with this board should have +3.3-V complementary PECL outputs capable of
driving a line terminated with 50 Ω. Oscillators conforming to these specifications are available in surface
mount packages and can be soldered onto the underside of the MC92604DVB at location Y2. This
oscillator, Y2, can then be enabled by placing SW1 switch 1 in the ‘on’ position. Both types of crystal
oscillators are available from external vendors in a variety of frequencies. The DVB may be shipped with
either the Y1 or the Y2 oscillator installed. When using the Y2 oscillator, the Y1 oscillator must be
removed from its socket. Once either type of oscillator is installed, SW1 switch 2 must be placed in the
‘on’ position to select the onboard oscillator.
2.4.2 External Reference Clock Source
The input reference clock can also be supplied by using an external reference clock into the clock buffer
circuit on the board via the CLK_IN SMA connector. To supply an external reference clock, switch
number 2 on SW1 must be set to the ‘off’ position. The user must then supply a 1.0-Vp-p input clock via
the SMA connector. The CLK_IN input is AC coupled on the board and, therefore, does not require any
DC biasing of the input signal. This external clock input is also terminated with a 50-Ωimpedance.
Y2
Y1
EN
EN
EN CLK_0 REF_CLK_P
CLK
CLK
DIV 1/2
CSEL
DIV 1/2
DIV by 1
REF_CLK_N
1
7
SW1
U2
U3
MC100ES6222
MPC9456
250-MHz
Oscillator
+
+
CLK_1
CLK_IN
3.3V_CLK_OUT1
3.3V_CLK_OUT2
3.3V_CLK_OUT3
3.3V_CLK_OUT4
TTL_REF_CLK
2
3
4
5
6
DIFF_CLK_OUT5
DIFF_CLK_OUT6
DIV 1/2

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 2-5
2.4.3 Supplying a Clock to the MC92604
The input reference clock, from either the onboard oscillator or an external source, is applied to a
MC100ES6222 clock buffer. This buffer has an input clock select multiplexer, and a programmable
divide-by-one/divide-by-two function. The buffer also contains a master reset (Enable). It is recommended
that this reset, found on SW1 switch 4, be activated, then deactivated after changing the divide-by-xx
switch. This will ensure proper frequency generation.
The MC100ES6222 PECL outputs provide the differential reference clock to the MC92604 (REF_CLK_P
and REF_CLK_N) and also to an MC9456 TTL fanout buffer. When using the default 250-MHz clock,
Y1, switch position 3 must be ‘off’ to do a divide-by-2 to provide the 125 MHz for the MC92604. A
differential output pair, DIFF_CLK_OUT5 and DIFF_CLK_OUT6, is also provided for use with external
equipment.
2.4.4 3.3V_CLK_OUTnSMA Connectors
Four single-ended, 3.3-V level, clock signals are available on SMA connectors to drive other instruments.
Between the MC100ES6222 output and the 4 SMAs, is an MPC9456 which performs a differential PECL
to single-ended +3.3-V LVTTL/CMOS level shift. These CMOS outputs are series terminated on the
board, then connect to the SMA connectors labeled 3.3V_CLK_OUT1, 3.3V_CLK_OUT2,
3.3V_CLK_OUT3, and 3.3V_CLK_OUT4. All of the outputs of the MPC9456 can be disabled by setting
the DIP switch SW1, switch 7 ‘off.’
2.4.5 Clock Frequency Selection
To accommodate the fact that the MC92604 can receive data on both edges of the reference clock (DDR),
but many pieces of the test equipment are single-edge triggered (SDR), the MC92604DVB clock outputs
can be programmed to be either the same as the supplied frequency or half the supplied frequency by
setting SW1, switches 3, 5, and 6 to either ‘on’ (divide-by-one) or ‘off’ (divide-by-2). This allows the
interface between the board and the bench to be either SDR with a double speed clock, or double data rate
(DDR) with a single speed clock.
The SMA outputs 3.3V_CLK_OUT1 and 3.3V_CLK_OUT2 can be programmed by setting SW1,
switch 5 and the 3.3V_CLK_OUT3 and 3.3V_CLK_OUT4 outputs can be programmed by setting SW1,
switch 6. Table 2-2 lists the switch positions and output frequencies. The input frequency, CLK_IN refers
to either the onboard oscillator frequency or the externally applied clock source frequency.
NOTE
Only those frequencies listed in the MC92604 Dual Gigabit Ethernet
Transceiver Reference Guide are considered valid. Freescale does not
guarantee operation of the MC92604 at frequencies other than those listed
in the reference Guide.

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
2-6 Freescale Semiconductor
Figure 2-3 depicts SW1 settings for using an onboard oscillator with the divide-by-two function set for the
MC92604 and 3.3V_CLK_OUTnSMA outputs. The 3.3V_CLK_OUT1 and 3.3V_CLK_OUT2 SMA
outputs are enabled and set to the divide-by-one function. The 3.3V_CLK_OUT3 and 3.3V_CLK_OUT4
SMA outputs are also enabled and are set to the divide-by-two function.
Figure 2-3. Reference Clock Selection Example Switch Settings
2.5 Interface Components
The following sections list the descriptions of the MC92604DVB interface connector components.
2.5.1 Parallel Inputs and Outputs
The MC92604 parallel I/O is supplied by the VDDQ voltage regulator (set for 2.5 or 3.3 V) and has a
rail-to-rail signal swing. The MC92604DVB is shipped with VDDQ set at 3.3 V.
Table 2-2. SW1 Settings and Output Frequencies
SW1
Switch
Switch
Position
REF_CLK_P, REF_CLK_N,
DIFF_CLK_OUT5, DIFF_CLK_OUT6
3.3V_CLK_OUT1,
3.3V_CLK_OUT2
3.3V_CLK_OUT3,
3.3V_CLK_OUT4
3On CLK_IN N/A N/A
Off CLK_IN/2 N/A N/A
5On N/A CLK_IN N/A
Off N/A CLK_IN/2 N/A
6On N/A N/A CLK_IN
Off N/A N/A CLK_IN/2
123456
On
SW1
3.3V_CLK_OUT3, _OUT4 Frequency Select
3.3V_CLK_OUT1, _OUT2 Frequency Select
MC100ES6222 Reset
MC92604 REF_CLK, Frequency select
Onboard/External CLK_IN Select
Alternate Oscillator ENABLE
7
MPC9456 Output ENABLE_BReset
Clk_In/2
Clk_In/2
Reset
Clk_In/2
External
Y1
Enabled
Clk_In
Clk_In
Enabled
Clk_In
Onboard
Y2

Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor 2-7
2.5.1.1 Parallel Inputs
The parallel inputs, both data and control, are accessible via 2×10, 0.100" connectors. Figure 2-4 depicts
the 2×10, 0.100" connector numbering scheme, with pin 1 being labeled on the board. A complete
mapping of the MC92604 inputs to the 2×10, 0.100" connectors is listed in Appendix A, “Connector
Signals.”Note that all even number pins are connected to ground.
Figure 2-4. 2×10, 0.100" Input Connector Numbering Scheme
(Top View)
For a description of the input functionality of the MC92604, refer to the MC92604 Dual Gigabit Ethernet
Transceiver Reference Guide.
2.5.1.2 Parallel Outputs
All parallel outputs, both data and status bits, are present at two 2×20, 0.100" connectors. Figure 2-5
depicts the 2×20, 0.100" output connector numbering scheme, with pin 1 labeled on the board. The parallel
output signals of the MC92604 are 2.5- or 3.3-V logic compatible depending on the setting of the VDDQ
regulator. A complete mapping of the MC92604 outputs to the 2×20, 0.100" connectors is listed in
Appendix A, “Connector Signals.”Note that all even number pins are connected to ground.
Figure 2-5. 2×20, 0.100" Output Connector Number Scheme
(Top View)
For information regarding the MC92604 outputs, refer to the MC92604 Dual Gigabit Ethernet Transceiver
Reference Guide.
2.5.2 +VDDQ and Ground (GND) Access Connections
The MC92604DVB also has a 2×8, 0.100" connector, PG14, with dedicated connections to the +VDDQ
and ground planes. These are useful for biasing parallel input signals using jumper cables. All of the odd
number pins (1, 3, 5, and 7) are connected to the VDDQ plane. All of the even number pins (2, 4, 6, and 8)
are connected to the ground (0.0 V) plane.
2.5.3 Serial Inputs and Outputs
All MC92604 high-speed serial differential inputs and outputs are connected to appropriately labeled pairs
of SMA connectors through board traces with a characteristic impedance of 50 Ω(100-Ωdifferential). The
output driver requires a 50-Ωparallel termination to mid-rail (+0.9 V nominal for +1.8-V supply). If the
termination voltage is not +0.9 V, the signal must be AC coupled. There is no AC coupling (DC blocking)
of the serial outputs on the board. If needed, AC coupling must be done in-line before any termination.
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Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
2-8 Freescale Semiconductor
During all testing, the serial transmitter outputs should be terminated with 50 Ω. This can be done by
connecting the serial transmitter outputs to serial receiver inputs, to any laboratory equipment with 50-Ω
input impedance through in-line AC coupling, or by terminating the outputs with 50-ΩSMA terminations.
2.6 Special Application Connections
There are two sets of special connectors provided for application interface evaluation. A Gigabit Ethernet
SFP socket is provided with SMA connections to connect to the MC92604DVB serial links and then
perform evaluation testing with a fiber optic interface. The user must supply the SFP module. It is not
provided with the MC92604DVB. The SFP socket has it’s own control interface connector, SFP_CTRL.
The mapping of this 2×8, 0.100” connector is listed in Appendix A, “Connector Signals.”
Likewise, a IEEE Std 1394B socket (bilingual version) is provided with SMA connections to connect to
the MC92604 serial links and perform testing with standard patch cords. (Note that there is a slight
impedance mismatch, as the 1394 cables are 110-Ωdifferential.)
2.7 Special Test Connection
The MC92604DVB also contains an oscilloscope PCB test socket, labeled TPA. When the MC92604 is
configured in a PLL factory test mode, this test socket enables special access to the PLL.
NOTE
This test mode is for factory testing purposes only. There are no system
applications for this mode and test socket TPA should remain unconnected
at all times.
2.8 Test Traces
The MCS92610DVB design verification board has both vertical and horizontal 50-Ωtest traces:
• Vertical: TST1–TST5 and TST2–TST6 are 11.82 inches long.
• Horizontal: TST3–TST7 and TST4–TST8 are 9.86 inches long.
These traces can be used to determine the impedance of the board using TDR measurement techniques.
NOTE
These test traces cannot be used as differential pairs. When doing TDR
measurements, observe the difference in propagation delays. This is due to
one trace being on the surface (top or bottom) layer and the other being on
an embedded signal layer.
For the verticle pair, the TST1–TST5 trace is on the bottom surface layer
(10) and TST2–TST6 is on an embedded signal layer (6). The horizontal test
traces have TST3–TST7 located on embedded signal layer (8) and
TST4–TST8 on the top surface layer (1).