NXP Semiconductors freescale K30 Series User manual

K30 Sub-Family Reference Manual
Supports: MK30DN512ZVLK10, MK30DN512ZVMB10
Document Number: K30P81M100SF2RM
Rev. 6, Nov 2011

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Contents
Section Number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................51
1.1.1 Purpose.........................................................................................................................................................51
1.1.2 Audience......................................................................................................................................................51
1.2 Conventions..................................................................................................................................................................51
1.2.1 Numbering systems......................................................................................................................................51
1.2.2 Typographic notation...................................................................................................................................52
1.2.3 Special terms................................................................................................................................................52
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................53
2.2 K30 Family Introduction...............................................................................................................................................53
2.3 Module Functional Categories......................................................................................................................................53
2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................54
2.3.2 System Modules...........................................................................................................................................55
2.3.3 Memories and Memory Interfaces...............................................................................................................56
2.3.4 Clocks...........................................................................................................................................................57
2.3.5 Security and Integrity modules....................................................................................................................57
2.3.6 Analog modules...........................................................................................................................................57
2.3.7 Timer modules.............................................................................................................................................58
2.3.8 Communication interfaces...........................................................................................................................59
2.3.9 Human-machine interfaces..........................................................................................................................60
2.4 Orderable part numbers.................................................................................................................................................60
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................61
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3.2 Core modules................................................................................................................................................................61
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................61
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................64
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................70
3.2.4 JTAG Controller Configuration...................................................................................................................71
3.3 System modules............................................................................................................................................................72
3.3.1 SIM Configuration.......................................................................................................................................72
3.3.2 Mode Controller Configuration...................................................................................................................73
3.3.3 PMC Configuration......................................................................................................................................73
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................74
3.3.5 MCM Configuration....................................................................................................................................76
3.3.6 Crossbar Switch Configuration....................................................................................................................76
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................78
3.3.8 Peripheral Bridge Configuration..................................................................................................................81
3.3.9 DMA request multiplexer configuration......................................................................................................83
3.3.10 DMA Controller Configuration...................................................................................................................86
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................87
3.3.12 Watchdog Configuration..............................................................................................................................88
3.4 Clock Modules..............................................................................................................................................................89
3.4.1 MCG Configuration.....................................................................................................................................89
3.4.2 OSC Configuration......................................................................................................................................90
3.4.3 RTC OSC configuration...............................................................................................................................91
3.5 Memories and Memory Interfaces................................................................................................................................91
3.5.1 Flash Memory Configuration.......................................................................................................................91
3.5.2 Flash Memory Controller Configuration.....................................................................................................94
3.5.3 SRAM Configuration...................................................................................................................................95
3.5.4 SRAM Controller Configuration.................................................................................................................98
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3.5.5 System Register File Configuration.............................................................................................................99
3.5.6 VBAT Register File Configuration..............................................................................................................100
3.5.7 EzPort Configuration...................................................................................................................................100
3.6 Security.........................................................................................................................................................................102
3.6.1 CRC Configuration......................................................................................................................................102
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3.7 Analog...........................................................................................................................................................................102
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................102
3.7.2 CMP Configuration......................................................................................................................................110
3.7.3 12-bit DAC Configuration...........................................................................................................................112
3.7.4 VREF Configuration....................................................................................................................................113
3.8 Timers...........................................................................................................................................................................114
3.8.1 PDB Configuration......................................................................................................................................114
3.8.2 FlexTimer Configuration.............................................................................................................................117
3.8.3 PIT Configuration........................................................................................................................................121
3.8.4 Low-power timer configuration...................................................................................................................122
3.8.5 CMT Configuration......................................................................................................................................124
3.8.6 RTC configuration.......................................................................................................................................125
3.9 Communication interfaces............................................................................................................................................126
3.9.1 CAN Configuration......................................................................................................................................126
3.9.2 SPI configuration.........................................................................................................................................128
3.9.3 I2C Configuration........................................................................................................................................131
3.9.4 UART Configuration...................................................................................................................................132
3.9.5 SDHC Configuration....................................................................................................................................134
3.9.6 I2S configuration..........................................................................................................................................135
3.10 Human-machine interfaces (HMI)................................................................................................................................137
3.10.1 GPIO configuration......................................................................................................................................137
3.10.2 TSI Configuration........................................................................................................................................138
3.10.3 Segment LCD Configuration.......................................................................................................................140
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................143
4.2 System memory map.....................................................................................................................................................143
4.2.1 Aliased bit-band regions..............................................................................................................................144
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4.3 Flash Memory Map.......................................................................................................................................................145
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................146
4.4 SRAM memory map.....................................................................................................................................................146
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................146
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................147
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................151
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................155
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................157
5.2 Programming model......................................................................................................................................................157
5.3 High-Level device clocking diagram............................................................................................................................157
5.4 Clock definitions...........................................................................................................................................................158
5.4.1 Device clock summary.................................................................................................................................159
5.5 Internal clocking requirements.....................................................................................................................................160
5.5.1 Clock divider values after reset....................................................................................................................161
5.5.2 VLPR mode clocking...................................................................................................................................162
5.6 Clock Gating.................................................................................................................................................................162
5.7 Module clocks...............................................................................................................................................................162
5.7.1 PMC 1-kHz LPO clock................................................................................................................................164
5.7.2 WDOG clocking..........................................................................................................................................164
5.7.3 Debug trace clock.........................................................................................................................................165
5.7.4 PORT digital filter clocking.........................................................................................................................165
5.7.5 LPTMR clocking..........................................................................................................................................166
5.7.6 FlexCAN clocking.......................................................................................................................................166
5.7.7 UART clocking............................................................................................................................................167
5.7.8 SDHC clocking............................................................................................................................................167
5.7.9 I2S clocking.................................................................................................................................................167
5.7.10 TSI clocking.................................................................................................................................................168
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Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................171
6.2 Reset..............................................................................................................................................................................171
6.2.1 Power-on reset (POR)..................................................................................................................................172
6.2.2 System resets................................................................................................................................................172
6.2.3 Debug resets.................................................................................................................................................175
6.3 Boot...............................................................................................................................................................................177
6.3.1 Boot sources.................................................................................................................................................177
6.3.2 Boot options.................................................................................................................................................177
6.3.3 FOPT boot options.......................................................................................................................................177
6.3.4 Boot sequence..............................................................................................................................................178
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................181
7.2 Power modes.................................................................................................................................................................181
7.3 Entering and exiting power modes...............................................................................................................................183
7.4 Power mode transitions.................................................................................................................................................184
7.5 Power modes shutdown sequencing.............................................................................................................................185
7.6 Module Operation in Low Power Modes......................................................................................................................185
7.7 Clock Gating.................................................................................................................................................................188
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................189
8.2 Flash Security...............................................................................................................................................................189
8.3 Security Interactions with other Modules.....................................................................................................................190
8.3.1 Security Interactions with EzPort................................................................................................................190
8.3.2 Security Interactions with Debug.................................................................................................................190
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Section Number Title Page
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................191
9.1.1 References....................................................................................................................................................193
9.2 The Debug Port.............................................................................................................................................................193
9.2.1 JTAG-to-SWD change sequence.................................................................................................................194
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................194
9.3 Debug Port Pin Descriptions.........................................................................................................................................195
9.4 System TAP connection................................................................................................................................................195
9.4.1 IR Codes.......................................................................................................................................................195
9.5 JTAG status and control registers.................................................................................................................................196
9.5.1 MDM-AP Control Register..........................................................................................................................197
9.5.2 MDM-AP Status Register............................................................................................................................199
9.6 Debug Resets................................................................................................................................................................200
9.7 AHB-AP........................................................................................................................................................................201
9.8 ITM...............................................................................................................................................................................202
9.9 Core Trace Connectivity...............................................................................................................................................202
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................202
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................203
9.11.1 Performance Profiling with the ETB...........................................................................................................203
9.11.2 ETB Counter Control...................................................................................................................................204
9.12 TPIU..............................................................................................................................................................................204
9.13 DWT.............................................................................................................................................................................204
9.14 Debug in Low Power Modes........................................................................................................................................205
9.14.1 Debug Module State in Low Power Modes.................................................................................................206
9.15 Debug & Security.........................................................................................................................................................206
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................207
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10.2 Signal Multiplexing Integration....................................................................................................................................207
10.2.1 Port control and interrupt module features..................................................................................................208
10.2.2 Clock gating.................................................................................................................................................208
10.2.3 Signal multiplexing constraints....................................................................................................................208
10.3 Pinout............................................................................................................................................................................209
10.3.1 K30 Signal Multiplexing and Pin Assignments...........................................................................................209
10.3.2 K30 Pinouts..................................................................................................................................................214
10.4 Module Signal Description Tables................................................................................................................................215
10.4.1 Core Modules...............................................................................................................................................215
10.4.2 System Modules...........................................................................................................................................216
10.4.3 Clock Modules.............................................................................................................................................217
10.4.4 Memories and Memory Interfaces...............................................................................................................217
10.4.5 Analog..........................................................................................................................................................218
10.4.6 Communication Interfaces...........................................................................................................................219
10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................222
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................225
11.1.1 Overview......................................................................................................................................................225
11.1.2 Features........................................................................................................................................................225
11.1.3 Modes of operation......................................................................................................................................226
11.2 External signal description............................................................................................................................................227
11.3 Detailed signal descriptions..........................................................................................................................................227
11.4 Memory map and register definition.............................................................................................................................227
11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................234
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................236
11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................237
11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................237
11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................238
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11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................239
11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................239
11.5 Functional description...................................................................................................................................................240
11.5.1 Pin control....................................................................................................................................................240
11.5.2 Global pin control........................................................................................................................................240
11.5.3 External interrupts........................................................................................................................................241
11.5.4 Digital filter..................................................................................................................................................242
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................243
12.1.1 Features........................................................................................................................................................243
12.1.2 Modes of operation......................................................................................................................................243
12.1.3 SIM Signal Descriptions..............................................................................................................................244
12.2 Memory map and register definition.............................................................................................................................244
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................246
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................248
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................250
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................252
12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................253
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................254
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................256
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................258
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................258
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................259
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................260
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................263
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................265
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................267
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................268
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12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................270
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................271
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................272
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................273
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................274
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................274
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................275
12.3 Functional description...................................................................................................................................................275
Chapter 13
Mode Controller
13.1 Introduction...................................................................................................................................................................277
13.1.1 Features........................................................................................................................................................277
13.1.2 Modes of Operation.....................................................................................................................................277
13.1.3 MCU Reset...................................................................................................................................................288
13.2 Mode Control Memory Map/Register Definition.........................................................................................................291
13.2.1 System Reset Status Register High (MC_SRSH)........................................................................................292
13.2.2 System Reset Status Register Low (MC_SRSL).........................................................................................293
13.2.3 Power Mode Protection Register (MC_PMPROT).....................................................................................294
13.2.4 Power Mode Control Register (MC_PMCTRL)..........................................................................................296
Chapter 14
Power Management Controller
14.1 Introduction...................................................................................................................................................................299
14.2 Features.........................................................................................................................................................................299
14.3 Low-Voltage Detect (LVD) System.............................................................................................................................299
14.3.1 LVD Reset Operation...................................................................................................................................300
14.3.2 LVD Interrupt Operation.............................................................................................................................300
14.3.3 Low-Voltage Warning (LVW) Interrupt Operation.....................................................................................300
14.4 PMC Memory Map/Register Definition.......................................................................................................................301
14.4.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)........................................................301
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14.4.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)........................................................302
14.4.3 Regulator Status and Control Register (PMC_REGSC)..............................................................................304
Chapter 15
Low-leakage wake-up unit (LLWU)
15.1 Introduction...................................................................................................................................................................305
15.1.1 Features........................................................................................................................................................306
15.1.2 Modes of operation......................................................................................................................................306
15.1.3 Block diagram..............................................................................................................................................307
15.2 LLWU Signal Descriptions...........................................................................................................................................308
15.3 Memory map/register definition...................................................................................................................................309
15.3.1 LLWU Pin Enable 1 Register (LLWU_PE1)..............................................................................................309
15.3.2 LLWU Pin Enable 2 Register (LLWU_PE2)..............................................................................................310
15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3)..............................................................................................312
15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4)..............................................................................................313
15.3.5 LLWU Module Enable Register (LLWU_ME)...........................................................................................314
15.3.6 LLWU Flag 1 Register (LLWU_F1)...........................................................................................................315
15.3.7 LLWU Flag 2 Register (LLWU_F2)...........................................................................................................317
15.3.8 LLWU Flag 3 Register (LLWU_F3)...........................................................................................................319
15.3.9 LLWU Control and Status Register (LLWU_CS).......................................................................................320
15.4 Functional description...................................................................................................................................................321
15.4.1 LLS mode.....................................................................................................................................................322
15.4.2 VLLS modes................................................................................................................................................322
15.4.3 Initialization.................................................................................................................................................323
15.4.4 Low power mode recovery..........................................................................................................................323
Chapter 16
Miscellaneous Control Module (MCM)
16.1 Introduction...................................................................................................................................................................325
16.1.1 Features........................................................................................................................................................325
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16.2 Memory Map/Register Descriptions.............................................................................................................................325
16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)..................................................................326
16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............................................................326
16.2.3 SRAM arbitration and protection (MCM_SRAMAP).................................................................................327
16.2.4 Interrupt status register (MCM_ISR)...........................................................................................................328
16.2.5 ETB counter control register (MCM_ETBCC)...........................................................................................329
16.2.6 ETB reload register (MCM_ETBRL)..........................................................................................................330
16.2.7 ETB counter value register (MCM_ETBCNT)...........................................................................................331
16.3 Functional Description..................................................................................................................................................331
16.3.1 Interrupts......................................................................................................................................................331
Chapter 17
Crossbar Switch (AXBS)
17.1 Introduction...................................................................................................................................................................333
17.1.1 Features........................................................................................................................................................333
17.2 Memory Map / Register Definition...............................................................................................................................334
17.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................335
17.2.2 Control Register (AXBS_CRSn).................................................................................................................338
17.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................340
17.3 Functional Description..................................................................................................................................................341
17.3.1 General operation.........................................................................................................................................341
17.3.2 Register coherency.......................................................................................................................................342
17.3.3 Arbitration....................................................................................................................................................342
17.4 Initialization/application information...........................................................................................................................345
Chapter 18
Memory Protection Unit (MPU)
18.1 Introduction...................................................................................................................................................................347
18.2 Overview.......................................................................................................................................................................347
18.2.1 Block Diagram.............................................................................................................................................347
18.2.2 Features........................................................................................................................................................348
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18.3 Memory Map/Register Definition.................................................................................................................................349
18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................352
18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................354
18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................355
18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................356
18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................357
18.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................357
18.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................360
18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................361
18.4 Functional Description..................................................................................................................................................363
18.4.1 Access Evaluation Macro.............................................................................................................................363
18.4.2 Putting It All Together and Error Terminations...........................................................................................364
18.4.3 Power Management......................................................................................................................................365
18.5 Initialization Information..............................................................................................................................................365
18.6 Application Information................................................................................................................................................365
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................369
19.1.1 Features........................................................................................................................................................369
19.1.2 General operation.........................................................................................................................................369
19.2 Memory map/register definition...................................................................................................................................370
19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................371
19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................375
19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................380
19.3 Functional Description..................................................................................................................................................385
19.3.1 Access support.............................................................................................................................................385
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Chapter 20
Direct memory access multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................387
20.1.1 Overview......................................................................................................................................................387
20.1.2 Features........................................................................................................................................................388
20.1.3 Modes of operation......................................................................................................................................388
20.2 External signal description............................................................................................................................................389
20.3 Memory map/register definition...................................................................................................................................389
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................390
20.4 Functional description...................................................................................................................................................391
20.4.1 DMA channels with periodic triggering capability......................................................................................391
20.4.2 DMA channels with no triggering capability...............................................................................................394
20.4.3 "Always enabled" DMA sources.................................................................................................................394
20.5 Initialization/application information...........................................................................................................................395
20.5.1 Reset.............................................................................................................................................................395
20.5.2 Enabling and configuring sources................................................................................................................395
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................399
21.1.1 Block diagram..............................................................................................................................................399
21.1.2 Block parts...................................................................................................................................................400
21.1.3 Features........................................................................................................................................................402
21.2 Modes of operation.......................................................................................................................................................403
21.3 Memory map/register definition...................................................................................................................................403
21.3.1 Control Register (DMA_CR).......................................................................................................................418
21.3.2 Error Status Register (DMA_ES)................................................................................................................420
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................422
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................424
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................426
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21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................427
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................428
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................429
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................430
21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................431
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................432
21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................433
21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................433
21.3.14 Error Register (DMA_ERR)........................................................................................................................436
21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................438
21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................440
21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................441
21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................442
21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................442
21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................443
21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................444
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................445
21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................446
21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................446
21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................447
21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................447
21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................448
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........449
21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................450
21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................452
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21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................453
21.4 Functional description...................................................................................................................................................454
21.4.1 eDMA basic data flow.................................................................................................................................454
21.4.2 Error reporting and handling........................................................................................................................457
21.4.3 Channel preemption.....................................................................................................................................459
21.4.4 Performance.................................................................................................................................................459
21.5 Initialization/application information...........................................................................................................................464
21.5.1 eDMA initialization.....................................................................................................................................464
21.5.2 Programming errors.....................................................................................................................................466
21.5.3 Arbitration mode considerations..................................................................................................................466
21.5.4 Performing DMA transfers..........................................................................................................................467
21.5.5 Monitoring transfer descriptor status...........................................................................................................471
21.5.6 Channel Linking...........................................................................................................................................472
21.5.7 Dynamic programming................................................................................................................................474
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................477
22.1.1 Features........................................................................................................................................................477
22.1.2 Modes of Operation.....................................................................................................................................478
22.1.3 Block Diagram.............................................................................................................................................479
22.2 EWM Signal Descriptions............................................................................................................................................480
22.3 Memory Map/Register Definition.................................................................................................................................480
22.3.1 Control Register (EWM_CTRL).................................................................................................................480
22.3.2 Service Register (EWM_SERV)..................................................................................................................481
22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................482
22.3.4 Compare High Register (EWM_CMPH).....................................................................................................482
22.4 Functional Description..................................................................................................................................................483
22.4.1 The EWM_out Signal..................................................................................................................................483
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22.4.2 The EWM_in Signal....................................................................................................................................484
22.4.3 EWM Counter..............................................................................................................................................484
22.4.4 EWM Compare Registers............................................................................................................................484
22.4.5 EWM Refresh Mechanism...........................................................................................................................485
Chapter 23
Watchdog Timer (WDOG)
23.1 Introduction...................................................................................................................................................................487
23.2 Features.........................................................................................................................................................................487
23.3 Functional Overview.....................................................................................................................................................489
23.3.1 Unlocking and Updating the Watchdog.......................................................................................................490
23.3.2 The Watchdog Configuration Time (WCT).................................................................................................491
23.3.3 Refreshing the Watchdog.............................................................................................................................492
23.3.4 Windowed Mode of Operation....................................................................................................................492
23.3.5 Watchdog Disabled Mode of Operation......................................................................................................492
23.3.6 Low Power Modes of Operation..................................................................................................................493
23.3.7 Debug Modes of Operation..........................................................................................................................493
23.4 Testing the Watchdog...................................................................................................................................................494
23.4.1 Quick Test....................................................................................................................................................494
23.4.2 Byte Test......................................................................................................................................................494
23.5 Backup Reset Generator...............................................................................................................................................496
23.6 Generated Resets and Interrupts...................................................................................................................................496
23.7 Memory Map and Register Definition..........................................................................................................................497
23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................498
23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................500
23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................500
23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................501
23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................501
23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................502
23.7.7 Watchdog Refresh Register (WDOG_REFRESH)......................................................................................502
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23.7.8 Watchdog Unlock Register (WDOG_UNLOCK).......................................................................................502
23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................503
23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................503
23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................................................................................504
23.7.12 Watchdog Prescaler Register (WDOG_PRESC).........................................................................................504
23.8 Watchdog Operation with 8-bit access.........................................................................................................................504
23.8.1 General Guideline........................................................................................................................................504
23.8.2 Refresh and Unlock operations with 8-bit access........................................................................................505
23.9 Restrictions on Watchdog Operation............................................................................................................................506
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................509
24.1.1 Features........................................................................................................................................................509
24.1.2 Modes of Operation.....................................................................................................................................512
24.2 External Signal Description..........................................................................................................................................513
24.3 Memory Map/Register Definition.................................................................................................................................513
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................514
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................515
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................516
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................517
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................518
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................520
24.3.7 MCG Status Register (MCG_S)..................................................................................................................521
24.3.8 MCG Auto Trim Control Register (MCG_ATC)........................................................................................523
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................523
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................524
24.4 Functional Description..................................................................................................................................................524
24.4.1 MCG Mode State Diagram..........................................................................................................................524
24.4.2 Low Power Bit Usage..................................................................................................................................529
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