NXP Semiconductors LPC55S0x Instruction Manual

1 Introduction
This document guides the hardware engineers to design and test their
LPC55(S)xx processor-based designs. The document provides information
about board layout recommendations and design checklists to ensure first
pass success and avoid any board bring-up problems.
This guide is released with the relevant device-specific hardware
documentation such as data sheets, reference manuals, and application notes
available on nxp.com.
2 LPC55(S)xx family comparison
All LPC55Sxx/LPC55xx family is based on Arm ® Cortex® -M33 core, with
PowerQuad Accelerator and CASPER Accelerator. The S in the middle
of part name means this part provides more security features, such as
TrustZone Support.
Table 1. LPC55Sxx family core features
Family Core
frequency
Dual
core
Power
Quad
CASPER
LPC55S0x/LPC550x 96 MHz — — YES
LPC55S1x/LPC551x 150 MHz — — YES
LPC55S2x/LPC552x 150 MHz YES YES YES
LPC55S6x/LPC556x 150 MHz YES YES YES
Table 2. LPC55Sxx/LPC55xx peripherals
Family Flexcomm 50 MHz HS-
SPI
HS USB FS USB CAN FD SDIO
LPC55S0x/LPC550x 8 1 — — 1—
LPC55S1x/LPC551x 8 1 1 1 1 —
LPC55S2x/LPC552x 8 1 1 1 —1
LPC55S6x/LPC556x 8 1 1 1 —1
Contents
1 Introduction......................................1
2 LPC55(S)xx family comparison.......1
3 Power supply...................................2
3.1 Introduction.................................. 2
3.2 Bulk and decoupling capacitors... 5
4 Clock circuitry..................................6
4.1 Introduction.................................. 6
4.2 Crystal oscillator...........................7
4.3 RTC oscillator.............................. 8
4.4 Common suggestions for the PCB
layout of oscillator circuit............10
5 Boot mode configurations............. 10
5.1 Boot mode selection.................. 11
6 Debug and programing interface...12
6.1 Debug connector pinouts...........14
7 Communication modules...............14
7.1 CAN interface for CAN-FD module
...................................................14
8 Analog........................................... 15
8.1 ADC impedance.........................15
9 Recommendations........................ 16
9.1 Pin descriptions..........................16
9.2 Termination of unused pins....... 17
9.3 PCB............................................18
9.4 General board layout guidelines
...................................................18
10 References....................................23
11 Revision history.............................23
AN13033
Hardware Design Guidelines for LPC55(S)xx Microcontrollers
Rev. 0 — 30 October 2020 Application Note

Table 3. LPC55Sxx/LPC55xx Timers
Family CTimer SCT MRT WWDT Code
WDT
RTC OS-Timer
LPC55S0x/LPC550x 5 1 1 1 1 1 1
LPC55S1x/LPC551x 5 1 1 1 1 1 1
LPC55S2x/LPC552x 5 1 1 1 —1 1
LPC55S6x/LPC556x 5 1 1 1 —1 1
Table 4. LPC55Sxx/LPC55xx analog peripherals
Family 16 bit ADC Comparator 12 bit DAC
LPC55S0x/LPC550x 1 (10ch)/2 Msps 1 (5 inputs) —
LPC55S1x/LPC551x 1 (10ch)/2 Msps 1 (5 inputs) —
LPC55S2x/LPC552x 1 (10ch)/1 Msps 1 (5 inputs) —
LPC55S6x/LPC556x 1 (10ch)/1 Msps 1 (5 inputs) —
Table 5. LPC55Sxx/LPC55xx packages
Family HVQFN 48 HVQFN 64 HTQFP 64 VFBGA 98 HLQFP
100
HLQFP
144
VBGA 196
LPC55S0x/LPC550x / /
LPC55S1x/LPC551x / / /
LPC55S2x/LPC552x / / /
LPC55S6x/LPC556x / / /
For details, see the latest version of the Datasheet and User Manuel on www.nxp.com.
3 Power supply
3.1 Introduction
LPC55Sxx series requires single 1.8 to 3.6 V operation voltage supply.
LPC55S0x/LPC550x, LPC55S1x/LPC551x, LPC55S2x/LPC552x and LPC55S6x/LPC556x internal core’s voltage are supplied
by internal DC/DC regulator, this DC/DC regulator needs external inductance and two or three capacitors. For details, see Using
the DCDC feature (document AN12325).
NXP Semiconductors
Power supply
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 2 / 24

Figure 1. Using internal DC/DC converter
The power and ground pins are described in subsequent sections.
NXP Semiconductors
Power supply
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 3 / 24

Figure 2. Power supply pins
The capacitors in Figure 2 is only for reference.
NOTE
Table 6. Power domains and decoupling capacitors
Power
domain Description Voltage
Bulk/Bypass capacitor for domain Decoupling
capacitor
per pin
CharacteristicsPackage
HTQFP64 VFBGA98 HLFP100
USB0_3V3 USB0 Analog 3.3
V supply 3.3 V 10 uF 10 uF 10 uF 0.1 uF X7R Ceramic
USB1_3V3 USB1 Analog 3.3
V supply 3.3 V 10 uF 10 uF 10 uF 0.1 uF X7R Ceramic
VDD Single power supply
powering I/Os 1.8 - 3.3 V 10 uF 10 uF 10 uF 0.1 uF X7R Ceramic
Table continues on the next page...
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Power supply
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Application Note 4 / 24

Table 6. Power domains and decoupling capacitors (continued)
Power
domain Description Voltage
Bulk/Bypass capacitor for domain Decoupling
capacitor
per pin
CharacteristicsPackage
HTQFP64 VFBGA98 HLFP100
VBAT_DCD
C
Supply of DCDC output
— 22 uF + 100 nF + 47 pF X7R Ceramic
VBAT_PMU
Core supply. For
applications with DCDC
converter, VDD_PMU
and FB are tied at
PCB level.
VDD_PMU Core supply
VDDA Analog supply voltage 1.8 - 3.6 V 10 uF 10 uF 10 uF 0.1 uF X7R ceramic
VREFP ADC positive reference
0.985 -
VDDA
10 uF 10 uF 10 uF 0.1 uF X7R Ceramic
VREFN ADC
negative reference
VSS, VSSA and VREFN must be shorted to GND at package level.
USB0_VSS USB0 analog 3.3
V ground
GND
USB1_VSS USB1 analog 3.3
V ground
VSS Ground
VSS_DCDC Star
ground connections
VSS_PMU Star
ground connections
VSSA Analog ground
FB Feedback node
LX DCDC power
stage output
3.2 Bulk and decoupling capacitors
The effectiveness of the bulk/bypass and the de-coupling capacitors depends on the optimum placement and connection type.
The bulk capacitors are used for a local power supply to the power pin, near the decoupling capacitors and as close as possible
to the assigned reference voltage pin. Decoupling capacitors make the current loop between supply, MCU and reference ground
as short as possible to reduce high frequency transients and noises. Therefore,
• All decoupling capacitors should be placed as close as possible to each of their respective power supply pin.
• The ground side of the decoupling capacitor should have a via to the pad which goes directly down to the internal ground
plane.
NXP Semiconductors
Power supply
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 5 / 24

• The route distance between the capacitors to the power plane should be as short as possible.
Figure 3. Bulk and decoupling capacitor connection
4 Clock circuitry
4.1 Introduction
The LPC55S1x/2x/6x has the following clock sources:
• Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz output (divided
down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to +/- 2% accuracy
over the entire voltage and temperature range.
• 32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 2% accuracy over the entire voltage and
temperature range.
• Internal low power oscillator (FRO 1 MHz) trimmed to +/- 15% accuracy over the entire voltage and temperature range.
• Crystal oscillator with an operating frequency of 16 MHz or 32 MHz. Option for external clock input (bypass mode) for
clock frequencies of up to 24 MHz.
• Crystal oscillator with 32.768 kHz operating frequency. Option for external clock input (bypass mode) for clock frequencies
of up to 100 kHz.
• PLL0 and PLL1 allow CPU operation up to the maximum CPU rate without the need for a high-frequency external clock.
PLL0 and PLL1 can run from the internal FRO 12 MHz output, the external oscillator, internal FRO 1 MHz output, or the
32.768 kHz RTC oscillator.
• Clock output function with divider to monitor internal clocks.
• Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal.
For external crystal oscillator and RTC oscillator, LPC55Sxx have capacitor bank feature. It means that the
stabilizing capacitors can be unsoldered on both 32 K and 16 MHz XTAL. We also suggest users to keep the two
stabilizing capacitors as DNP/Do Not Populate on PCB.
NOTE
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Clock circuitry
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 6 / 24

4.2 Crystal oscillator
In the crystal oscillator circuit, only the crystal (XTAL) and the capacitances, CX1 and CX2, need to be connected externally on
XTAL32M_P and XTAL32M_N pins, as shown in Figure 4. In bypass mode, an external clock (maximum frequency of up to 24 MHz)
can also be connected to XTAL32M_P if XTAL32M_N is left open. External [0 – VH] square signal can be applied on the XTAL32M_P
pin from 0 V to 850 mV.
Figure 4. Reference oscillator circuit
Table 7. Components of the oscillator circuit
Symbol Description
XTAL Quartz crystal/ceramic resonator
CX1 Stabilizing capacitor
CX2 Stabilizing capacitor
For best results, it is very critical to select a matching crystal for the on-chip oscillator. Load Capacitance (CL), Resistance Series
(RS), and Drive Level (DL) are important parameters to consider while choosing the crystal. After selecting the proper crystal, the
external load capacitor CX1 and CX2 values can also be generally determined by the following expression:
Where:
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Clock circuitry
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 7 / 24

• CL: Crystal load capacitance
• CPad: Pad capacitance of the XTAL32M_P and XTAL32M_N pins (~3 pF)
• CParasitic: Parasitic or stray capacitance of external circuit.
Although CParasitic can be ignored in general, the actual board layout and placement of external components influences the optimal
values of external load capacitors. Therefore, it is recommended to fine tune the values of external load capacitors on actual
hardware board to get the accurate clock frequency. For fine tuning, output the RTC Clock to one of the GPIOs and optimize the
values of external load capacitors for minimum frequency deviation. The load capacitors are dependent on the specifications of
the crystal and on the board capacitance. It is recommended to have the crystal manufacturer evaluate the crystal on the PCB.
4.2.1 Crystal Printed Circuit Board (PCB) design guidelines
• Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of
the chip.
• The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines.
• Ensure that the load capacitors CX1 and CX2, in case of third overtone crystal usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitic as
small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.
4.3 RTC oscillator
In the RTC oscillator circuit, only the 32.768 kHz crystal (XTAL) and the capacitances, CX1 and CX2, need to be connected
externally on XTAL32K_P and XTAL32K_N, as shown in Figure 5.
In bypass mode, an external clock (maximum frequency of up to 100 kHz) can also be connected to XTAL32K_P if XTAL32K_N is
left open. External [0 – VH] square signal can be applied on the XTAL32K_P pin with 1.1 V +/-10%
An external signal below 1.0 V or above 1.2 V cannot be applied.
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Clock circuitry
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 8 / 24

Figure 5. Reference oscillator circuit
For best results, it is very critical to select a matching crystal for the on-chip oscillator. Load Capacitance (CL), Resistance Series
(RS), and Drive Level (DL) are important parameters to consider while choosing the crystal. After selecting the proper crystal, the
external load capacitor CX1 and CX2 values can also be generally determined by the following expression:
Where:
• CL: Crystal load capacitance
• CPad: Pad capacitance of the XTAL32K_P and XTAL32K_N pins (~3 pF)
• CPrasitic: Parasitic or stray capacitance of external circuit
Although CParasitic can be ignored in general, the actual board layout and placement of external components influences the optimal
values of external load capacitors.
Therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate
clock frequency. For fine tuning, output the RTC Clock to one of the GPIOs and optimize the values of external load capacitors
for minimum frequency deviation.
4.3.1 RTC PCB design guidelines
• Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of
the chip.
• The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines.
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Clock circuitry
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 9 / 24

• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground
plane.
• Loops must be made as small as possible to minimize the noise coupled in through the PCB and to keep the parasitics as
small as possible.
• Lay out the GND pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.
4.4 Common suggestions for the PCB layout of oscillator circuit
The crystal oscillator is an analog circuit and must be designed carefully and according to the analog-board layout rules:
• It is recommended to send the PCB to the crystal manufacturer to determine the negative oscillation margin as well as
the optimum regarding CXTAL and CEXTAL capacitors. The datasheet includes recommendations for the tank capacitors
CXTAL and CEXTAL. These values together with the expected PCB, pin, etc. stray capacity values should be used as an
initial point.
• The crystal or resonator oscillator is sensitive to stray capacitance and noise from other signals. It should be placed away
from high-frequency devices and traces in order to avoid and reduce the capacitive coupling between the XTAL and
EXTAL pins and their PCB traces.
• The main oscillation loop current is flowing between the crystal and the load capacitors. This signal path (Oscillator to
CEXTAL to CXTAL to Oscillator) should be kept as short and symmetric tracing as possible. Hence, both the capacitor's
ground connections should be direct always to the closer VSS pin using the cooper-pour ground plane and several vias to
the ground internal layer in the PCB are mandatory.
• The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
Figure 6 shows the recommended placement and routing for the oscillator layout.
Figure 6. Suggested crystal oscillator layout
5 Boot mode configurations
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Boot mode configurations
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Application Note 10 / 24