NXP Semiconductors KE17Z Series User manual

1 Introduction
Touch Sensing Interface (TSI) provides touch sensing detection on capacitive
touch sensors. The external capacitive touch sensor is typically formed on
PCB. The sensor electrodes are connected to TSI input channels through the
I/O pins in the device.
1.1 KE17Z dual TSI
KE17Z MCU has two TSI modules. It supports two kinds of touch
sensing methods: self-capacitance (also called self-cap) mode and mutual
capacitance (also called mutual-cap) mode.
The dual-TSI technology of KE17Z MCU supports up to 50 touch channels. The
two TSI modules not only increase the number of touch electrode, but also work
in parallel to increase the scanning efficiency of touch electrode and save the
scanning time.
To enhance the liquid tolerance and improve the driving ability, each TSI
module has three shield channels, up to 25 touch channels for self-cap mode,
and up to 6 × 6 touch channels for mutual-cap mode. Both mentioned methods
can be combined on one single PCB, while only the lower 12 TSI channels
TSI[0:11] can be used for mutual mode.
TSI[0:5] are TSI TX pins and TSI[6:11] are TSI RX pins in
mutual mode.
NOTE
• In the self-capacitive mode, developers can use these 50 channels to
design 50 (25 × 2) touch electrodes.
• In the mutual-capacitive mode, design options expand to up to 72 (6 × 6
× 2) touch electrodes.
In some use cases, such as, a multi-burner induction cooker with touch controls
or touch keyboards, the MCUs can support touchscreen designs scaling up
to 98 touch electrodes (26 electrodes using self-capacitance + 72 electrodes
using mutual channels).
1.2 TSI model comparison of KE17Z parts
Table 1 lists the number of TSI channels corresponding to different parts of
KE17Z. These parts all support dual TSI modules.
Contents
1 Introduction......................................1
1.1 KE17Z dual TSI............................1
1.2 TSI model comparison of KE17Z
parts.............................................1
1.3 TSI model comparison between
KE17Z parts and KE15Z parts.....3
1.4 KE17Z dual TSI evaluation board
.....................................................6
2 TSI self-cap mode introduction....... 7
2.1 Self-cap touch sensor.................. 7
2.2 Self-cap sensing mode................ 7
2.3 Clock generation..........................9
2.4 TSI scan time and scan result
accumulation..............................12
2.5 Scan time and sensitivity boost
tests in self-cap mode................15
3 TSI Mutual-cap mode....................18
3.1 Mutual-cap sensor..................... 18
3.2 Clock generation in mutual-cap
mode..........................................19
3.3 Mutual-cap sensing mode..........20
3.4 Sensitivity boost in mutual-cap
mode..........................................23
4 Shield channels.............................24
4.1 Principle of self-cap mode to
improve liquid tolerance by
enabling shield channels........... 24
4.2 Advantages of three shield
channels of KE17Z of each TSI. 25
4.3 Principle of mutual-cap mode to
improve liquid tolerance.............25
5 Hardware design guide................. 25
5.1 Electrode design........................ 26
5.2 PCB trace routing.......................26
5.3 Ground plane............................. 27
5.4 Overlay of the touch electrode...28
5.5 Electrodes placement................ 30
5.6 Hardware checklist.....................30
5.7 X-KE17Z-TSI-EVB touch electrode
patterns design.......................... 30
6 References....................................34
7 Revision history.............................34
Legal information.................................... 35
KE17ZDTSIUG
KE17Z Dual TSI User Guide
Rev. 0 — 05 May 2022 User Guide

Table 1. KE17Z parts supporting dual TSI modules
Product Memory Package IO and ADC channel HMI
Part number Flash
(kB)
SRAM
(kB) Pin count Package GPIOs GPIOs (INT/HD)
ADC
channels TSI
MKE17Z256VLL7 256 48 100 LQFP 89 89/8 16 50 ch
MKE17Z256VLH7 256 48 64 LQFP 58 58/8 16 47 ch
MKE17Z256VLF7 256 48 48 LQFP 42 42/6 11 31 ch
MKE17Z128VLL7 128 32 100 LQFP 89 89/8 16 50 ch
MKE17Z128VLH7 128 32 64 LQFP 58 58/8 16 47 ch
MKE17Z128VLF7 128 32 48 LQFP 42 42/6 11 31 ch
Table 2. KE17Z dual TSI channels for different package
Product TSI TSI0 TSI1
KE17Z
100LQFP 50 ch 25 channels
TSI0[0: 24]
25
channels
TSI1[0: 24]
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE17Z
64LQFP
47 ch 22
channels
TSI0[0: 12], [16: 24]
25
channels
TSI1[0: 24]
No CH13, CH14, CH15
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE17Z
48LQFP
31 ch 15
channels
No CH2, CH3, CH4, CH5, CH13,
CH14, CH15, CH19, CH20,
CH21 16
channels
No CH8, CH9, CH10, CH13,
CH14, CH19, CH20, CH21, CH22
One shield channel: CH12 Two shield channels: CH4, CH12
TX[0:1], RX[6:11] TX[0:5], RX[7,11]
Figure 1 shows the assignment of dual TSI channels on the three packages of KE17Z. Compared with the KE17Z 100LQFP, the
TSI channels marked in yellow are not supported in the KE17Z 64 LQFP. The ones marked in yellow and red are TSI channels
not supported in K17Z 48 LQFP.
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Introduction
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Figure 1. TSI channel assignment of KE17Z 100 LQFP, KE17Z 64 LQFP, and KE17Z 48 LQFP
1.3 TSI model comparison between KE17Z parts and KE15Z parts
Table 3. KE17Z dual TSI channels for different package
Product TSI TSI0 TSI1
KE15Z
100LQFP
MKE15Z256VLL7
MKE15Z128VLL7
25 ch 25
channels
TSI0[0 : 24]
One shield channel: CH12
TX[0:5], RX[6:11]
KE17Z
100LQFP
MKE17Z256VLL7
50 ch 25
channels
TSI0[0: 24]
25
channels
TSI1[0: 24]
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
Table continues on the next page...
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Table 3. KE17Z dual TSI channels for different package (continued)
Product TSI TSI0 TSI1
MKE17Z128VLL7 TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE15Z
64LQFP
MKE15Z256VLH7
MKE15Z128VLH7
25 ch 25
channels
TSI0[0: 24]
One shield channel: CH12
TX[0:5], RX[6:11]
KE17Z
64LQFP
MKE17Z256VLH7
MKE17Z128VLH7
47 ch 22
channels
TSI0[0 : 12], [16 : 24]
25
channels
TSI1[0:24]
No CH13,CH14,CH15
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE15Z/KE16Z
48LQFP
MKE16Z64VLF4
MKE15Z64VLF4
MKE16Z32VLF4
MKE15Z32VLF4
25 ch 25
channels
TSI0[0: 24]
One shield channel: CH12
TX[0:5], RX[6:11]
KE17Z
48LQFP
MKE17Z256VLF7
MKE17Z128VLF7
47 ch 22
channels
TSI0[0 : 12], [16 : 24]
25
channels
TSI1[0: 24]
No CH13, CH14, CH15
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
For the KE17Z in 100LQFP, 64LQFP, and 48LQFP packages, its pin assignment is compatible with the KE15Z. That is, the
number and position of GPIO pins are the same. But the TSI channel assignment of KE17Z is different from KE15Z. To migrate
touch code from KE15Z to KE17Z, see Figure 2, Figure 3, and Figure 4 for the TSI channel assignment. For more migration details,
see Migration Guide from KE15Z256 to KE17Z256 (document AN13429).
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Figure 2. TSI pin assignment comparison of 100 LQFP between KE15Z and KE17Z
Figure 3. TSI pin assignment comparison of 64 LQFP between KE15Z and KE17Z
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Figure 4. TSI pin assignment comparison of 48 LQFP between KE15Z/KE16Z and KE17Z
1.4 KE17Z dual TSI evaluation board
X-KE17Z-TSI-EVB is a touch sensing reference design including multiple touch patterns based on the 5 V Robust KE17Z MCU
of NXP. It has dual-TSI modules and supports up to 50 touch channels, all demonstrated on the board.
Figure 5. X-KE17Z-TSI-EVB, KE17Z dual TSI evaluation board
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Introduction
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2 TSI self-cap mode introduction
The sensor structure and electric field distribution between self-cap sensor and mutual-cap sensor are different.
2.1 Self-cap touch sensor
Ground Hatch
Electrode Ground Hatch
Ground Hatch
PCB
Dielectric Overlay
Cs Cs
ΔCs
via
Routing I/O pin
Self-cap
electrode
Ground hatch
Figure 6. Self-cap touch sensor structure and electric field
In self-cap mode, TSI requires only one pin for each touch sensor. As shown in Figure 6, capacitance exists between electrode
to system ground. Touch changes field through human body and creates extra capacitance.
Self-cap touch sensor structure:
• Cs: Intrinsic self-capacitance. 10 - 50 pF as usual.
• ΔCs: Touch generated self-capacitance. 0.3 - 2 pF as usual.
• Sensitivity of sensor: ΔCs/Cs. 1 - 10 % as usual.
2.2 Self-cap sensing mode
There are three modes of self-cap mode:
• Basic self-cap mode
• Noise cancellation mode
• Sensitivity boost mode
The noise cancellation mode and sensitivity boost mode cannot be enabled at same time. The following describes the
three modes.
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2.2.1 Basic self-cap sensing mode
sample
ph 1
Digital SINC
filter
Icx
Cx
XIN*Icx
ph 2
Vcx
current mirror: input
TSIx_MODE[S_XIN]
current mirror: charge
TSIx_MODE[S_XCH]
XCH*XIN*Icx
Ci 90pF
Transconductance Amplifier
charge
-
+
Vp
Vm
TSIx_GENC[DVOLT]
Counts
TSIx_DATA[TSICNT]
Vci
IN CHIP
OUT CHIP
I/O
Comparator
Cx = Cs + ΔCs,
Cx is the capacitance of self-cap electrode.
Cs is the self capacitance between touch electrode and ground.
ΔCs is touch generated capacitance.
If no touch happens, Cx = Cs.
TSIx_SINC[CUTOFF]
TSIx_SINC[ORDER]
TSIx_SINC[DECIMATION]
vddlv vdd3v
Figure 7. TSI basic self-cap mode HW architecture
Figure 8. TSI self-cap timing
Inside the TSI IP module, the TSI scan is operated by non-overlapping clock ph1/ph2 and trans-conductance amplifier.
There are two phases controlled by the ph1 and ph2 respectively for the TSI scan module:
• Sample phase: The switch ph1 controls the sample phase. When ph1 turns on, the external touch electrode Cx is charged
by vdd3v.
• Charge phase: The switch ph2 controls the charge phase. When ph1 turns off and then ph2 turns on, the charge on the
capacitor Cx flows to the internal integrated capacitor Ci, which generates the average current Icx.
Via the trans-conductance amplifier, the Icx are amplified to charge Ci and the voltage Vci ramps on Ci. Vci is detected by
comparator, when the Vci becomes larger than the pre-setting Vp, Ci is discharged to negative reference Vm. Then next scanning
cycle continues.
The digital SINC filter controls the scan cycle. The digital SINC filter is a digital decimation filter for filtering out the low frequency
noise from EMC. The digital SINC detects and accumulates the filter number of Vci ramp up steps in per cycle. Digital SINC filter
outputs totally counter which can be read from TSIx_DATA[TSICNT]. The software uses the counts to detect touch.
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When touch happens, input capacitance Cx increases. The charging current of Ci becomes larger and then the number of Vci ramp
up steps is reduced. The output count of digital SINC filter is reduced, so the value of TSIx_DATA[TSICNT] is decreased.
2.2.2 Noise cancellation mode of self-cap
If touch sensor encounters strong low frequency noise, noise cancellation can be activated by setting TSIx_MODE[S_NOISE].
In the noise cancellation mode, vdd3v, and vddlv (1.2 V) are dual sample voltages. Two phases exist in noise
cancellation architecture:
• Charging phase of Ci when vdd3v is on and vddlv is off
• Discharging phase of Ci when vdd3v is off and vddlv is on
Two switching clock cycles are cost to samples twice which includes charging phase (sampling vdd3v) and discharging phase
(sampling vddlv). The input current of Ci equal to charging phase current abstract discharging phase current. At the end of each
second phase, low frequency noise is subtracted. In a long integration period, the noise induced error can be canceled.
2.2.3 Sensitivity boost mode of self-cap
The larger parasitic capacitance causes the low sensitivity. The low sensitivity results in the difficulty to recognize the touch event.
For example, when the touch overlay is very thick, it becomes very hard to detect a touch event correctly.
To increase the sensitivity, enable sensitivity-boost feature by removing part parasitic capacitance virtually. So touch works well
under the thicker overlay with sensitivity boost enabled.
The capacitance to be removed cannot be configured more than the intrinsic capacitance of the touch key.
Otherwise, it causes the sensitivity invalid.
NOTE
2.3 Clock generation
The clock generation determines the TSI scan speed. The maximum frequency of TSI is about 10 MHz.
The TSI module is only clocked by the main clock, which is generated by TSI module itself without any other external clock source.
The main clock has four ranges of frequency. It can be divided into the switching clock which is used to control the ph1/ph2
switching speed and finally determines the whole scan time, as shown in Figure 9.
SSC
Main Clock
20.72MHz
16.65MHz
13.87MHz
11.91MHz
SSC_MODE
PRBS SSC
No SSC
Up-down
counter SSC
Touch Key
Switching Clock
SSC_MODE = 10b
SSC_MODE = 00b/01b
basic
advanced
1/ 2
Main Clock
Prescale + 1
Figure 9. Block diagram of clock generation
• When SSC_MODE = 10b, the switching clock is divided from main clock directly, as the basic clock generation.
• When SSC_MODE = 00b/01b, the switching clock is generated from SSC module, as the advanced clock generation.
2.3.1 Basic clock generation
Equation 1 si the basic clock generation, when TSIx_SSC0[SSC_MODE] = 10b.
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SwitcℎingClock= MainClock
SSC_PRESCALE_NUM + 1  ×  1 2
Equation 1.
Table 4. Main clock setting
Register Value Main clock (MHz)
TSI_MODE[SETCLK]
00 20.72
01 16.65
10 13.87
11 11.91
Table 5. Divider setting
Register Value SSC_PRESCALE_NUM + 1
TSI_SSC0.SSC_PRESCALE_NUM[7:0]
00000000 divide 1
00000001 divide 2
… …
11111111 divide 256
There is an example of the basic clock generation, the main clock as 16.65 MHz, the divider as 16, and the result of switching clock
is 1.04 MHz.
To use no SSC switching clock with frequency of 1 MHz,
• Set SETCLK < 1:0 > to ‘01b’ to get main clock = 16.65 MHz.
• Set SSC_MODE < 1:0 > to ‘10b’ to disable SSC function.
• Set SSC_PRESCALE_NUM < 7:0 > to ‘00000111b’ to get division 8. When SSC mode is disabled, the frequency is main
clock/[(SSC_PRESCALE_NUM+1) × 2] .
• Keep other registers in TSIx_SSC0, TSIx_SSC1, and TSIx_SSC2 as default value.
SwitcℎingClock=MainClock
Divider  × 1
2=16.65MHz 8 × 1 2 = 1.04MHz
2.3.2 Advanced clock generation, spread spectrum clocking
The Spread Spectrum Clocking (SSC) increases the noise immunity to RF interference and spreads the emissions.
With the SSC enabled (TSIx_SSC0[SSC_MODE] = 00/01b), the switching clock is generated by the SSC module, other than the
direct divided main clock.
In the Self-cap mode, changing the SSC charge time does not affect the final scan result. It changes the total scan time as it
changes the switching clock frequency.
If SSC mode is enabled, the timing of the switching clock generation is as shown in Figure 10.
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Main Clock
Divider value:
1 - 256
1 clock cycle
t1 t2 t3
Divider Main Clock before
going to SSC logic
SSC output
Figure 10. Timing of the advance clock generation with SSC enabled
As shown in Figure 10, t1 and t2 determine the SSC output 1's period and t3 determines the SSC output 0's period.
Equation 2 shows the advanced clock generation, with SSC enabled when TSIx_SSC0[SSC_MODE] = 00/01b.
SwitcℎingClock= MainClock
SSC_PRESCALE_NUM + 1  × t1+t2+t3
Equation 2.
• When TSIx_SSC0[SSC_MODE] = 00b, t2 can be random (PRBS).
• When TSIx_SSC0[SSC_MODE] = 01b, t2 can be the range of TSIx_SSC2[MOVE_NOCHARGE_MIN] to
TSIx_SSC2[MOVE_NOCHARGE_MAX].
The generation of switching clock includes:
• The switching clock can be generated as a pseudo random clock using the Pseudo-Random Binary Sequence (PRBS)
method by setting TSI_SSC0[SSC_MODE] = 00. t2 is configured as the random width.
Table 6. TSI_SSC0[SSC_MODE] = 00, PRBS mode
Variable Register Clock cycle Description
t1 TSIx_SSC0[BASE_NOCHARGE_NUM] 1 - 16 SSCHighWidth
t2 TSIx_SSC0[PRBS_OUTSEL] 2 - 15 SSCHighRandomWidth
t3 TSIx_SSC0[CHARGE_NUM] 1 - 16 SSCLowWidth
• Switching Clock can be generated in a configurable up-down counter method by setting TSI_SSC0[SSC_MODE] = 01. The
range of t2 is limited by TSI_SSC2[MOVE_NOCHARGE_MIN] and TSI_SSC2[MOVE_NOCHARGE_MAX].
Table 7. TSI_SSC0[SSC_MODE] = 01, up-down counter mode
Variable Register Clock cycle Description
t1 TSI_SSC0[BASE_NOCHARGE_NUM] 1 - 16 SSCHighWidth
t2 TSI_SSC2[MOVE_NOCHARGE_MIN]
TSI_SSC2[MOVE_NOCHARGE_MAX]
MAX-MIN SSCHighCounterWidth
Table continues on the next page...
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Table 7. TSI_SSC0[SSC_MODE] = 01, up-down counter mode (continued)
Variable Register Clock cycle Description
t3 TSI_SSC0[CHARGE_NUM] 1 ~ 16 SSCLowWidth
There is an example of the advance clock generation attached below.
To use PRBS mode SSC switching clock with central frequency of 1 MHz.
• Set SETCLK<1:0> to ‘01b’ to get main clock = 16.65 MHz.
• Set SSC_PRESCALE_NUM<7:0> to ‘0b’ to get division 1. The divided main clock is 16.65 MHz.
• Set SSC_MODE<1:0> to ‘00b’ to enable PRBS SSC mode. SSC t2 is random.
• Set BASE_NOCHARGE_NUM<3:0> to ‘0100b’ to set t1 = 5. The basic length of SSC output bit 1’s period is five clock
cycle of the divided main clock.
• Set PRBS_OUTSEL<3:0> to ‘0110b’ to set t2 range from 1 to 6. The average of t2 is 3.5. t2 is the random length of SSC
output bit 1’s period. It is 3.5 clock cycle of the divided main clock.
• Set CHARGE_NUM<3:0> to ‘0110b’ to set t3 = 7. The basic length of SSC output bit 1’s period is seven clock cycle of the
divided main clock.
• Keep other registers in TSIx_SSC0, TSIx_SSC1, and TSIx_SSC2 as default value.
• Then, switching clock = 16.65 MHz/[(5+3.5+7) * (0 + 1)] = 1.074 MHz. Switching clock is spectrum spread pulse.
SwitcℎingClock
=  MainClock
SSC_PRESCALE_NUM + 1 × SSCHigℎWidtℎt1 + SSCHigℎRandomWidtℎt2 + SSCLowWidtℎt3
=16.65MHz
0+1 × 5+3.5+7  = 1.074MHz
2.4 TSI scan time and scan result accumulation
TSI supports multiple scans per channel. That is, to get better Signal-to-Noise Ratio (SNR) and resolution, TSI performs multiple
scans. The final scan result is accumulated in TSI_DATA[TSICNT] counter as the NSTEP multiplied by number of scans, and the
scan time is multiple of single TSI scan time.
With higher Decimation, the number of scans is increased. The result is the physically longer TSI counter
accumulation and increased resolution.
If the Order is higher than 1, then the scan number physically executed by TSI is smaller than the scan number
calculated by HW. It is beneficial to get the higher resolution.
NOTE
2.4.1 TSI single scan process
Figure 11 shows one process that the step voltage (Vci) reaches threshold Vp of comparator from Vm. If Vci reaches the threshold
Vp, the voltage VCI is discharged to Vm for next scanning. The step voltage (Vci) depends on touch sensor and IP configuration.
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Figure 11. One process of the step voltage (Vci) reach threshold Vp of comparator
1. Calculate NSTEP in basic self-cap mode.
Equation 3 is the basic equation of the self-cap mode. NSTEP is the Vci steps of TSI single scan in self-cap mode.
NSTEP =  Ci ×Vp − Vm
vdd3v×Cs ×S_XIN ×S_XCH
Equation 3.
Equation 4 is the basic equation of the scan time. Tnstep is the time cost of TSI single scan in self-cap mode.
Tnstep=NSTEP ×1
Fsw
Equation 4.
• Ci: Typical 90 pF. The integrated capacitance inside TSI module.
• Vdd3v: Typical 3.3 V. PMC internal voltage regulator generates the analog power supply voltage.
• Vp, Vm: Configurable, dual reference voltage which can be configured by TSIx_GENCS[DVOLT].
• S_XIN, S_XCH: Configurable, the parameters of analog front end, configured TSIx_MODE[S_XIN],
TSIx_MODE[S_XCH].
• Fsw: Configurable, the switching clock frequency.
• Cs: The self-capacitance of touch sensor.
2. Equation 5 is a new equation to calculate NSTEP when noise cancellation mode is enabled.
NSTEP =  2 × Ci ×Vp − Vm
vdd3v − vddlv ×Cs ×S_XIN ×S_XCH
Equation 5.
Vddlv: is internal power supply voltage. Typical 1.2 V.
3. Calculate NSTEP in basic self-cap mode.
The TSI self-cap mode implements the sensitivity boost by canceling the external intrinsic capacitance. The value of the
capacitance to be canceled ranges from 2.5 pF to 20 pF, which is configurable in register TSI_MODE[S_CTRIM].
For example, given the intrinsic capacitance of the touch electrode is 20 pF (it can be calculated by NSTEP equation),
setting the S_CTRIM value as 5.0 pF can make the effective intrinsic capacitance become 15 pF.
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As the intrinsic sensitivity of the touch key is given by ΔCs/Cs, the less intrinsic capacitance would result in more sensitive
touch response. With this sensitivity boost enabled, sensitivity can be improved to ΔCs/ (Cs-S_CTRIM*(S_XDN/S_XCH)).
Sensitivity boost feature in self-cap mode can be activated by setting TSI_MODE[S_SEN]. Equation 6 is a new equation to
calculate NSTEP when sensitivity boost function is enabled.
NESTP =  Ci × Vp − Vm
vdd3v×Cs − S_CTRIM ×S_XDN/S_XCH ×S_XIN ×S_XCH
Equation 6.
• S_CTRIM: configurable, the capacitance to be removed.
• S_XDN/S_XCH: configurable, the capacitance multiplier.
• The actual capacitance to be removed is S_CTRIM × (S_XDN/S_XCH).
2.4.2 TSI scan multiple rounds in self-cap mode
To minimize the noise deviation on the single scan, TSI supports multiple scans per channel. That is, TSI performs single scan
operation for many times from getting the trigger to end of scan.
Figure 12. Multiple scans per channel
Each time the TSI is triggered, multiple scans can be performed inside the TSI. The scan round is set by the registers
(TSI_SINC[DECIMATION], [ORDER] and [CUTOFF]), ranged from 1 to 322. When the TSI_SINC[DECIMATION] is set to 0 (only
once), the single scan is engaged.
The 16-bit counter accumulates all scan results until the scan number reaches predefined number. To get the final scan result,
read TSI_DATA[TSICNT].
There are two kinds of scan number:
• For digital calculation to accumulate the final TSI scan result, as shown in Equation 5.
• For TSI IP to execute the scan action practically, as shown in Equation 6.
ScanResult: TSICNT =NSTEP ×DecimationOrder
Cutoff
Equation 7.
ScanTime: Time = Tnstep ×Decimation × Order
Equation 8.
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According to Equation 3, Equation 4, Equation 7, and Equation 8, the parameters of Decimation, Order and Cutoff, S_XIN, S_XCH,
and (Vp -Vm) affect the final accumulated scan result and the total scan time.
Users must adjust the touch electrode according to different applications. The parameters of TSI can be adjusted comprehensively
to achieve the best performance of TSI.
For example,
• Increase the voltage of (Vp-Vm) can reduce the effect of low frequency noise, but the scan time of TSI increases.
The increase of S_XCH and S_XIN can increase the charging current of Ci and shorten the scan time of TSI, but the
noise increases. Therefore, when (Vp-Vm) increases, S_XCH and S_XIN can be reduced, which cannot only reduce the
scanning time but also reduce the noise and enhance the sensitivity.
• Decimation, Order, and Cutoff increase the number of scans for the touch electrodes and enhance the anti-interference
of the electrodes. At the same time, the scan time of the touch electrodes is also longer. Setting the Order as 2 is
recommended as it can save scan time to achieve the same digital scan result.
2.5 Scan time and sensitivity boost tests in self-cap mode
2.5.1 Scan time test in self-cap mode
This chapter shows the one self-cap touch electrode scan time test results on X-KE17Z-TSI-EVB.
As shown in Table 8, given the NSTEP is 110 and Tnstep is 239 us by the measurement result of single scan, shown as Example
1. The theoretical value can be calculated by Equation 7 and Equation 8.
Table 8. Scan time test by changing the configuration of Decimation, Order, Cutoff
Switching
Clock (MHz) NSTEP Tnstep (μs)
Configurations Result
Decimation Order Cutoff NSTEP
Multiple
Counter
(TSICNT)1
Real
Scan
Round
Scan
Time2
(μs)
1 0.52 11 1 1 110 1 239
2 0.52 110 239 21 1 2 220 2 448
3 0.52 110 239 41 1 4 440 4 869
4 0.52 110 239 81 1 8 880 8 1709
5 0.52 110 239 16 1 1 16 1760 16 3390
6 0.52 110 239 32 1 1 32 3520 32 6750
7 0.52 110 239 1 21 1 110 2449
8 0.52 110 239 2 21 4 440 4869
9 0.52 110 239 4 21 16 1760 81709
10 0.52 110 239 8 21 64 7040 16 3390
11 0.52 110 239 8 2 232 3520 16 3390
1. The Counter (TSICNT) is read from the register when debugging the code.
2. The actual Scan time is calculated by LPTMR module.
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• Other conditions: Ci, 90 pF; vdd3v, 3.3 V; S_XIN, 1/4; S_XCH, 1/2.
•Example 1: Configure the Decimation, Order, and Cutoff as 1, and the final scan result is 110. TSI performs scan
operation for one time, and the scan time is 239 μs.
•Example 2: Change the Decimation to 2, and the final scan result becomes 220. TSI performs scan twice, and the scan
time is 448, about twice of the previous 239 μs.
•Example 10: Change the order to 2, and the final scan result becomes 110 * 64 = 7040. TSI only performs scan for 8 * 2 =
16 times, and the scan time is 3390 μs, saving time by setting order = 2.
By comparing the test results when setting order to 1 and order to 2, the conclusion is:
Increasing TSI conversion result (TSICNT) means to cost longer scan time. When TSI performs multiple scans, it is recommended
to set order to 2 to reduce interference and save touch electrode scan time. Then change the Decimation and Cutoff to adjust the
TSI conversion result. Increase TSI conversion result means longer scan time.
The scan time in this table is measured by the LPTMR module. That is, start LPTMR on the TSI scan start, stop LPTMR on the
TSI scan end, and then read the LPTMR counter to estimate the time cost. There are some inevitable small errors and differences
between LPTMR measurement and real TSI scan time.
2.5.2 Sensitivity test result when sensitivity boost feature enable
When the sensitivity boost function is enabled, NSTEP is calculated by Equation 6, and the calculation of TSICNT and scan time
still uses Equation 7 and Equation 8.
The sensitivity boost configurations include: S_SEN Enable, S_CTRIM, and Multiplier (S_XDN/S_XCH).
Table 9. Sensitivity boost configurations registers
Variable Register Descriptions
S_SEN Enable TSI_MODE[S_SEN] Enable sensitivity boost by setting S_SEN to 1.
S_CTRIM TSI_MODE[S_CTRIM] Remove the parasitic capacitance virtually, from 2.5 pF to 20 pF.
Multiplier:
S_XDN/S_XCH
TSI_MODE[S_XDN] Multiplier factor when sensitivity boost is enabled.
TSI_MODE[S_XCH] Charge/discharge multiple
The remove capacitance is:
Cremoved=SCTRIM ×SXDN
SXCH

Equation 9.
Table 10. Sensitivity test for sensitivity boost configurations
Current Amplifier Sensitivity Boost Intrinsic
capacitance
calculated Cx
Sensitivity
calculated
(%)
S_XIN S_XCH Current Amplifier
(S_XIN*S_XCH)
S_SEN
Enable S_XDN S_Ctrim (pF) Cremoved (pF)
1/4 1/2 1/8 OFF 1/2 2.5 0.0 16 11.6
1/4 1/2 1/8 ON 1/2 2.5 2.5 16 12.5
Table continues on the next page...
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Table 10. Sensitivity test for sensitivity boost configurations (continued)
Current Amplifier Sensitivity Boost Intrinsic
capacitance
calculated Cx
Sensitivity
calculated
(%)
S_XIN S_XCH Current Amplifier
(S_XIN*S_XCH)
S_SEN
Enable S_XDN S_Ctrim (pF) Cremoved (pF)
1/4 1/2 1/8 ON 1/2 5.0 5.0 16 15.0
1/4 1/2 1/8 ON 1/2 7.5 7.5 16 22.2
1/4 1/2 1/8 ON 1/2 10.0 10.0 16 28.2
1/4 1/2 1/8 ON 1/2 12.5 12.5 15 43.8
Figure 13. Sensitivity curve
From sensitivity calculated results, we can find out that the Cremoved is the key configuration to the sensitivity boost feature. As
Cremoved increases, the sensitivity becomes better. That is, it is to recognize touch event. Therefore, users can adjust the S_CTRIM
and S_XDN to quickly adjust the sensitivity of touch electrode recognition.
Figure 14 shows the definition of the sensitivity.
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Figure 14. TSI sensitivity definition
Sensitivity =TSI_Counter_Delter
TSI_Baseline × 100%
Equation 10.
The large sensitivity value means the stronger signal caused by finger touch.
Sensitivity around 10 % is recommended in self-cap mode.
3 TSI Mutual-cap mode
3.1 Mutual-cap sensor
Mutual-cap mode measures the capacitance between two electrodes connected to two TSI channels. One of the TSI channels is
used as transmit (TX) channel and the other one is used as receive (RX) channel.
For the two TSI instances of KE17Z, TSIx[5:0] can be used as TX channel by configuring TSIx_MUL0[M_SEL_TX]. TSIx[11:6]
can be used as RX channel by configuring TSIx_MUL0[M_SEL_RX]. The mutual-cap touch electrode design of TSI0 and TSI1 is
independent. Each TSI instance supports the design of 6 × 6 touch electrodes.
Touch changes field through human body and reduces the mutual capacitance. TSI IP is to convert the capacitance changing from
the sensor to digital code for application.
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Ground Hatch
Tx Electrode Ground HatchGround Hatch
PCB
Dielectric
Overlay
Cs Cs
via
Routing I/O pin
Rx Electrode
Cm
via
via
Routing
I/O pin
ΔCm
Ground
Hatch
Tx
Rx
Mutual-cap
electrode
Figure 15. Mutual-cap touch sensor structure and electric field
Sensor structure:
• Cm: Intrinsic mutual cap. 2 - 10 pF as usual.
• ΔCm: Touch reduced mutual cap. 0.3 - 2 pF as usual.
• Cs: Parasitic self-cap. 10 - 50 pF as usual.
• Sensitivity of sensor: ΔCm/Cm. 1 - 20 % as usual.
3.2 Clock generation in mutual-cap mode
One difference to the self-mode clock, the SSC must be enabled for mutual mode to generate switching clock, because the TSI
RX signal in the mutual mode depends on the TSI_SSC0[CHARGE_NUM]. In the mutual mode, changing the SSC charge time
changes the RX signal coupled from TX channel and affects the final scan result.
Figure 16. Clock generation in mutual-cap mode, spread spectrum clocking
SSC is enabled, the mutual mode shares the clock generation of the self-cap mode. For detailed configurations, see Advanced
clock generation, spread spectrum clocking.
Equation 2 is used to calculate the Switching Clock when SSC is enabled.
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3.3 Mutual-cap sensing mode
Mutual-cap sensing includes transmitter and receiver. Under clocking, transmitter outputs pulses which decouple through mutual
cap then reach receiver site. Receiver amplifies the signal with noise cancellation method. The method is similar as charge transfer
circuit in self-cap sensing. That is, convert to averaging charge current on integration cap Ci which creates step voltage Vci.
The step number of each scanning is accumulated to give final count TSICNT for each trigger.
Figure 17. Block diagram of TSI mutual-cap mode
ON
charge
Vp
Switching Clock: ph1
Vm
Single TSI Scan
0 STEP 1 STEP
N STEP
Comparator: Vci
Switching Clock: ph2
OFF
OFF ON
discharge
Tx
Rx
charge discharge
Vpre+∆V
Vpre-∆V
VDD5V
GND
Figure 18. Mutual capacitive mode timing
• Vpre is selected by TSIx_MUL1[M_VPRE_CHOOSE].
• ΔV: signal voltage RX received, decided by VDD5V × Cm/(Cm + Cs).
• TX drive mode is controlled by TSIx_MUL1[M_MOD], -5 - +5 V is selected in Figure 18.
As shown in Figure 17 and Figure 18, there are two phases controlled by the switching clock for the TSI mutual capacitive mode:
• Charge phase: The switch ph1 controls the charge phase, when ph1 turns on, the transmit channel outputs pulses which
are coupled through the mutual capacitance Cm. Receiver converts the received voltage pulse (Vpre + ∆V) to the current
Icharge through the resistor Rs.
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