NXP Semiconductors MPC5606BK User manual

MPC5606BK Microcontroller
Reference Manual
Devices Supported:
MPC5606BKRM
Rev. 2
05/2014
MPC5606BK
MPC5605BK

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Chapter 1
Preface
1.1 Overview .........................................................................................................................................21
1.2 Audience ..........................................................................................................................................21
1.3 Guide to this reference manual ........................................................................................................21
1.4 Register description conventions ....................................................................................................25
1.5 References .......................................................................................................................................26
1.6 How to use the MPC5606BK documents .......................................................................................26
1.6.1 The MPC5606BK document set .....................................................................................26
1.6.2 Reference manual content ..............................................................................................27
1.7 Using the MPC5606BK ..................................................................................................................28
1.7.1 Hardware design .............................................................................................................28
1.7.2 Input/output pins .............................................................................................................29
1.7.3 Software design ..............................................................................................................29
1.7.4 Other features .................................................................................................................30
Chapter 2
Introduction
2.1 The MPC5606BK microcontroller family ......................................................................................31
2.2 MPC5606BK device comparison ....................................................................................................31
2.3 Device block diagram ......................................................................................................................32
2.4 Feature details .................................................................................................................................35
2.4.1 e200z0h core processor ..................................................................................................35
2.4.2 Crossbar switch (XBAR) ................................................................................................35
2.4.3 Interrupt Controller (INTC) ............................................................................................35
2.4.4 System Integration Unit Lite (SIUL) ..............................................................................36
2.4.5 Flash memory .................................................................................................................36
2.4.6 SRAM .............................................................................................................................38
2.4.7 Memory Protection Unit (MPU) ....................................................................................38
2.4.8 Boot Assist Module (BAM) ...........................................................................................38
2.4.9 Enhanced Modular Input Output System (eMIOS) ........................................................39
2.4.10 Deserial Serial Peripheral Interface Module (DSPI) ......................................................40
2.4.11 Controller Area Network module (FlexCAN) ................................................................40
2.4.12 System clocks and clock generation ...............................................................................41
2.4.13 System timers .................................................................................................................42
2.4.14 System watchdog timer ..................................................................................................43
2.4.15 Inter-Integrated Circuit (I2C) module ............................................................................43
2.4.16 On-chip voltage regulator (VREG) ................................................................................43
2.4.17 Analog-to-Digital Converter (ADC) ..............................................................................44
2.4.18 Enhanced Direct Memory Access controller (eDMA) ...................................................45
2.4.19 Cross Trigger Unit (CTU) ..............................................................................................45
2.4.20 Serial communication interface module (LINFlex) .......................................................46
2.4.21 JTAG Controller (JTAGC) .............................................................................................47
2.5 Developer support ..........................................................................................................................47

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Chapter 3
Memory Map
Chapter 4
Signal description
4.1 Package pinouts ...............................................................................................................................53
4.2 Pin muxing ......................................................................................................................................55
Chapter 5
Microcontroller Boot
5.1 Boot mechanism ..............................................................................................................................75
5.1.1 Flash memory boot .........................................................................................................76
5.1.2 Serial boot mode .............................................................................................................78
5.1.3 Censorship ......................................................................................................................78
5.2 Boot Assist Module (BAM) ............................................................................................................83
5.2.1 BAM software flow ........................................................................................................83
5.2.2 LINFlex (RS232) boot ....................................................................................................91
5.2.3 FlexCAN boot ................................................................................................................92
5.3 System Status and Configuration Module (SSCM) ........................................................................94
5.3.1 Introduction ....................................................................................................................94
5.3.2 Features ...........................................................................................................................94
5.3.3 Modes of operation .........................................................................................................95
5.3.4 Memory map and register description ............................................................................95
Chapter 6
Clock Description
6.1 Clock architecture .........................................................................................................................105
6.2 Clock gating ..................................................................................................................................106
6.3 Fast external crystal oscillator (FXOSC) digital interface ............................................................107
6.3.1 Main features ................................................................................................................107
6.3.2 Functional description ..................................................................................................107
6.3.3 Register description ......................................................................................................108
6.4 Slow external crystal oscillator (SXOSC) digital interface ..........................................................109
6.4.1 Introduction ..................................................................................................................109
6.4.2 Main features ................................................................................................................109
6.4.3 Functional description ..................................................................................................109
6.4.4 Register description ......................................................................................................110
6.5 Slow internal RC oscillator (SIRC) digital interface ....................................................................111
6.5.1 Introduction ..................................................................................................................111
6.5.2 Functional description ..................................................................................................112
6.5.3 Register description ......................................................................................................112
6.6 Fast internal RC oscillator (FIRC) digital interface ......................................................................113
6.6.1 Introduction ..................................................................................................................113
6.6.2 Functional description ..................................................................................................113
6.6.3 Register description ......................................................................................................114

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6.7 Frequency-modulated phase-locked loop (FMPLL) .....................................................................115
6.7.1 Introduction ..................................................................................................................115
6.7.2 Overview ......................................................................................................................115
6.7.3 Features .........................................................................................................................115
6.7.4 Memory map ................................................................................................................116
6.7.5 Register description ......................................................................................................116
6.7.6 Functional description ..................................................................................................120
6.7.7 Recommendations ........................................................................................................122
6.8 Clock monitor unit (CMU) ............................................................................................................123
6.8.1 Introduction ..................................................................................................................123
6.8.2 Main features ................................................................................................................123
6.8.3 Block diagram ..............................................................................................................124
6.8.4 Functional description ..................................................................................................124
6.8.5 Memory map and register description ..........................................................................126
Chapter 7
Clock Generation Module (MC_CGM)
7.1 Overview .......................................................................................................................................131
7.2 Features .........................................................................................................................................132
7.3 Modes of operation ........................................................................................................................133
7.3.1 Normal and reset modes of operation ...........................................................................133
7.4 External signal description ............................................................................................................133
7.5 Memory map and register definition .............................................................................................133
7.5.1 Register descriptions ....................................................................................................137
7.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................138
7.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................139
7.6 Functional Description ..................................................................................................................142
7.6.1 System Clock Generation .............................................................................................142
7.6.2 Output Clock Multiplexing ...........................................................................................143
7.6.3 Output Clock Division Selection ..................................................................................144
Chapter 8
Mode Entry Module (MC_ME)
8.1 Overview .......................................................................................................................................145
8.1.1 Features .........................................................................................................................145
8.1.2 Modes of operation .......................................................................................................146
8.2 External signal description ............................................................................................................147
8.3 Memory map and register definition .............................................................................................147
8.3.1 Register descriptions ....................................................................................................150
8.4 Functional description ...................................................................................................................163
8.4.1 Mode transition request ................................................................................................163
8.4.2 Modes details ................................................................................................................164
8.4.3 Mode transition process ................................................................................................167
8.4.4 Protection of mode configuration registers ..................................................................175
8.4.5 Mode transition interrupts ............................................................................................175

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8.4.6 Application example .....................................................................................................177
Chapter 9
Reset Generation Module (MC_RGM)
9.1 Introduction ...................................................................................................................................179
9.1.1 Overview ......................................................................................................................179
9.1.2 Features .........................................................................................................................180
9.1.3 Modes of operation .......................................................................................................181
9.2 External signal description ............................................................................................................181
9.3 Memory map and register definition .............................................................................................182
9.3.1 Register descriptions ....................................................................................................183
9.4 Functional description ...................................................................................................................188
9.4.1 Reset state machine ......................................................................................................188
9.4.2 Destructive resets ..........................................................................................................191
9.4.3 External reset ................................................................................................................192
9.4.4 Functional resets ...........................................................................................................192
9.4.5 Alternate event generation ............................................................................................192
9.4.6 Boot mode capturing ....................................................................................................193
Chapter 10
Power Control Unit (MC_PCU)
10.1 Introduction ...................................................................................................................................195
10.1.1 Overview ......................................................................................................................195
10.1.2 Features .........................................................................................................................196
10.1.3 Modes of operation .......................................................................................................196
10.2 External signal description ............................................................................................................197
10.3 Memory map and register definition .............................................................................................197
10.3.1 Register descriptions ....................................................................................................199
10.4 Functional description ...................................................................................................................202
10.4.1 General .........................................................................................................................202
10.4.2 Reset / Power-On Reset ................................................................................................203
10.4.3 MC_PCU configuration ................................................................................................203
10.4.4 Mode transitions ...........................................................................................................203
10.5 Initialization information ...............................................................................................................205
10.6 Application information ................................................................................................................206
10.6.1 STANDBY Mode Considerations ................................................................................206
Chapter 11
Voltage Regulators and Power Supplies
11.1 Voltage regulators ..........................................................................................................................207
11.1.1 High power regulator (HPREG) ...................................................................................207
11.1.2 Low power regulator (LPREG) ....................................................................................207
11.1.3 Ultra low power regulator (ULPREG) .........................................................................208
11.1.4 LVDs and POR .............................................................................................................208
11.1.5 VREG digital interface .................................................................................................208

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11.1.6 Register description ......................................................................................................209
11.2 Power supply strategy ...................................................................................................................209
11.3 Power domain organization ...........................................................................................................210
Chapter 12
Wakeup Unit (WKPU)
12.1 Overview .......................................................................................................................................213
12.2 Features .........................................................................................................................................215
12.3 External signal description ............................................................................................................216
12.4 Memory map and register description ...........................................................................................216
12.4.1 Memory map ................................................................................................................216
12.4.2 NMI Status Flag Register (NSR) ..................................................................................217
12.4.3 NMI Configuration Register (NCR) .............................................................................218
12.4.4 Wakeup/Interrupt Status Flag Register (WISR) ...........................................................219
12.4.5 Interrupt Request Enable Register (IRER) ...................................................................219
12.4.6 Wakeup Request Enable Register (WRER) ..................................................................220
12.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) .............................220
12.4.8 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) .............................221
12.4.9 Wakeup/Interrupt Filter Enable Register (WIFER) ......................................................221
12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) .................................................222
12.5 Functional description ...................................................................................................................222
12.5.1 General .........................................................................................................................222
12.5.2 Non-maskable interrupts ..............................................................................................223
12.5.3 External wakeups/interrupts .........................................................................................224
12.5.4 On-chip wakeups ..........................................................................................................226
Chapter 13
Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.1 Overview .......................................................................................................................................227
13.2 Features .........................................................................................................................................227
13.3 Device-specific information ..........................................................................................................229
13.4 Modes of operation ........................................................................................................................229
13.4.1 Functional mode ...........................................................................................................229
13.4.2 Debug mode ..................................................................................................................230
13.5 Register descriptions .....................................................................................................................230
13.5.1 RTC Supervisor Control Register (RTCSUPV) ...........................................................230
13.5.2 RTC Control Register (RTCC) .....................................................................................231
13.5.3 RTC Status Register (RTCS) ........................................................................................233
13.5.4 RTC Counter Register (RTCCNT) ...............................................................................234
13.6 RTC functional description ...........................................................................................................234
13.7 API functional description ............................................................................................................235
Chapter 14
CAN Sampler
14.1 Introduction ...................................................................................................................................237

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14.2 Main features .................................................................................................................................237
14.3 Memory map and register description ...........................................................................................238
14.3.1 Control Register (CR) ...................................................................................................238
14.3.2 CAN Sampler Sample Registers 0–11 ..........................................................................239
14.4 Functional description ...................................................................................................................239
14.4.1 Enabling/disabling the CAN sampler ...........................................................................240
14.4.2 Selecting the Rx port ....................................................................................................240
14.4.3 Baud rate generation .....................................................................................................241
Chapter 15
e200z0h Core
15.1 Overview .......................................................................................................................................245
15.2 Microarchitecture summary ..........................................................................................................245
15.3 Block diagram ...............................................................................................................................247
15.4 Features .........................................................................................................................................247
15.4.1 Instruction unit features ................................................................................................248
15.4.2 Integer unit features ......................................................................................................248
15.4.3 Load/Store unit features ...............................................................................................249
15.4.4 e200z0h system bus features ........................................................................................249
15.5 Core registers and programmer’s model .......................................................................................249
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Device-specific features ................................................................................................................253
16.2 Introduction ...................................................................................................................................253
16.2.1 Features .........................................................................................................................254
16.3 Memory map and register definition .............................................................................................255
16.3.1 Memory map ................................................................................................................255
16.3.2 Register descriptions ....................................................................................................257
16.4 Functional description ...................................................................................................................278
16.4.1 eDMA basic data flow ..................................................................................................280
16.5 Initialization / application information ..........................................................................................283
16.5.1 eDMA initialization ......................................................................................................283
16.5.2 DMA programming errors ............................................................................................285
16.5.3 DMA request assignments ............................................................................................286
16.5.4 DMA arbitration mode considerations .........................................................................286
16.5.5 DMA transfer ................................................................................................................287
16.5.6 TCD status ....................................................................................................................290
16.5.7 Channel linking ............................................................................................................291
16.5.8 Dynamic programming .................................................................................................292
Chapter 17
eDMA Channel Multiplexer (DMA_MUX)
17.1 Introduction ...................................................................................................................................295
17.2 Features .........................................................................................................................................295

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17.3 Modes of operation ........................................................................................................................296
17.4 External signal description ............................................................................................................296
17.5 Memory map and register definition .............................................................................................296
17.5.1 Channel configuration registers (CHCONFIGn) ..........................................................297
17.6 DMA_MUX inputs .......................................................................................................................298
17.6.1 DMA_MUX peripheral sources ...................................................................................298
17.6.2 DMA_MUX periodic trigger inputs .............................................................................300
17.7 Functional description ...................................................................................................................300
17.7.1 eDMA channels with periodic triggering capability ....................................................300
17.7.2 eDMA channels with no triggering capability .............................................................302
17.8 Initialization/Application information ...........................................................................................303
17.8.1 Reset .............................................................................................................................303
17.8.2 Enabling and configuring sources ................................................................................303
Chapter 18
Interrupt Controller (INTC)
18.1 Introduction ...................................................................................................................................307
18.2 Features .........................................................................................................................................307
18.3 Block diagram ...............................................................................................................................309
18.4 Modes of operation ........................................................................................................................309
18.4.1 Normal mode ................................................................................................................309
18.5 Memory map and register description ...........................................................................................311
18.5.1 Module memory map ...................................................................................................311
18.5.2 Register description ......................................................................................................311
18.6 Functional description ...................................................................................................................319
18.6.1 Interrupt request sources ...............................................................................................327
18.6.2 Priority management ....................................................................................................328
18.6.3 Handshaking with processor .........................................................................................330
18.7 Initialization/application information ............................................................................................332
18.7.1 Initialization flow .........................................................................................................332
18.7.2 Interrupt exception handler ...........................................................................................332
18.7.3 ISR, RTOS, and task hierarchy .....................................................................................334
18.7.4 Order of execution ........................................................................................................335
18.7.5 Priority ceiling protocol ................................................................................................336
18.7.6 Selecting priorities according to request rates and deadlines .......................................336
18.7.7 Software configurable interrupt requests ......................................................................337
18.7.8 Lowering priority within an ISR ..................................................................................338
18.7.9 Negating an interrupt request outside of its ISR ..........................................................338
18.7.10 Examining LIFO contents ............................................................................................339
Chapter 19
Crossbar Switch (XBAR)
19.1 Introduction ...................................................................................................................................341
19.2 Block diagram ...............................................................................................................................341
19.3 Overview .......................................................................................................................................342

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19.4 Features .........................................................................................................................................342
19.5 Modes of operation ........................................................................................................................342
19.5.1 Normal mode ................................................................................................................342
19.5.2 Debug mode ..................................................................................................................342
19.6 Functional description ...................................................................................................................342
19.6.1 Overview ......................................................................................................................342
19.6.2 General operation .........................................................................................................343
19.6.3 Master ports ..................................................................................................................343
19.6.4 Slave ports ....................................................................................................................344
19.6.5 Priority assignment .......................................................................................................344
19.6.6 Arbitration ....................................................................................................................344
Chapter 20
System Integration Unit Lite (SIUL)
20.1 Introduction ...................................................................................................................................347
20.2 Overview .......................................................................................................................................347
20.3 Features .........................................................................................................................................349
20.4 External signal description ............................................................................................................349
20.4.1 Detailed signal descriptions ..........................................................................................350
20.5 Memory map and register description ...........................................................................................351
20.5.1 SIUL memory map .......................................................................................................351
20.5.2 Register protection ........................................................................................................352
20.5.3 Register descriptions ....................................................................................................353
20.6 Functional description ...................................................................................................................372
20.6.1 Pad control ....................................................................................................................372
20.6.2 General purpose input and output pads (GPIO) ...........................................................372
20.6.3 External interrupts ........................................................................................................373
20.7 Pin muxing ....................................................................................................................................374
Chapter 21
Memory Protection Unit (MPU)
21.1 Introduction ...................................................................................................................................375
21.2 Features .........................................................................................................................................376
21.3 Modes of operation ........................................................................................................................377
21.4 External signal description ............................................................................................................377
21.5 Memory map and register description ...........................................................................................377
21.5.1 Memory map ................................................................................................................378
21.5.2 Register description ......................................................................................................379
21.6 Functional description ...................................................................................................................390
21.6.1 Access evaluation macro ..............................................................................................390
21.6.2 Putting it all together and AHB error terminations ......................................................391
21.7 Initialization information ...............................................................................................................392
21.8 Application information ................................................................................................................392