Panasonic eUniStone Guide

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eUniStone
PAN1322 Application Note DesignGuide

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PAN1322
Application Note 2 Revision 1.2, 2013-12-18
Design Guide
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PAN1322
Application Note 3 Revision 1.2, 2013-12-18
Design Guide
Revision History
Revision Number
Description
Revision Date
1.2
Updated reference schematic
Added chapter describing how to change from HCI to SPP, chapter 9.4.
16-Oct-2013
1.1
Added chapters Application development and FAQ
27-Jun-2013
1.0
New document for eUniStone PBA31309 v1.00
12-Mar-2013

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PAN1322
Application Note 4 Revision 1.2, 2013-12-18
Design Guide
Contents
1Introduction..................................................................................................................10
2Interfaces ......................................................................................................................13
2.1 UART Interface ............................................................................................................13
2.1.1 Low Power Mode Control .........................................................................................13
2.1.2 Hardware Flow Control.............................................................................................15
2.2 EEPROM / I2C Interface...........................................................................................15
2.3 GPIO Interface.............................................................................................................16
2.4 JTAG Interface.............................................................................................................16
3Power Supply ...............................................................................................................17
3.1 Power up Sequence ...................................................................................................17
3.2 Power down through ONOFF Pin...........................................................................18
4Operation Modes.........................................................................................................19
4.1 Command Mode ..........................................................................................................19
4.2 Stream Mode................................................................................................................19
4.3 Switch from Command Mode to Stream Mode ...............................................20
4.4 Switch from Stream Mode to Command Mode ...............................................20
5Accessory Development Compatible with Smart Phones............................21
5.1 Accessory.......................................................................................................................22
5.1.1 Host Processor.............................................................................................................22
5.1.2 Host Application ..........................................................................................................24
5.1.3 Smart Phone compatibility requirements..........................................................26
5.1.3.1 Serial Port Profile - device A and B .....................................................................26
5.1.3.2 Security settings –Input & Output Capabilities .............................................27
5.1.3.3 Registering service - UUID and CoD. .................................................................28
5.1.3.4 Registering multiple services and connection handling...............................30
5.1.3.5 Smart Phone connecting to Accessory...............................................................31

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Application Note 5 Revision 1.2, 2013-12-18
Design Guide
5.2 Smart Phone specifics...............................................................................................32
5.2.1 Android Smart Phones..............................................................................................33
5.2.1.1 Registering service for Android compatibility..................................................33
5.2.1.2 Security settings and connecting/bonding to Smart Phone versus App
in the phone .................................................................................................................34
5.2.1.3 Android market and Developing Apps for Android Smart Phones...........35
5.2.2 Windows phone ...........................................................................................................35
5.2.2.1 Registering service for Windows Phone.............................................................35
5.2.2.2 Bonding ..........................................................................................................................36
5.2.2.3 Windows Phone Store, development and design...........................................36
5.2.2.4 Programming language for Windows Phone ....................................................37
5.2.3 iPhone .............................................................................................................................37
5.2.3.1 Registering service for iPhone...............................................................................38
5.2.3.2 Bonding ..........................................................................................................................39
5.2.3.3 iOS and MFi license....................................................................................................40
6Reference Design Schematic .................................................................................41
7Layout .............................................................................................................................44
7.1 Two layer PCB reference design ...........................................................................44
7.2 General four layer PCB design ..............................................................................46
7.2.1 Phase1: Layer Assignment....................................................................................46
7.2.1.1 Via Holes ........................................................................................................................47
7.2.2 Phase 2: Components Placement .......................................................................48
7.2.3 Phase 3: Routing.......................................................................................................48
7.2.3.1 Basic Hints.....................................................................................................................48
7.2.3.2 Layout Specific Hints.................................................................................................48
8Antenna..........................................................................................................................50
9Test and Development Tools..................................................................................51
9.1 Tools available for development and testing...................................................51
9.1.1 SPP Toolbox..................................................................................................................51

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Application Note 6 Revision 1.2, 2013-12-18
Design Guide
9.1.2 SPP Test Tool ...............................................................................................................51
9.1.3 HCI Lite ..........................................................................................................................51
9.1.4 eeprog –Aardvark .....................................................................................................51
9.2 Setup of Device Under Test (DUT) ......................................................................52
9.3 Preparation for RF Tests in non-signaling mode ............................................53
9.4 Restoring from HCI to SPP (without using Aardvark)..................................55
9.4.1 Restoring SPP-AT - Overwriting EEPROM..........................................................55
9.4.2 Restoring SPP-AT - Loading latest SPP-AT Application. ..............................58
9.4.3 Restoring SPP - Writing BD address and oscillator trim value .................59
9.5 Crystal Trimming ........................................................................................................60
9.5.1 Osc_Trim Parameter .................................................................................................60
9.5.2 Crystal Trimming Procedure...................................................................................61
9.5.2.1 Crystal Trimming with HCI application for special RF tests.......................61
9.5.2.2 Crystal Trimming with SPP-AT Application.......................................................65
10 FAQ ..................................................................................................................................67
10.1 First use of PBA31309 USB dongles....................................................................67
10.1.1 Connect the dongle to a USB port on the computer....................................67
10.1.2 Modify FTDI COM port settings for full throughput.......................................68
10.2 Change UART baud rate of PBA31309 ...............................................................69
10.2.1 Change of baud rate in product manufacturing .............................................69
10.2.2 Change of baud rate by host at runtime...........................................................70
10.3 SW update.....................................................................................................................70
10.4 Aardvark and eeprog.exe........................................................................................71
10.4.1 Installing Aardvark.....................................................................................................71
10.4.2 Connecting Aardvark to PBA31309 .....................................................................73
10.4.3 Downloading software to PBA31309...................................................................73
10.4.4 Aardvark problems. ...................................................................................................73
10.5 UUID & CoD..................................................................................................................74

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Application Note 7 Revision 1.2, 2013-12-18
Design Guide
10.6 Low Power Mode, LPM, control..............................................................................74
10.7 Bluetooth Qualification and Regulatory Certification....................................74
11 References.....................................................................................................................75
Figures
Figure 1. Simplified Block Diagram of eUniStone Module..................................................12
Figure 2. UART Interface ................................................................................................................13
Figure 3. Host Initiates Low Power Mode Entry and Exit ...................................................14
Figure 4. Host Initiates Low Power Mode Entry, eUniStone Initiates Exit...................15
Figure 5. Example of EEPROM Access at Start-up ................................................................18
Figure 6. Accessory with Mobile App..........................................................................................21
Figure 7. Host processor with peripheral device and UART connection to eUniStone
...........................................................................................................................................................23
Figure 8. General state machine for a Host application as accessory...........................25
Figure 9. Smart Phone Apps using Serial Port Profile UUID connecting to Serial
port accessory. ............................................................................................................................29
Figure 10. eUniStone with three registered services and possible connections to
Smart Phones. .............................................................................................................................30
Figure 11. Handling incoming connection depending on service....................................31
Figure 12. Accessory and Android Smart Phone App using the same UUID will be
able to connect............................................................................................................................34
Figure 13. Reference Design .........................................................................................................43
Figure 14. Restricted area under antenna and recommended placement on PCB. .44
Figure 15. Top layer and drill holes of the eUniStone USB Dongle. ..............................45
Figure 16. Bottom layer (from above) and drill holes of the eUniStone USB Dongle.
...........................................................................................................................................................45
Figure 17. The two layers of the eUniStone USB Dongle. .................................................46

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PAN1322
Application Note 8 Revision 1.2, 2013-12-18
Design Guide
Figure 18. Example of a four layer stack-up...........................................................................47
Figure 19. Via Types.........................................................................................................................47
Figure 20. Radiation patterns of the built in antenna. ........................................................50
Figure 21. Setup of Device Under Test with AT commands. ............................................52
Figure 22. Download of HCI Application via UART................................................................54
Figure 23 Restoring from HCI to SPP-AT using HCI Lite....................................................56
Figure 24 Downloading latest SPP-AT application. ...............................................................58
Figure 25. Typical 32MHz frequency offset in PPM versus OSC_Trim value. .............61
Figure 26. Crystal Trimming using HCI Lite Tool ..................................................................62
Figure 27. Intel Write BD-Data Window ...................................................................................64
Figure 28. Crystal Trimming using eBMU SPP Toolbox.......................................................66
Figure 29. Finding the COM port in the Device Manager ...................................................68
Figure 30. Modify the Latency Timer of the FTDI driver ....................................................68
Figure 31. Aardvark drivers installed and visible in the Device Manager. ..................72
Figure 32. Aardvark connect to the PBA31309 USB dongle. (Black = GND, Red =
I2C clock, White = I2C data).................................................................................................73
Figure 33. PBA31309 powered by an USB hub ......................................................................74
Tables
Table 1. Sending and receiving data in command mode ...................................................19
Table 2. Sending and receiving data in stream mode.........................................................19
Table 3. Configurable combination of Input and Output Capabilities for eUniStone.
...........................................................................................................................................................28
Table 4. Class of Device bits for a handheld terminal with bar-code scanner. .........28
Table 5. CoD examples for some accessories. .......................................................................29
Table 6. Accessory (eUniStone) set to connectable, device B .........................................31
Table 7. Android Smart Phone - bonding with eUniStone .................................................34

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PAN1322
Application Note 9 Revision 1.2, 2013-12-18
Design Guide
Table 8. Windows Phone - bonding with eUniStone. ...........................................................36
Table 9. iPhone - bonding with eUniStone. .............................................................................40
Table 10. Default Pin Configuration............................................................................................42
Table 11. Register for Switching Capacitances ......................................................................60
Table 12. Changing the baud rate at runtime ........................................................................70
Table 13. SW update sequence....................................................................................................70

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PAN1322
Application Note 10 Revision 1.2, 2013-12-18
Design Guide
1Introduction
eUniStone (embedded UniStone), with part number PBA31309, is a module based on PMB8754
(eBMU), an integrated BT radio transceiver, baseband and protocol stack, with EEPROM, band-pass
filter and built in antenna
eUniStone supports the following features
Bluetooth v2.1 + EDR compliant SPP implementation
Secure Simple Pairing, Security Mode 4
oAssociation Models „Numeric Comparison“, „Just Works“ and „Passkey
Entry“ are supported
Encryption Pause Resume
Enhanced Power Control (BT3.0 feature of the BT Controller)
Device A (initiating) and device B (accepting) role
One point-to-point link for data transmission
octet by octet in stream mode
by packets in command mode (MTU size 500 bytes)
Device is visible and connectable until the link has been set up
Sniff and Sniff Sub Rating are supported on the link to save current
Up to five trusted devices can be stored in EEPROM
when 6th device is paired, the first device is deleted
AT commands for development and manufacturing
Device Under Test mode for connection to a BT tester
Secure Simple Paring Debug mode to sniff and decrypt the air traffic
Crystal oscillator re-calibration (needed for debug only)
EEPROM configuration update
SW upgrade via UART and I2C

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Application Note 11 Revision 1.2, 2013-12-18
Design Guide
UART with HW flow control (RTS/CTS)
Use of HW flow control is mandatory
UART baud rate may be changed in EEPROM configuration 9.6kbps to 3.25Mbps

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PAN1322
Application Note 12 Revision 1.2, 2013-12-18
Design Guide
The block diagram of the eUniStone module is shown below.
EEPROM
PMB8754
eBMU
26MHz
Crystal
Supply
regulator
Balun filter
RF
singnal
UART
Supply
I2C interface
eUniStone
Onboard
Antenna
LPM
GPIO
I2C
Figure 1. Simplified Block Diagram of eUniStone Module

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PAN1322
Application Note 13 Revision 1.2, 2013-12-18
Design Guide
2Interfaces
2.1 UART Interface
The UART interface is the main communication interface between the host and eUniStone. For the SPP
application, communication between the host and the eUniStone is through AT commands over the
UART interface.
The interface consists of four UART signals for the AT interface and two GPIOs for additional low
power mode control, as shown in Figure 2.
Figure 2. UART Interface
2.1.1 Low Power Mode Control
The use of low power mode (LPM) control is optional. If not used, P0.14 shall be tied to VDDUART.
The low power mode protocol for eUniStone is based on hardware signaling only. No AT commands or
responses are required for the low power mode protocol. The two GPIOs are used to tell the other
device (host or controller) when it may enter low power mode, when it should wake up and when it
cannot transmit because the other device is in low power mode.
To allow the eUniStone to enter low power mode, the host sets pin P0.14 low. When eUniStone is
ready, it will also allow the host to enter LPM by setting P0.0 low. Before entering LPM, the host shall
set UART CTS of eUniStone high. Before entering LPM, eUniStone will set its own UART RTS high.
UARTTXD
UARTRXD
UARTTXD
UARTRXD
UARTRTS
UARTCTS
UARTCTS
UARTRTS
Host
eUniStone
P
0
.
0
P
0
.
14
BT
_
LPM
_
IN
BT
_
LPM
_
OUT

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PAN1322
Application Note 14 Revision 1.2, 2013-12-18
Design Guide
The host can wake up eUniStone by setting UARTCTS of eUniStone low again and setting P0.14 high
again, whereas the eUniStone can wake up the host by setting its own UART RTS low again and setting
P0.0 high again.
Figure 3 shows a case where the host initiates low power mode entry and exit.
Host
eUniStone
Host Output

P 0.14
Host RTS

UARTCTS
Host Input

P 0.00
Host CTS

UARTRTS
Figure 3. Host Initiates Low Power Mode Entry and Exit
1. The host allows eUniStone to enter low power mode
2. eUniStone starts to enter low power mode
3. When UARTRTS is high and P0.0 is low, eUniStone enters low power mode. The host
may now enter low power mode by signaling UARTCTS high.
4. The host requests the eUniStone to wake up
5. eUniStone wakes up. P0.0 goes high and UARTRTS goes low.
Figure 4 shows a case where the host initiates low power mode and the controller wakes up the
host.
Host
eUniStone
Host Output

P 0.14
Host RTS

UARTCTS
Host Input

P 0.0
Host CTS

UARTRTS

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PAN1322
Application Note 15 Revision 1.2, 2013-12-18
Design Guide
Figure 4. Host Initiates Low Power Mode Entry, eUniStone Initiates Exit
1. The host allows eUniStone to enter low power mode
2. eUniStone starts to enter low power mode
3. When UARTRTS is high and P0.0 is low, eUniStone enters low power mode. The host
may now enter low power mode by signaling UARTCTS high.
4. The host enters low power mode.
5. eUniStone wakes up and requests the host to wake up
6. The host wakes up and accept UART data by lowering UARTCTS
2.1.2 Hardware Flow Control
Use of the UART HW flow control pins UARTRTS and UARTCTS is strongly recommended.
If the HW flow control is not used, UARTCTS must be tied low (flow "go"). Floating UARTCTS will result
in random stop of the UART flow.
Without the HW flow control, a buffer overflow can occur on the UART, more probably at higher baud
rate but also possible in lower baud rates due to congestion over the air.
For the LPM protocol, UARTCTS shall be high during LPM. In some cases the module could send events
before the host is completely awake. Therefore LPM shall not be used without HW flow control.
2.2 EEPROM / I2C Interface
As shown in the block diagram (Figure 1), the eUniStone module is equipped with an EEPROM for
storage of the non-volatile information. The size of the EEPROM is 32 kbit.
The EEPROM contains the following partitions:
The Bluetooth Device Data (BD_DATA) Storage
The application software
Application specific data
Production default values
On the PBA31309 module, the communication between the eBMU PMB 8754 and the EEPROM is
carried through a standard I2C bus. The I2C bus is also accessible from external pins, which is useful in
the development or debug phase in case the EEPROM gets corrupted.

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PAN1322
Application Note 16 Revision 1.2, 2013-12-18
Design Guide
2.3 GPIO Interface
Most digital pins on eUniStone can be used as general purpose I/O’s (GPIOs). The GPIO pins are
grouped into two ports: P0 and P1. P0 has 16 pins (P0.0 - P0.15) and P1 has nine pins (P1.0 - P1.8).
The non-reserved pins on port P0 may be controlled with AT commands. The P1 pins are not
controllable through AT commands. They are reserved for use by future applications of the chip.
2.4 JTAG Interface
The pins used for the JTAG interface (TDI, TDO, TMS, TCK and RTCK) can also be used as general
purpose I/Os. The operative interface (JTAG or GPIO) on these pins can be selected through the mode
selection pin JTAG#. When JTAG# is connected to low, the pins are used for JTAG interface. When
JTAG# is connected to high, the pins serve as GPIO pins.
JTAG# has an internal pull-up. If the JTAG functionality is not needed, leave this pin open.

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PAN1322
Application Note 17 Revision 1.2, 2013-12-18
Design Guide
3Power Supply
Main supply voltages (VSUPPLY1 on pin A4, A5 and A6) are required in the range
from 2.9V to 4.1V. All these supplies are internally connected. It is only necessary to
supply one of them.
VDDUART defines the reference level for UART interface. It can be
supplied externally. In this case voltages between 1.35 and 3.6 V are required.
connected to the internal regulator, voltage “Internal 2” on pin VREG (pin No.
C1), if 2.5 V is enough for UART operation (of course, voltage levels of the digital
signals on the UART interface depends from this supply voltage). Ultimately, this
depends on the host.
Note: The state of UART pins is not defined while VDDUART is not supplied. The
host shall not drive any UART pin before the reference levels are stable.
VDD1 defines the reference level for ports P0.0-P0.3. It can be
supplied externally. In this case voltages between 1.35 and 3.6 V are required.
connected to the internal regulator, voltage “Internal 2” on pin VREG (pin No.
C1), if not used.
Note: The state of pins P0.0-P0.3 is not defined while VDD1 is not supplied. The
host shall not drive any of these pins before the reference levels are stable.
3.1 Power up Sequence
The eBMU accesses the EEPROM to load the BD-Data and the application data during startup. The
EEPROM access starts around 22 ms after the RESET# pin is pulled high. Power dropouts during the
start-up phase can cause EEPROM data corruption. The startup typically takes 100ms. If power falls
below the EEPROM’s minimum supply level during the startup phase, a reset shall be applied
immediately. This can be achieved by an external pull-down on RESET#. There is no internal pull
resistor on RESET# on the module.
The sequence of the EEPROM accesses at start-up is shown in Figure 5, During the EEPROM access,
UARTRTS stays high. When the EEPROM access has finished, the UARTRTS signal is pulled down and a
startup response “ROK” is sent via UART to the host. After receiving the startup response, the host is
informed that the eUniStone module is ready to work.
The range for the startup time is indicated for each application SW release in the Release Notes [3].

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PAN1322
Application Note 18 Revision 1.2, 2013-12-18
Design Guide
Figure 5. Example of EEPROM Access at Start-up
3.2 Power down through ONOFF Pin
If VSUPPLY, VDDUART and VDD1 are supplied by the same source, it is not possible to switch off the
module with the ONOFF signal.
When the ONOFF pin is driven low, the reference levels VDDUART and VDD1 must also be switched
off. Otherwise the module would draw current from VDDUART and VDD1, and the output pins would
be “undefined”, i.e. they could drive high or low levels or vary periodically.
One option is to supply VDDUART and VDD1 by pin C1 VREG which connects to the “Internal2” voltage.
Internal2 is switched off when ONOFF goes low. VSUPPLY can remain always on. Precondition for this
is that the host’s UART pins are compatible with the logical levels for Internal2 driven pins indicated in
the data sheet: Input Low max 0.45 V, Output High min 2.1 V. See “Table 18 Internal2 (2.5 V) Supplied
Pins” in the data sheet [1] for the full specification.
If ONOFF is not used, it shall be connected to VSUPPLY.
RESET#
SDA0
UARTRTS
UARTTXD

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PAN1322
Application Note 19 Revision 1.2, 2013-12-18
Design Guide
4Operation Modes
4.1 Command Mode
In command mode which is the default mode after power up or HW/SW reset, all communication by
the host with the module is done using AT commands. The module will respond with different
responses depending on what command was sent. Commands to eUniStone shall be ended with
carriage return and line feed. Responses from eUniStone will be ended in the same way. E.g. for SW
reset, AT+JRES<cr><lf> sent to eUniStone will be responded with ROK<cr><lf>. (“<cr><lf>“ might be
omitted in further descriptions of commands and responses)
After a SPP connection is set up to another device, data is sent using the command AT+JSDA. Data
received from the other side is sent to the host with the response +RDAI. See example in the SPP AT
specification, [2]. Sending and receiving data in command mode is normally used when transmitting
burst and packetized data.
Table 1. Sending and receiving data in command mode
Direction
Command / Response
Note
Host eUniStone
AT+JSDA=008,DataSent<cr><lf>
Data that shall be sent
Host eUniStone
OK<cr><lf>
Positive response that the data was sent
Host eUniStone
+RDAI=012,DataReceived<cr><lf>
Data received
4.2 Stream Mode
Stream mode can only be used after an established SPP connection. In this mode, the host application
will send and receive un-packetized data to and from eUniStone, which are transmitted/received over
the air to the remote device. Carriage return and line feed are not used in either direction, as in
command mode. This mode is normally used when transmitting small size of data in a random way and
for serial cable replacement applications.
Table 2. Sending and receiving data in stream mode
Direction
Stream data
Note
Host eUniStone
DataSent
Data that shall be sent
Host eUniStone
DataReceived
Data received

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PAN1322
Application Note 20 Revision 1.2, 2013-12-18
Design Guide
4.3 Switch from Command Mode to Stream Mode
After a Bluetooth SPP connection has been established, the host can send the command AT+JSCR in
command mode to switch the eUniStone to stream mode. A transparent communication will be
enabled if both sides of the connection are using stream mode.
4.4 Switch from Stream Mode to Command Mode
The host can send the escape string “^ ^ ^” to switch the eUniStone back to command mode. The
string must be sent with the following timing:
Pause time between each “^ “ sign: T1 = 100ms to 1 sec.
Pause time after the last “^” sign: T0 > 1sec.
If the remote device disconnects the link when the eUniStone module is in stream mode, the
eUniStone module will immediately send a „Disconnect Indication“ +RDII to the host and switch back
to command mode automatically.
If the remote device is off (e.g. powered off or out of range) when the eUniStone module is in stream
mode, stream data cannot be transmitted any more on the air. Hardware flow control stops any
further UART communication as soon as the module’s UART input buffer is full. After the link
supervision timeout of 20 s, the module sends a „Disconnect Indication“ +RDII to the host. At that
instant, Any UART data is flushed and the device switches back to command mode automatically.
The host has to wait during the supervision timeout of 20 s. As soon as the UART buffer is full, it is not
possible to leave stream mode or to disconnect the link locally before the supervision timeout expires.
There are two ways to detect a disconnection in stream mode:
1. The host is searching for “+RDII“ in the data stream from the module. The host shall
switch from stream mode to command mode when it recognizes the “+RDII“
indication. Any stream data sent after the “+RDII“ indication will be answered by an
error message “ERR=-1“ (syntax error). If the host after that sends a first command
it will be responded with “ERR=-1“, since the UART is out of sync. The second
command will get the expected response (e.g. “OK”).
2. The GPIO pin P0.1 (pin E5) is used to indicate the connection status. P0.1 is HIGH
when eUniStone device is connected and LOW when there is no connection. The
transition from HIGH to LOW happens prior to sending the “+RDII” indication via
UART. Hosts that cannot monitor the incoming data stream for the "+RDII"
indication in stream mode may monitor P0.1 in eUniStone.
P0.1 is configured as input pin by default. To use this feature the host shall send the AT command
“AT+JGPC=FFFD,0000,0000,0000,FFFD” which configures P0.1 as an output pin.