Philips PTN3501 User manual

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PTN3501
Maintenance and control device
Product specification
Supersedes data of 2000 Nov 22 2001 Jan 17
INTEGRATED CIRCUITS

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2
2001 Jan 17 853-2227 25436
FEATURES
•I2C to parallel port expander
•Internal 256x8 E2PROM
•Self timed write cycle (5 ms typ.)
•16 byte page write operation
•Controlled pull-up on address lines
•Low voltage VCC range of +2.5 V to +3.6 V
•5 V – tolerant I/Os
•Low standby current (< 60 µA )
•Power on Reset
•Supports Live Insertion
•Compatible with SMBus specification version 1.1
•High E2PROM endurance and data retention
•Available in TSSOP20 package
DESCRIPTION
The PTN3501 is a general purpose maintenance and control device.
It features an on-board E2PROM that can be used to store error
codes or board manufacturing data for read–back by application
software for diagnostic purposes.
The eight quasi bidirectional data pins can be independently
assigned as inputs or outputs to monitor board level status or
activate indicator devices such as LEDs.
The PTN3501 has six address pins allowing up to 64 devices to
share the common two wire I2C software protocol serial data bus.
The PTN3501 supports live insertion to facilitate usage in removable
cards on backplane systems.
The PTN3501 is an alternative to the functionally similar PTN3500
for systems where a high number of devices are required to share
the same I2C-bus without need for an additional I2C-bus I/O
expander.
PIN CONFIGURATION
1
2
3
4
5
6
7
20
19
18
17
16
15
14
A0
A1
A2
P0
P1
P2
P3
SDA
SCL
P7
P6
P5
WC
VDD
SW00657
PTN3501
813 P4
9
10
12
11
A5 A3
A4
VSS
INT
Figure 1.
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1,2,3,9,11,12 A0:5 Address Lines
4,5,6,7 P0:3 Quasi–bidirectional I/O pins
10 VSS Ground
13,14,15,16 P4:7 Quasi–bidirectional I/O pins
17 WC Write Control Pin. Should be
tied LOW.
8 INT Interrupt Pin
18 SCL I2C Serial Clock
19 SDA I2C Serial Data
20 VDD Supply Voltage
ORDERING INFORMATION
Type n mber
Package
Type
n
u
mber
Name Description Version
PTN3501DH TSSOP20 Plastic thin shrink small-outline package; 20 leads; body width 4.4 mm SOT360-1
FUNCTIONAL DIAGRAM
I2C
CONTROL 8-BIT I/O PORT P7:0
A5:0
SDA
SCL
E2PROM
256 ×8
WC
INT
SW00647
Figure 2.

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 3
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 3).
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 4).
System configuration
A device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 5).
SDA
SCL
SW00542
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 3. Bit transfer
SDA
SCL P
SDA
SCL
S
SW00543
START CONDITION STOP CONDITION
Figure 4. Definition of start and stop conditions
SDA
SCL
SW00544
MASTER
TRANSMITTER/
RECEIVER SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
Figure 5. System configuration

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 4
Acknowledge (see Figure 6)
The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set–up and hold times must be
taken into account.
A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
S
9821
SW00545
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
ACKNOWLEDGE
NOT ACKNOWLEDGE
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
Figure 6. Acknowledgment on the I2C-bus
FUNCTIONAL DESCRIPTION
SW00788
WRITE PULSE
DATA FROM
SHIFT REGISTER
POWER-ON
RESET
READ PULSE
DATA TO
SHIFT REGISTER
VDD
P0 TO P7
VSS
100 µA
CIS
DQ
FF
CIS
DQ
FF
TO INTERRUPT LOGIC
Figure 7. Simplified schematic diagram of each I/O

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 5
Addressing
For addressing, see Figure 8.
S 0 A5 A4 A3 A2 A1 A0 0 A A5 0 AS 1 A4 A3 A2 A1 A0
a. b.
(a) I/O EXPANDER
(b) MEMORY
SW00648
SLAVE ADDRESSSLAVE ADDRESS
Figure 8. PTN3501 slave addresses
Asynchronous Start
Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The
device does not support a Stop or a repeated Start condition during this time period.
I/O OPERATIONS (see also Figure 7)
Each of the PTN3501’s eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port to the
microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9).
S 0 A5 A4 A3 A2 A1 A0 0 A DATA 1 ADATA 2 ASDA
SCL
tpv
12345678
tpv
DATA 2 VALIDDATA 1 VALID
SW00649
ACKNOWLEDGE
FROM SLAVE
R/WSTART CONDITION ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE FROM SLAVE
SLAVE ADDRESS (I/O EXPANDER) DATA TO PORT DATA TO PORT
WRITE TO
PORT
DATA OUT
FROM PORT
Figure 9. I/O WRITE mode (output)
S 0 A5 A4 A3 A2 A1 A0 1 A DATA 1 ADATA 4 1SDA
tph tps
DATA 4
P
DATA 2 DATA 3
SW00650
SLAVE ADDRESS (I/O EXPANDER) DATA FROM PORT DATA FROM PORT
READ FROM
PORT
DATA INTO
PORT
START CONDITION ACKNOWLEDGE
FROM SLAVE
R/W ACKNOWLEDGE
FROM MASTER STOP CONDITION
DATA 1
INT
tiv tir
Figure 10. I/O READ mode (input)

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 6
Interrupt (see Figs 11 and 12)
The PTN3501 provides an open drain output (INT) which can be fed
to a corresponding input of the microcontroller. This gives these
chips a type of master function which can initiate an action
elsewhere in the system.
An interrupt is generated by any rising or falling edge of the port
inputs in the input mode. After time tiv the signal INT is valid.
Resetting and reactivating the interrupt circuit is achieved when data
on the port is changed to the original setting or data is read from or
written to the port which has generated the interrupt.
Resetting occurs as follows:
•In the READ mode at the acknowledge bit after the rising edge of
the SCL signal
•In the WRITE mode at the acknowledge bit after the
HIGH–to–LOW transition of the SCL signal
•Returning of the port data to its original setting. A second port
state change will require an SCL rising clock edge to be captured
as an INT event.
•Interrupts which occur during the acknowledge clock pulse may
be lost (or very short) due to the resetting of the interrupt during
this pulse.
Each change of the I/Os after resetting will be detected and, after
the next rising clock edge, will be transmitted as INT. Reading from
or writing to another device does not affect the interrupt circuit.
SW00790
PTN3501
(1)
INT
PTN3501
(2)
INT
PTN3501
(16)
INT
MICROCONTROLLER
INT
VDD
Figure 11. Application of multiple PTN3501s with interrupt
S 0 A5 A4 A3 A2 A1 A0 1 A 1 1SDA
SCL 12345678
tir
SW00791
ACKNOWLEDGE
FROM SLAVE
R/WSTART CONDITION STOP CONDITION
SLAVE ADDRESS (I/O EXPANDER) DATA FROM PORT
DATA
INTO P5
INT
P
P5
tiv
Figure 12. Interrupt generated by a change of input to I/O P5

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 7
Quasi-bidirectional I/Os (see Figure 13)
A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH.
In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs.
These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before
being used as inputs.
S 0 A2 A1 A0 0 A A ASDA
SCL 12345678
SW00789
ACKNOWLEDGE
FROM SLAVE
R/WSTART CONDITION ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS (PTN3501) DATA TO PORT DATA TO PORT
1
P3
0
P3
P
P3
OUTPUT
VOLTAGE
P3
PULL-UP
OUTPUT
CURRENT IOHt IOH
A5A4A3
Figure 13. Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW
SYMBOL PARAMETER MIN TYP MAX UNIT
tpv Output data valid; CL≤100 pF – – 4 µs
tps Input data setup time; CL≤100 pF 0 – – µs
tph Input data hold time; CL≤100 pF 4 – – µs
tiv Interrupt input data valid time;
CL≤100 pF – – 4 µs
tir Interrupt reset time; CL≤100 pF – – 4 µs

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 8
MEMORY OPERATIONS
Write operations
Write operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.
Byte Write (see Figure 14)
To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PTN3501 will respond
with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the
data. The PTN3501 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non–volatile memory. Only write and read operations to the
quasi–bidirectional I/Os are allowed during the internal write cycle.
Page Write (see Figure 15)
A page write is initiated in the same way as the byte write, if after
sending the first word of data, the stop condition is not received the
PTN3501 considers subsequent words as data. After each data
word the PTN3501 responds with an acknowledge and the four least
significant bits of the memory address field are incremented. Should
the master not send a stop condition after 16 data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.
P
SW00651
SDA
SLAVE
ADDRESS
(MEMORY) WORD
ADDRESS DATA
S 1 A5 A4 A3 A2 A1 A0 A A
R/W
START CONDITION STOP
CONDITION
0A
ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
Figure 14. Byte write
SP
SDA
SW00652
SLAVE ADDRESS
(MEMORY) WORD ADDRESS DATA TO MEMORY
1 A5A4A3A2A1A0 AA
0
START
CONDITION R/W ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE FROM SLAVE
DATA n A
ACKNOWLEDGE
FROM SLAVE
DATA +3n
DATA TO MEMORY
STOP
CONDITION
A
Figure 15. Page Write

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 9
Read operations
PTN3501 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address’
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.
Current Address Read (see Figure 16)
The PTN3501 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.
When the PTN3501 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.
Random Read (see Figure 17)
The PTN3501’s random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PTN3501 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PTN3501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
Sequential Read (see Figure 18)
The PTN3501 sequential read is an extension of either the current
address read or random read. If the master doesn’t issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PTN3501 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
SP
SW00653
SLAVE ADDRESS
(MEMORY) DATA FROM MEMORY
SDA
START
CONDITION
1A5A4A3A2A1A0 1 A
R/W ACKNOWLEDGE
FROM SLAVE
STOP
CONDITION
Figure 16. Current Address Read
SP
SDA
SW00654
SLAVE ADDRESS
(MEMORY) WORD ADDRESS
1 A5A4A3A2A1A0 AA
0
START
CONDITION R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
A
ACKNOWLEDGE
FROM SLAVE
DATA FROM MEMORY
STOP
CONDITION
S
START
CONDITION
1A5A4A3A2A1A0 1
R/W
SLAVE ADDRESS
(MEMORY)
Figure 17. Random Read
SP
SDA
SW00655
SLAVE ADDRESS
(MEMORY) DATA FROM MEMORY DATA FROM MEMORY
1 A5A4A3A2A1A0 AA
1
START
CONDITION R/W ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE FROM MASTER
DATA n A
ACKNOWLEDGE
FROM MASTER
DATA N+X
STOP
CONDITION
DATA n+1
DATA
FROM MEMORY
Figure 18. Sequential Read

Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 10
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
SYMBOL PARAMETER MIN MAX UNIT
VCC Supply Voltage –0.5 4.0 V
VIInput Voltage VSS – 0.5 5.5 V
IIDC Input Current –20 20 mA
IODC Output Current –25 25 mA
IDD Supply Current –100 100 mA
ISS Supply Current –100 100 mA
Ptot Total Power Dissipation – 400 mW
POTotal Power Dissipation per Output – 100 mW
TSTG Storage Temperature –65 +150 _C
TAMB Operating Temperature –40 +85 _C
VESD Electrostatic Discharge:
Human Body Model, 1.5 kΩ, 100 pF – >2000 V
Machine Model, 0 Ω, 200 pF – >200 V
DC ELECTRICAL CHARACTERISTICS
Tamb = –40_C to +85_C unless otherwise specified; VCC = 3.3 V
SYMBOL PARAMETER MIN TYP MAX UNIT
Supply
VDD Supply Voltage 2.5 3.3 3.6 V
IDDQ Standby Current; A0thru A5, WC = HIGH – 60 µA
IDD1 Supply Current Read – – 1 mA
IDD2 Supply Current Write – – 2 mA
VPOR Power on Reset Voltage – – 2.4 V
Input SCL; input, output SDA
VIL Input LOW voltage –0.5 –0.3 VDD V
VIH Input HIGH voltage 0.7 VDD – 5.5 V
IOL Output LOW current @ VOL = 0.4 V 3 – – mA
ILInput leakage current @ VI= VDD or VSS –1 – 1 µA
CIInput capacitance @ VI= VSS – – 7 pF
I/O Expander Port
VIL Input LOW voltage –0.5 –0.3 VDD V
VIH Input HIGH voltage 0.7 VDD – 5.5 V
IIHL(max) Input current through protection diodes –400 – 400 µA
IOL Output LOW current @ VOL = 1 V 10 25 – mA
IOH Output HIGH current @ VOH = Vss 30 100 300 µA
IOHt Transient pull–up current – 2 – mA
CIInput Capacitance – – 10 pF
COOutput Capacitance – – 10 pF
Address Inputs A0thru A5, WC input
VIL Input LOW voltage –0.5 –0.3 VDD V
VIH Input HIGH voltage 0.7 VDD – 5.5 V
ILInput leakage current @ VI= VDD –1 – 1 µA
Input leakage (pull-up) current @ VI= VSS 10 25 100 µA
Interrupt output INT
IOL Low level output current; VOL = 0.4 V 1.6 – – mA
ILLeakage current @ VI= VDD or VSS –1 – +1 µA