Philips TDA8002C User manual

DATA SHEET
Product specification
Supersedes data of 1999 Feb 24
File under Integrated Circuits, IC02
1999 Oct 12
INTEGRATED CIRCUITS
TDA8002C
IC card interface

1999 Oct 12 2
Philips Semiconductors Product specification
IC card interface TDA8002C
FEATURES
•Single supply voltage interface (3.3 or 5 V environment)
•Low-power sleep mode
•Three specific protected half-duplex bidirectional
buffered I/O lines
•VCC regulation 5 V ±5% or 3 V ±5%, ICC <55mAfor
V
DD = 3.0 to 6.5 V, with controlled rise and fall times
•Thermal and short-circuit protections with current
limitations
•Automatic ISO 7816 activation and deactivation
sequences
•Enhanced ESD protections on card side (>6 kV)
•Clock generation for the card up to 12 MHz with
synchronous frequency changes
•Clock generation up to 20 MHz (external clock)
•Synchronous and asynchronous cards (memory and
smart cards)
•ISO 7816, GSM11.11 compatibility and EMV
(Europay, MasterCardand Visa) compliant
•Step-up converter for VCC generation
•Supplysupervisorforspikeseliminationand emergency
deactivation
•Chip select input for easy use of several TDA8002Cs in
parallel.
APPLICATIONS
IC card readers for:
•GSM applications
•Banking
•Electronic payment
•Identification
•Pay TV
•Road tolling.
GENERAL DESCRIPTION
The TDA8002C is a complete low-power analog interface
forasynchronousandsynchronouscards.Itcanbeplaced
between the card and the microcontroller. It performs all
supply, protection and control functions. It is directly
compatible with ISO 7816, GSM11.11 and EMV
specifications.
ORDERING INFORMATION
TYPE NUMBER PACKAGE
MARKING NAME DESCRIPTION VERSION
TDA8002CT/A/C1 TDA8002CT/A SO28 plastic small outline package; 28 leads; body width
7.5 mm SOT136-1
TDA8002CT/B/C1 TDA8002CT/B
TDA8002CT/C/C1 TDA8002CT/C
TDA8002CG/C1 TDA8002C LQFP32 plastic low profile quad flat package; 32 leads;
body 5 ×5×1.4 mm SOT401-1

1999 Oct 12 3
Philips Semiconductors Product specification
IC card interface TDA8002C
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDD supply voltage 3.0 −6.5 V
IDD(lp) supply current low-power −−150 µA
IDD(idle) supply current Idle mode; fCLKOUT = 10 MHz −−5mA
I
DD(active) supply current active mode; VCC(O) =5V;
f
CLKOUT =10MHz
f
CLK = LOW; ICC = 100 µA−−8mA
f
CLK = 5 MHz; ICC =10mA −−50 mA
fCLK = 5 MHz; ICC =55mA −−140 mA
active mode; VCC(O) =3V;
f
CLKOUT =10MHz
f
CLK = LOW; ICC = 100 µA−−8mA
f
CLK = 5 MHz; ICC =10mA −−50 mA
fCLK = 5 MHz; ICC =55mA −−140 mA
Card supply
VCC(O) output voltage active mode for VCC =5V
I
CC < 55 mA; DC load 4.6 −5.4 V
ICC = 40 nAs; AC load 4.6 −5.4 V
active mode for VCC =3V
I
CC < 55 mA; DC load 2.76 −3.24 V
ICC = 40 nAs; AC load 2.76 −3.24 V
General
fCLK card clock frequency 0 −12 MHz
tde deactivation sequence duration 60 80 100 µs
Ptot continuous total power dissipation
TDA8002CT/x Tamb =−25 to +85 °C−−0.56 W
TDA8002CG Tamb =−25 to +85 °C−−0.46 W
Tamb ambient temperature −25 −+85 °C

1999 Oct 12 4
Philips Semiconductors Product specification
IC card interface TDA8002C
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
FCE246
100 nF 100 nF 470 nF
470 nF
100
nF 100
nF
I/O
TRANSCEIVER
I/O
TRANSCEIVER
I/O
TRANSCEIVER
THERMAL
PROTECTION
VCC
GENERATOR
RST
BUFFER
CLOCK
BUFFER
SEQUENCER
CLOCK
CIRCUITRY
LATCH
OSCILLATOR
INTERNAL OSCILLATOR
2.5 MHz
STEP-UP CONVERTER
INTERNAL
REFERENCE
VOLTAGE SENSE
SUPPLY
EN2
PVCC
EN5
EN4
EN3
CLK
EN1 CLKUP
ALARM
Vref
28
VDDD
13
VDDA
14 12
S1 S2
15
11
VUP
AGND
23 VCC
22 RST
18 PRES
21 CLK
20
17
16
AUX1
AUX2
I/O
10 29
DGND1 DGND2
32
2
1
I/OUC
AUX2UC
AUX1UC
31
30
9
19
27
24
25
8
5
7
6
XTAL2
XTAL1
CLKOUT
26
STROBE
CLKSEL
CLKDIV2
CLKDIV1
MODE
CMDVCC
RSTIN
OFF
CV/TV
3
4
CS
ALARM
TDA8002CG

1999 Oct 12 5
Philips Semiconductors Product specification
IC card interface TDA8002C
PINNING
SYMBOL PIN I/O DESCRIPTION
TYPE
CT/A TYPE CT/B TYPE CT/C TYPE CG
XTAL1 1 1 1 30 I crystal connection or input for external clock
XTAL2 2 2 2 31 O crystal connection
I/OUC 3 3 3 32 I/O data I/O line to and from microcontroller
AUX1UC 4441I/Oauxiliary line 1 to and from microcontroller for synchronous
applications
AUX2UC 5 −−2 I/O auxiliary line 2 to and from microcontroller for synchronous
applications
CS −5 5 3 I chip select control input for enabling pins I/OUC, AUX1UC,
AUX2UC, CLKSEL, CLKDIV1, CLKDIV2, STROBE, CV/TV,
CMDVCC, RSTIN, OFF and MODE; note 1
ALARM 6664Oopen drain PMOS reset output for microcontroller (active
HIGH)
CLKSEL 7775Icontrol input signal for CLK (LOW = XTAL oscillator;
HIGH = STROBE input)
CLKDIV1 8886Icontrol input with CLKDIV2 for choosing CLK frequency
CLKDIV2 9997Icontrol input with CLKDIV1 for choosing CLK frequency
STROBE 10 10 10 8 I external clock input for synchronous applications
CLKOUT 11 11 11 9 O clock output (see Table 1)
DGND1 12 12 12 10 supply digital ground 1
AGND 13 13 13 11 supply analog ground
S2 14 14 14 12 I/O capacitance connection for voltage doubler
VDDA 15 15 15 13 supply analog supply voltage
S1 16 16 16 14 I/O capacitance connection for voltage doubler
VUP 17 17 17 15 I/O output of voltage doubler
I/O 18 18 18 16 I/O data I/O line to and from card
AUX2 19 −−17 I/O auxiliary I/O line to and from card
PRES 20 19 19 18 I card input presence contact (active LOW)
PRES −20 −−I active HIGH card input presence contact
CV/TV −−20 19 I card voltage selection input line (high = 5 V, low = 3 V); note 1
AUX1 21 21 21 20 I/O auxiliary I/O line to and from card
CLK 22 22 22 21 O clock to card output (C3I) (see Table 1)
RST 23 23 23 22 O card reset output (C2I)
VCC 24 24 24 23 O supply for card (C1I)
CMDVCC 25 25 25 24 I start activation sequence input from microcontroller (active
LOW)
RSTIN 26 26 26 25 I card reset input from microcontroller
OFF 27 27 27 26 O open-drain NMOS interrupt output to microcontroller (active
LOW)

1999 Oct 12 6
Philips Semiconductors Product specification
IC card interface TDA8002C
Note
1. A pull-up resistor of 100 kΩconnected to VDD is integrated.
MODE 28 28 28 27 I operating mode selection input (HIGH = normal; LOW = sleep)
VDDD −−−28 supply digital supply voltage
DGND2 −−−29 supply digital ground 2
SYMBOL PIN I/O DESCRIPTION
TYPE
CT/A TYPE CT/B TYPE CT/C TYPE CG
Fig.2 Pin configuration (TDA8002CT/A).
handbook, halfpage
XTAL1
XTAL2
I/OUC
AUX1UC
AUX2UC
ALARM
CLKSEL
CLKDIV1
CLKDIV2
STROBE
CLKOUT
DGND1
AGND
S2
MODE
RSTIN
RST
CLK
VCC
AUX1
AUX2
I/O
VUP
S1
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
TDA8002CT/A
FCE247
OFF
CMDVCC
PRES
Fig.3 Pin configuration (TDA8002CT/B).
handbook, halfpage
XTAL1
XTAL2
I/OUC
AUX1UC
CS
ALARM
CLKSEL
CLKDIV1
CLKDIV2
STROBE
CLKOUT
DGND1
AGND
S2
MODE
RSTIN
RST
CLK
VCC
AUX1
I/O
VUP
S1
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
TDA8002CT/B
FCE248
OFF
CMDVCC
PRES
PRES

1999 Oct 12 7
Philips Semiconductors Product specification
IC card interface TDA8002C
Fig.4 Pin configuration (TDA8002CT/C).
handbook, halfpage
XTAL1
XTAL2
I/OUC
AUX1UC
CS
ALARM
CLKSEL
CLKDIV1
CLKDIV2
STROBE
CLKOUT
DGND1
AGND
S2
MODE
RSTIN
RST
CLK
VCC
AUX1
I/O
VUP
S1
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
TDA8002CT/C
FCE249
OFF
CMDVCC
CV/TV
PRES
Fig.4 Pin configuration (TDA8002CT/C).
Fig.5 Pin configuration (TDA8002CG).
handbook, full pagewidth
TDA8002CG
FCE250
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12 13 14 15 16
32
31
30 29 28 27 26 25
AUX1UC
STROBE
CLKOUT
VDDD I/OUC DGND2
AUX2
XTAL2 XTAL1
I/O
AUX2UC
CS
ALARM
CLKSEL
CLKDIV1
CLKDIV2
DGND1
AGND
S2
VUP
S1
VDDA
RST
CLK
VCC
AUX1
CMDVCC
CV/TV
PRES
MODE RSTIN OFF

1999 Oct 12 8
Philips Semiconductors Product specification
IC card interface TDA8002C
FUNCTIONAL DESCRIPTION
Power supply
The supply pins for the chip are VDDA, VDDD, AGND,
DGND1 and DGND2. VDDA and VDDD (i.e. VDD) should be
in the range of 3.0 to 6.5 V. All card contacts remain
inactive during power-up or power-down.
On power-up, the logic is reset by an internal signal.
The sequencer is not activated until VDD reaches
Vth2 +V
hys2 (see Fig.6). When VDD falls below Vth2, an
automatic deactivation sequence of the contacts is
performed.
Chip selection
The chip select pin (CS) allows the use of several
TDA8002Cs in parallel.
When CS is HIGH, the pins RSTN, CMDVCC, MODE,
CV/TV, CLKDIV1, CLKDIV2, CLKSEL and STROBE
control the chip, pins I/OUC, AUX1UC and AUX2UC are
the copy of I/O, AUX1 and AUX2 when enabled (with
integrated 20 kΩpull-up resistors connected to VDD) and
OFF is enabled.
When CS goes LOW, the levels on pins RSTIN,
CMDVCC, MODE, CV/TV, CLKDIV1, CLKDIV2 and
STROBE are internally latched, I/OUC, AUX1UC and
AUX2UC go to high-impedance with respect to I/O, AUX1
and AUX2 (with integrated 100 kΩpull-up resistors
connected to VDD) and OFF is high-impedance.
Supply voltage supervisor (VDD)
This block surveys the VDD supply. A defined retriggerable
pulse of 10 ms minimum (tW) is delivered on the ALARM
output during power-up or power-down of VDD (see Fig.6).
This signal is also used for eliminating the spikes on card
contacts during power-up or power-down.
When VDD reaches Vth2 +V
hys2, an internal delay (tW) is
started. The ALARM output is active until this delay has
expired. When VDD falls below Vth2, ALARM is activated
and a deactivation sequence of the contacts is performed.
Clock circuitry
The TDA8002C supports both synchronous and
asynchronouscards. There are three methods toclock the
circuitry:
•Apply a clock signal to pin STROBE
•Use of an internal RC oscillator
•Use of a quartz oscillator which should be connected
between pins XTAL1 and XTAL2 or an external clock
applied on XTAL1.
When CLKSEL is HIGH, the clock should be applied to the
STROBE pin. When CLKSEL is LOW, the internal
oscillators is used.
When an internal clock is used, the clock output is
availableon pin CLKOUT. The RC oscillator isselected by
making CLKDIV1 HIGH and CLKDIV2 LOW. The clock
output to the card is available on pin CLK. The frequency
of the card clock can be the input frequency divided by
2 or 4, STOP low or 1.25 MHz, depending on the states of
CLKDIV1 or CLKDIV2 (see Table 1).
When STROBE is used for entering the clock to a
synchronous card, STROBE should remain stable during
activation sequence otherwise the first pulse may be
omitted.
Do not change CLKSEL during activation. When in
low-power (sleep) mode, the internal oscillator frequency
which is available on pin CLKOUT is lowered to
approximately 16 kHz for power economy purposes.

1999 Oct 12 9
Philips Semiconductors Product specification
IC card interface TDA8002C
Fig.6 ALARM as a function of VDD (tWpulse width minimum of 10 ms).
handbook, full pagewidth
FCE272
VDD
tWtW
Vth2 + Vhys2
Vth2
ALARM
Fig.7 Chip select.
handbook, full pagewidth
tDZ
tSL
CS
CS
INPUTS
FCE245
tSI tIS tDI tID
OFF, I/OUC
AUX1UC, AUX2UC

1999 Oct 12 10
Philips Semiconductors Product specification
IC card interface TDA8002C
Table 1 Clock circuitry definition
Notes
1. X = don’t care.
2. In low-power mode.
3. fint = 32 kHz in low-power mode.
MODE CLKSEL CLKDIV1 CLKDIV2 FREQUENCYOF
CLK FREQUENCYOF CLKOUT
HIGH LOW HIGH LOW 1⁄2fint 1⁄2fint
HIGH LOW LOW LOW 1⁄4fxtal fxtal
HIGH LOW LOW HIGH 1⁄2fxtal fxtal
HIGH LOW HIGH HIGH STOP low fxtal
HIGH HIGH X(1) X(1) STROBE fxtal
LOW(2) X(1) X(1) X(1) STOP low 1⁄2fint(3)
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
forallI/O pins(i.e.I/O,I/OUC,AUX1,AUX1UC,AUX2and
AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to
VDD, thus ensuring proper operation in the event that
VCC ≠VDD.
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output), see Fig.8.
After a delay time td(between 50 and 400 ns), the logic 0
present on the master side is transferred on the slave side.
When the input is back to HIGH level, a current booster is
turned on during the delay tdon the output side and then
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
In the event of a conflict, both lines may remain LOW until
the software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
200 kHz.
When CS is HIGH, I/OUC, AUX1UC and AUX2UC are
internally pulled-up to VDD with 20 kΩresistors. When
CS is LOW, I/OUC, AUX1UC and AUX2UC are
permanently HIGH (with integrated 100 kΩpull-up
resistors connected to VDD).
Fig.8 Master and slave signals.
handbook, full pagewidth
td
MGD703
td td
I/O
I/OUC
conflict idle

1999 Oct 12 11
Philips Semiconductors Product specification
IC card interface TDA8002C
Logic circuitry
After power-up, the circuit has six possible states of
operation. Figure 9 shows the state diagram.
IDLE MODE
After reset, the circuit enters the idle mode. A minimum
number of functions in the circuit are active while waiting
for the microcontroller to start a session:
•All card contacts are inactive
•I/OUC, AUX1UC and AUX2UC are high-impedance
•Oscillator (XTAL) runs, delivering CLKOUT
•Voltage supervisor is active.
LOW-POWER MODE
When pin MODE goes LOW, the circuit enters the
low-power (sleep) mode. As long as pin MODE is LOW no
activation is possible.
If pin MODE goes LOW in the active mode, a normal
deactivation sequence is performed before entering the
low-power mode. When pin MODE goes HIGH, the circuit
enters the normal operating mode after a delay of at least
6 ms (96 cycles of CLKOUT). During this time the
CLKOUT remains at 16 kHz.
•All card contacts are inactive
•Oscillator (XTAL) does not operate
•The VDD supervisor, ALARM output, card presence
detection and OFF output remain functional
•Internal oscillator is slowed to 32 kHz, providing 16 kHz
on CLKOUT.
ACTIVE MODE
When the activation sequence is completed, the
TDA8002C will be in the active mode. Data is exchanged
between the card and the microcontroller via the I/O lines.
Fig.9 State diagram.
handbook, full pagewidth
MGE735
POWER
OFF
ACTIVE
MODE
LOW-POWER
MODE
IDLE
MODE FAULT
ACTIVATION
DEACTIVATION

1999 Oct 12 12
Philips Semiconductors Product specification
IC card interface TDA8002C
ACTIVATION SEQUENCE
From Idle mode, the circuit enters the activation mode
when the microcontroller sets the CMDVCC line LOW or
sets the MODE line HIGH when the CMDVCC line is
already LOW. The internal circuitry is then activated, the
internal clock is activated and an activation sequence is
executed. When RST is enabled it becomes the inverse of
RSTIN.
Figures 10 to 12 illustrate the activation sequence as
follows:
1. Step-up converter is started (t1≈t0)
2. VCC risesfrom 0 to 3 or 5 V (t2=t
1+1
1
⁄
2
T)(according
to the state on pin CV/TV)
3. I/O, AUX1 and AUX2 are enabled and CLK is enabled
(t3=t
1+ 4T); I/O, AUX1 and AUX2 were forced LOW
until this time
4. CLK is set by setting RSTIN to HIGH (t4)
5. RST is enabled (t5=t
1+ 7T); after t5, RSTIN has no
further action on CLK, but is only controlling RST.
The value of VCC (5 or 3 V) must be selected by the level
on pin CV/TV before the activation sequence.
Fig.10 Activation sequence using RSTIN and CMDVCC.
handbook, full pagewidth
FCE273
OSC_INT/64
CMDVCC
VUP
VCC
I/O
CLK
RSTIN
RST
LOW
tact
t0
t1
t2t3
t4
t5
T = 25 µs

1999 Oct 12 13
Philips Semiconductors Product specification
IC card interface TDA8002C
Fig.11 Activation sequence using CMDVCC, CLKDIV1 and CLKDIV2 signals to enable CLK.
handbook, full pagewidth
FCE274
OSC_INT/64
CMDVCC
VUP
VCC
I/O
CLK
RSTIN
RST
LOW
tact
t0
t1
t2t3
CLKDIV1
CLKDIV2
Fig.12 Activation sequence for synchronous application.
handbook, full pagewidth
FCE251
VCC
I/O
AUX1UC
AUX1
RSTIN
RST
STROBE
CMDVCC
tact
CLK

1999 Oct 12 14
Philips Semiconductors Product specification
IC card interface TDA8002C
DEACTIVATION SEQUENCE
When a session is completed, the microcontroller sets the
CMDVCC line to HIGH state or MODE line to LOW state.
The circuit then executes an automatic deactivation
sequence by counting the sequencer down and thus end
in the Idle mode.
Figures 13 and 14 illustrate the deactivation sequence as
follows:
1. RST goes LOW (t11 ≈t10)
2. CLK is stopped (t12 =t
11 +1⁄2T)
3. I/O, AUX1 and AUX2 fall to zero (t13 =t
11 +T)
4. VCC falls to zero (t14 =t
11 +1
1
⁄
2
T); a special circuit
ensures that I/O remains below VCC during the falling
slope of VCC
5. VUP falls (t15 =t
11 + 5T).
handbook, full pagewidth
FCE479
CMDVCC
VUP
OSC_INT/64
VCC
I/O
CLK
RSTIN
RST
LOW
tde
t10
t11
t12
t13
t14
t15
Fig.13 Deactivation sequence

1999 Oct 12 15
Philips Semiconductors Product specification
IC card interface TDA8002C
Fault detection
The following fault conditions are monitored by the circuit:
•Short-circuit or high current on VCC
•Removing card during transaction
•VDD dropping
•Overheating.
When one or more of these faults are detected, the circuit
pulls the interrupt line OFF to its active LOW state and a
deactivation sequence is initiated. In the event that the
card is present the interrupt line OFF is set to HIGH state
when the microcontroller has reset the CMDVCC line
HIGH (after completion of the deactivation sequence).
In the event that the card is not present OFF remains
LOW.
handbook, full pagewidth
FCE480
I/O
CLK
RST
LOW
tde
OFF
PRES
VCC
t10
t11
t12
t13
t14
OSC_INT/64
Fig.14 Emergency deactivation sequence.

1999 Oct 12 16
Philips Semiconductors Product specification
IC card interface TDA8002C
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1.
Note
1. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional
operation of the device under this condition is not implied.
HANDLING
Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin with respect to ground.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage −0.3 +6.5 V
VDDA analog supply voltage −0.3 +6.5 V
VCC card supply voltage pins;
XTAL1, XTAL2, ALARM, CS, MODE,
RSTIN, CLKSEL, AUX2UC, AUX1UC,
CLKDIV1, CLKDIV2, CLKOUT,
STROBE, CMDVCC, CV/TV and OFF
−0.3 +6.5 V
Vi(card) input voltage on card contact pins;
I/O, AUX2,PRES,PRES,AUX1, CLK,
RST and VCC
−0.3 +6.5 V
Ves electrostatic handling voltage
on pins I/O, AUX2, PRES, PRES,
AUX1, CLK, RST and VCC
−6+6kV
on all other pins −2+2kV
T
stg storage temperature −55 +125 °C
Ptot continuous total power dissipation
TDA8002CT/x Tamb =−25 to +85 °C−0.56 W
TDA8002CG Tamb =−25 to +85 °C−0.46 W
Tamb ambient temperature −25 +85 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air
SOT136-1 70 K/W
SOT401-1 91 K/W

1999 Oct 12 17
Philips Semiconductors Product specification
IC card interface TDA8002C
CHARACTERISTICS
VDD = 3.3 V; Tamb =25°C; fxtal = 10 MHz; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDD supply voltage 3 −6.5 V
IDD(lp) supply current low-power mode −−150 µA
IDD(idle) supply current Idle mode; fCLKOUT = 10 MHz −−5mA
I
DD(active) supply current active mode; VCC(O) =5V;
f
CLKOUT =10MHz
f
CLK = LOW; ICC = 100 µA−−8mA
f
CLK = 5 MHz; ICC =10mA −−50 mA
fCLK = 5 MHz; ICC =55mA −−140 mA
active mode; VCC(O) =3V;
f
CLKOUT =10MHz
f
CLK = LOW; ICC = 100 µA−−8mA
f
CLK = 5 MHz; ICC =10mA −−50 mA
fCLK = 5 MHz; ICC =55mA −−140 mA
Vth2 threshold voltage on VDD for
voltage supervisor falling 2.2 −2.4 V
Vhys2 hysteresis on Vth2 50 100 150 mV
Card supply
VCC(O) output voltage Idle mode −−0.3 V
active mode
VCC =5V;I
CC < 55 mA;
DC load 4.6 −5.4 V
ICC = 40 nAs; AC load 4.6 −5.4 V
VCC = 3 V; ICC < 55 mA;
DC load 2.76 −3.24 V
ICC = 24 nAs; AC load 2.76 −3.24 V
ICC(O) output current VCC(O) = from 0 to 5 or 3 V −−55 mA
VCC short-circuited to ground −200 −mA
SR slew rate rising or falling slope 0.10 0.15 0.20 V/µs
Crystal connections (XTAL1 and XTAL2)
Cext external capacitors note 1 −15 −pF
fxtal resonance frequency note 2 2 −24 MHz

1999 Oct 12 18
Philips Semiconductors Product specification
IC card interface TDA8002C
Data lines
GENERAL
td(edge) delay between falling edge
of I/O, AUX1, AUX2, I/OUC,
AUX1UC and AUX2UC
−−1µs
t
r
, tfrise and fall times Ci=C
o=30pF −−0.5 µs
fI/O(max) maximum frequency on
data lines −−200 kHz
DATA LINES I/O, AUX1 AND AUX2 (WITH 10 KΩPULL-UP RESISTOR CONNECTED TO VCC)
Vooutput voltage Idle and low-power modes 0 −0.3 V
VOH HIGH-level output voltage
on data lines IOH =−20 µA 0.8VCC −VCC V
VOL LOW-level output voltage on
data lines II/O =1mA −−0.4 V
VIH HIGH-level input voltage on
data lines 0.6VCC −VCC V
VIL LOW-level input voltage on
data lines 0−0.5 V
Vidle voltage on data lines
outside a session −−0.4 V
Rpu internal pull-up resistance
between data lines and VCC
81012kΩ
I
edge current from data lines
when active pull-up is active −1−mA
IIL LOW-level input current on
data lines VIL = 0.4 V −−−600 µA
IIH HIGH-level input current on
data lines VIH =V
CC −−10 µA
DATA LINES I/OUC, AUX1UC AND AUX2UC (WITH 20 KΩPULL-UP RESISTOR CONNECTED TO VDD WHEN CS IS HIGH AND
100 KΩWHEN CS IS LOW)
VOH HIGH-level output voltage
on data lines IOH =−20 µAV
DD −1−VDD + 0.2 V
VOL LOW-level output voltage on
data lines II/OUC =1mA −−0.4 V
VIH HIGH-level input voltage on
data lines 0.7VDD −VDD V
VIL LOW-level input voltage on
data lines 0−0.3VDD V
Zidle impedance on data lines
outside a session 10 −− MΩ
ALARM and OFF when connected (open-drain outputs)
IOH(OFF) HIGH-level output current
on pin OFF VOH(OFF) =5V −−5µA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 12 19
Philips Semiconductors Product specification
IC card interface TDA8002C
VOL(OFF) LOW-level output voltage on
pin OFF IOL(OFF) =2mA −−0.4 V
IOL(ALARM) LOW-level output current on
pin ALARM VOL(ALARM) =0V −−−5µA
V
OH(ALARM) HIGH-level output voltage
on pin ALARM IOH(ALARM) =−2mA V
DD −1−− V
t
WALARM pulse width 6 −20 ms
Clock output (CLKOUT; powered from VDD)
fCLKOUT frequency on CLKOUT 0 −20 MHz
low power −16 −kHz
VOL LOW-level output voltage IOL = 1 mA 0 −0.5 V
VOH HIGH-level output voltage IOH =−1mA V
DD −0.5 −− V
t
r
, tfrise and fall times CL= 15 pF; notes 3 and 4 −−8ns
δduty factor CL= 15 pF; notes 3 and 4 40 −60 %
Internal oscillator
fint frequency of internal
oscillator active mode 2 2.5 3 MHz
sleep mode −32 −kHz
Card reset output (RST)
VO(inact) output voltage inactive modes 0 −0.3 V
td(RST) delay between RSTIN and
RST RST enabled −−100 ns
VOL LOW-level output voltage IOL = 200 µA0−0.3 V
VOH HIGH-level output voltage IOH =−200 µAV
CC −0.5 −VCC V
tr, tfrise and fall times CL=30pF −−0.5 ns
Card clock output (CLK)
VO(inact) output voltage inactive modes 0 −0.3 V
VOL LOW-level output voltage IOL = 200 µA0−0.3 V
VOH HIGH-level output voltage IOH =−50 µAV
CC −0.5 −VCC V
tr, tfrise and fall times CL= 30 pF; note 3 −−8ns
δduty factor CL= 30 pF; note 3 45 −55 %
SR slew rate (rise and fall) 0.2 −− V/ns
Strobe input (STROBE)
fSTROBE frequency on STROBE 0 −10 MHz
VIL LOW-level input voltage 0 −0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD V
Logic inputs (CLKSEL, CLKDIV1, CLKDIV2, MODE, CMDVCC and RSTIN); note 5
VIL LOW-level input voltage 0 −0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 12 20
Philips Semiconductors Product specification
IC card interface TDA8002C
LOGIC INPUTS (CV/TV AND CS) (INTEGRATED 10 KΩPULL-UP RESISTOR CONNECTED TO VDD); note 5
VIL LOW-level input voltage 0 −0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD V
Logic inputs PRES and PRES; note 5
VIL LOW-level input voltage 0 −0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD V
IIL(PRES) LOW-level input current on
pin PRES VOL =0V −−−10 µA
IIH(PRES) HIGH-level input current on
pin PRES −−10 µA
Protections
Tsd shut-down local
temperature −135 −°C
I
CC(sd) shut-down current at VCC −−90 mA
Timing
tact activation sequence
duration guaranteed by design; see Fig.12 −180 220 µs
tde deactivation sequence
duration guaranteed by design; see Fig.14 50 70 100 µs
t3start of the window for
sending CLK to the card see Figs 10 and 11 −−130 µs
t5end of the window for
sending CLK to the card see Fig.11 150 −− µs
t
IS time from input to select 100 −− ns
tSI time from select to input 1000 −− ns
tID time from input to deselect 1000 −− ns
tDI time from deselect to input 100 −− ns
tSL time from select to low
impedance −−40 ns
tDZ time from deselect to high
impedance pull-up resistor at pin OFF = 10 kΩ; 1 device −−6ns
2 devices in parallel −−3ns
t
r(max) maximum rise time on pin
CS −−100 ns
tf(max) maximum fall time on pin
CS −−100 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT