Phytec phyCORE-P8xC51Mx2 User manual

A product of a PHYTEC Technology Holding company
phyCORE-P8xC51Mx2
Hardware Manual
Edition April 2005

phyCORE-P8xC51Mx2
PHYTEC Messtechnik GmbH 2005 L-602e_3
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2005 PHYTEC Messtechnik GmbH, D-55129 Mainz
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or in
part - are reserved. No reproduction may occur without the express written consent
from PHYTEC Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone] [e-mail] 1 [phone] [e-mail]
Technical
Support: [phone] [email protected] 1 [phone] [e-mail]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
3rd Edition: April 2005

Contents
PHYTEC Messtechnik GmbH 2005 L-602e_3
Preface...........................................................................................................1
1 Introduction .........................................................................................3
1.1 Blockdiagram................................................................................6
1.2 View of the phyCORE-P8xC51Mx2............................................6
2 Pin Description.....................................................................................7
3 Jumpers..............................................................................................13
3.1 J1 Internal or External Program Memory..................................16
3.2 J2, J3 Pin 1 and Pin 23 on U1....................................................16
3.3 J4 PLD Control..........................................................................17
3.4 J5, J6 RAM Selection................................................................17
3.5 J7 SRAM Supply Voltage..........................................................18
3.6 J8, J9 P3.0 and P3.1 as RxD0 and TxD0 Signals......................18
3.7 J10, J11 P4.0 and P4.1 as 2nd Serial Interface ...........................19
3.8 J12, J13 Pins X1F13 / X1E14 Configuration .............................19
3.9 J14 RS-485 Interface Control....................................................20
3.10 J15, J18 EEPROM Configuration .............................................20
3.11 J16, J17 Configuration of P1.6 and P1.7 for I2C Bus...............21
3.12 J19 RTC Interrupt......................................................................21
3.13 J20 Remote Download Source...................................................22
4 Memory Models.................................................................................23
4.1 Control Register 1.......................................................................25
4.2 Control Register 2.......................................................................28
5 Serial Interfaces.................................................................................30
5.1 RS-232 Interface.........................................................................30
5.2 RS-485 Interface.........................................................................30
6 Flash Memory (U7)............................................................................31
7 Serial EEPROM (U12)......................................................................33
8 Real-Time Clock RTC-8563/64 (U13)..............................................34
9 Reset Controller (U8)........................................................................35
10 Remote Supervisory Chip (U10) ......................................................36
11 Battery Buffer....................................................................................37
12 Technical Specifications....................................................................39
13 Hints for Handling the Module........................................................41

phyCORE-P8xC51Mx2
PHYTEC Messtechnik GmbH 2005 L-602e_3
14 The phyCORE-P8xC51Mx2 on the
phyCORE Development Board LD 5V...........................................43
14.1 Concept of the phyCORE Development Board LD 5V .............43
14.2 Development Board LD 5V Connectors and Jumpers...............45
14.2.1 Connectors.....................................................................45
14.2.2 Jumpers on the
phyCORE Development Board LD 5V.........................46
14.2.3 Unsupported Features and Improper Jumper Settings ..48
14.3 Functional Components on the
phyCORE Development Board LD 5V......................................49
14.3.1 Power Supply at X1.......................................................49
14.3.2 Starting FlashTools .......................................................51
14.3.3 First Serial Interface at Socket P1A..............................53
14.3.4 Power Supply to External Devices via Socket P1A......54
14.3.5 Socket P1B....................................................................56
14.3.6 Plug P2A .......................................................................58
14.3.7 RS-485 Interface at Plug P2B .......................................60
14.3.8 Programmable LED D3.................................................62
14.3.9 Pin Assignment Summary of the phyCORE,
the Expansion Bus and the Patch Field.........................63
14.3.10 Battery Connector BAT1...............................................68
14.3.11 DS2401 Silicon Serial Number.....................................69
14.3.12 Pin Header Connector X4 .............................................70
Index............................................................................................................71

Contents
PHYTEC Messtechnik GmbH 2005 L-602e_3
Index of Figures
Figure 1: Block Diagram..............................................................................6
Figure 2: View of the phyCORE-P8xC51Mx2............................................6
Figure 3: Pinout of the phyCORE-P8xC51Mx2 (Top View) ......................7
Figure 4: Numbered Matrix Overview of the phyCORE-Connector
(Viewed from Above)...................................................................9
Figure 5: Numbering of the Jumper Pads...................................................13
Figure 6: Location of the Jumpers (Top View)..........................................13
Figure 7: Location of the Jumpers (Bottom View)....................................14
Figure 8: Default Memory Model following a Hardware Reset...............24
Figure 9: Von Neumann Memory Model...................................................27
Figure 10: Configuration of the I/O Area ....................................................29
Figure 11: Physical Dimensions (not Shown at Scale) ................................39
Figure 12: Modular Development and Expansion Board Concept with
the phyCORE-P8xC51Mx2........................................................44
Figure 13: Location of Connectors on the
phyCORE Development Board LD 5V ......................................45
Figure 14: Numbering of Jumper Pads ........................................................46
Figure 15: Location of the Jumpers (View of the Component Side)...........47
Figure 16: Default Jumper Settings of the
phyCORE Development Board LD 5V with
phyCORE-P8xC51Mx2..............................................................47
Figure 17: Connecting the Supply Voltage at X1 ........................................50
Figure 18: Pin Assignment of the DB-9 Socket P1A as RS-232
(Front View) ...............................................................................53
Figure 19: Location of Components at U11 and U12 for
Power Supply to External Subassemblies...................................54
Figure 20: Pin Assignment of the DB-9 Socket P1B (Front View).............56

phyCORE-P8xC51Mx2
PHYTEC Messtechnik GmbH 2005 L-602e_3
Figure 21: Pin Assignment of the DB-9 Plug P2A (Front View)................58
Figure 22: Pin Assignment of the DB-9 Plug P2B as RS-485 Interface .....60
Figure 23: Pin Assignment Scheme of the Expansion Bus..........................64
Figure 24: Pin Assignment Scheme of the Patch Field................................64
Figure 25: Connecting the DS2401 Silicon Serial Number.........................70
Figure 26: Pin Assignment of the DS2401 Silicon Serial Number..............70
Index of Tables
Table 1: Pinout of the phyCORE-Connector X1......................................12
Table 2: Jumper Settings Overview..........................................................15
Table 3: J1 Access to External or Internal Program Memory.................16
Table 4: J2, J3 U1 Pins 1 and 23 Connections ........................................16
Table 5: J4 PLD Control..........................................................................17
Table 6: J5, J6 RAM Selection and Mode...............................................17
Table 7: J7 SRAM Supply Voltage .........................................................18
Table 8: J8, J9 Port P3.0 and P3.1 / 1st Serial Interface Configuration...18
Table 9: J10, J11 Port P4.0 and P4.1 / 2nd Serial Interface
Configuration..............................................................................19
Table 10: J12, J13 X1F13 and X1E14 Configuration ...............................19
Table 11: J14 RS-485 Interface Control Configuration ............................20
Table 12: J15, J18 EEPROM Configuration .............................................20
Table 13: J16 and J17 I²C Interface Configuration...................................21
Table 14: J19 RTC Interrupt Configuration ..............................................21
Table 15: J20 Remote Download Source Configuration...........................22
Table 16: Control Register 1 of the Address Decoder................................25
Table 17: Control Register 2 of the Address Decoder................................28
Table 18: EEPROM Memory Options and Addressing..............................33
Table 19: Improper Jumper Settings for the Development Board..............48

Contents
PHYTEC Messtechnik GmbH 2005 L-602e_3
Table 20: JP9 Configuration of the Main Supply Voltage VCCI..............49
Table 21: JP9 Improper Jumper Settings for the Main Supply Voltage....50
Table 22: JP28 Configuration of the Boot Button.....................................51
Table 23: JP28 Configuration of a Permanent FlashTools
Start Condition............................................................................52
Table 24: JP22, JP23, JP10 Configuration of Boot via RS-232 ................52
Table 25: Improper Jumper Settings for Boot via RS-232.........................52
Table 26: Jumper Configuration for the RS-232 Interface.........................53
Table 27: JP24 Power Supply to External Devices Connected to P1A
on the Development Board.........................................................55
Table 28: Jumper Configuration of the DB-9 Socket P1B.........................56
Table 29: Improper Jumper Settings for Configuration of P1B .................57
Table 30: Jumper Configuration for Plug P2A...........................................58
Table 31: Improper Jumper Settings for Plug P2A.....................................59
Table 32: Jumper Configuration for DB-9 Plug P2B as RS-485
Interface......................................................................................60
Table 33: Improper Jumper Settings for the RS-485 Interface at
Plug P2B.....................................................................................61
Table 34: JP17 Configuration of the Programmable LED D3...................62
Table 35: Pin Assignment Data/Address Bus for the
phyCORE-P8xC51Mx2 / Development Board /
Expansion Board.........................................................................65
Table 36: Pin Assignment Control Signals for the
phyCORE-P8xC51Mx2 / Development Board /
Expansion Board.........................................................................66
Table 37: Pin Assignment Interface Signals for the
phyCORE-P8xC51Mx2 / Development Board /
Expansion Board.........................................................................66
Table 38: Pin Assignment Power Supply for the
phyCORE-P8xC51Mx2 / Development Board /
Expansion Board.........................................................................67

phyCORE-P8xC51Mx2
PHYTEC Messtechnik GmbH 2005 L-602e_3
Table 39: Unused Pins on the phyCORE-P8xC51Mx2 /
Development Board / Expansion Board.....................................68
Table 40: JP19 Jumper Configuration for Silicon Serial Number Chip....69

Preface
PHYTEC Messtechnik GmbH 2005 L-602e_3 1
Preface
This phyCORE-P8xC51Mx2 Hardware Manual describes the board’s
design and functions. Precise specifications for the P8xC51Mx2
microcontroller can be found in the enclosed microcontroller Data
Sheet/User’s Manual. If software is included please also refer to
additional documentation for this software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration of Electro Magnetic Conformity for the
PHYTEC phyCORE-P8xC51Mx2
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Note:
PHYTEC products lacking protective enclosures are subject to dam-
age by Electro Static Discharge (ESD) and, hence, may only be
unpacked, handled or operated in environments in which sufficient
precautionary measures have been taken in respect to ESD dangers. It
is also necessary that only appropriately trained personnel (such as
electricians, technicians and engineers) handle and/or operate these
products. Moreover, PHYTEC products should not be operated
without protection circuitry if connections to the product’s pin header
rows are longer than 3 m.

phyCORE-P8xC51Mx2
2PHYTEC MMesstechnikGmbH 2005 L-602e_3
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnatic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-P8xC51Mx2 is one of a series of PHYTEC Single
Board Computers (SBCs) that can be populated with different
controllers and, hence, offers various functions and configurations.
PHYTEC supports all common 8- and 16-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro- / mini- and phyCORE
OEM modules which can be embedded directly into the user's
peripheral hardware design.
PHYTEC's microcontroller modules allow engineers to shorten devel-
opment horizons, reduce design costs and speed project concepts from
design to market.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Web Site: http://www.phytec.de http://www.phytec.com
e-mail: [email protected] [e-mail]
Voice: [phone] [phone]
Fax: [phone] [phone]

Introduction
PHYTEC Messtechnik GmbH 2005 L-602e_3 3
1Introduction
The phyCORE-P8xC51Mx2 belongs to PHYTEC’s phyCORE Single
Board Computer (SBC) module family. The phyCORE SBCs
represent the continuous development of PHYTEC Single Board
Computer technology. Like its mini-, micro- and nanoMODUL
predecessors, the phyCORE boards integrate all core elements of a
microcontroller system on a subminiature board and are designed in a
manner that ensures their easy expansion and embedding in peripheral
hardware developments.
As independent research indicates that approximately 70 % of all
Electro Magnetic Interference (EMI) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and
EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE modules achieve their small size through advanced SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD and laser-drilled Microvias
components are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.

phyCORE-P8xC51Mx2
4PHYTEC MMesstechnikGmbH 2005 L-602e_3
The phyCORE-P8xC51Mx2 is a subminiature (55 x 51 mm)
insert-ready Single Board Computer populated with the
Philips P8xC51Mx2 microcontroller family featuring extended
memory addressing. Its universal design enables its insertion in a
wide range of embedded applications. All controller signals and ports
extend from the controller to standard-width (2.54 mm / 0.1 in.) pin
header rows aligning two sides of the board, allowing it to be plugged
like a "big chip" into a target application.
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. The
descriptions in this manual are based on the Philips 8xC51Mx2
controller. No description of compatible microcontroller derivative
functions is included, as such functions are not relevant for the basic
operation of the phyCORE-P8xC51Mx2.

Introduction
PHYTEC Messtechnik GmbH 2005 L-602e_3 5
The phyCORE-P8xC51Mx2 offers the following features:
•subminiature Single Board Computer (55 x 51 mm) achieved
through advanced SMD technology
•populated with the Philips P8xC51Mx2 microcontroller (PLCC-44
packaging) featuring extended memory addressing
•instruction cycle time of 500 ns at 12 MHz clock speed (standard)
•PLCC-socketed controller enables easy emulator connectivity
(optional soldered controller)
•improved interference safety achieved through multi-layer PCB
technology and dedicated Ground pins
•controller signals and ports extend to standard-width (2.54 mm)
pins aligning two sides of the board, enabling it to be plugged like
a "big chip" into target applications
•256 kByte to 2 MB external Flash on-board, enabling In-System
Programming (ISP) with PHYTEC FlashTools
•no dedicated Flash programming voltage required through use of
5 V Flash devices
•128 kByte to 1 MB external SRAM on-board (SMD)
•flexible software-configurable address decoding via a complex
logic device
•two RS-232 interfaces or one RS-232 and one RS-485 interface,
user-configurable
•I²C Real-Time Clock with internal quartz
•up to 1 kByte I²C EEPROM1
•Watchdog device for reset logic and battery control
•Remote Supervisory Circuit1
•3 free Chip Select signals for easy connection of peripheral
devices
•requires single 5 V / < 200 mA or 3 V / < 170 mA supply voltage
1: This feature is under development and not available yet.

phyCORE-P8xC51Mx2
6PHYTEC MMesstechnikGmbH 2005 L-602e_3
1.1 Blockdiagram
Figure 1: Block Diagram
1.2 View of the phyCORE-P8xC51Mx2
Figure 2: View of the phyCORE-P8xC51Mx2
R e s e t /
W a t c h d o g
digital I / O ports
P H I L I P S
8xC51Mx2
P2 / Cntrl
p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
Transceiver
R S - 2 3 2
analog In ports
C n t r l / A d d r
F L A S H
256KB / 2MB R A M 128 KB / 1MB
S1
P0 D a t a
Transceiver
R S - 4 8 5
Transceiver
R S - 2 3 2
A / B
RxD1 / TxD1
RxD0 / TxD0
I2C bus
Latch
A d d r e s s
D e c o d e r
R T C
RxD1
TxD1
RxD0
I2C
Reset
R e m o t e1
S u p e r v i s o r E E P R O M 0.5/1KB1
1: This feature is under development and is not available yet.
TxD0

Pin Description
PHYTEC Messtechnik GmbH 2005 L-602e_3 7
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller User’s Manual/Data
Sheets located on the Spectrum CD. As damage from improper
connections varies according to use and application, it is the user's
responsibility to take appropriate safety measures to ensure that the
module connections are protected from overloading through
connected peripherals.
As Figure 3 indicates, all controller signals extend to standard-width
(2.54 mm / 0.10 in.) pin rows lining two sides the board (referred to as
phyCORE-connector). This allows the phyCORE-P8xC51Mx2 to be
plugged into any target application like a "big chip".
Figure 3: Pinout of the phyCORE-P8xC51Mx2 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ABC DEF
X1
X1
16
17
18
16
17
18

phyCORE-P8xC51Mx2
8PHYTEC MMesstechnikGmbH 2005 L-602e_3
A new numbering scheme for the pins on the phyCORE-connector
has been introduced with the phyCORE specifications. This enables
quick and easy identification of desired pins and minimizes errors
when matching pins on the phyCORE module with the receptacle
socket on the appropriate PHYTEC phyCORE Development
Board LD 5V or your OEM application.
The numbering scheme for the phyCORE-connector is based on a two
dimensional matrix in which column positions are identified by a
letter and row position by a number. Pin 1A, for example, is always
located in the upper left hand corner of the matrix. The pin numbering
values increase moving down on the board. Lettering of the pin
connector rows progresses alphabetically from left to right
(refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-P8xC51Mx2
(viewed from above; phyCORE-connector header pins pointing
down) or with the socket of the phyCORE Development
Board LD 5V / target circuitry. The upper left hand corner of the
numbered matrix (Pin 1A) is thus covered with the corner of the
phyCORE-P8xC51Mx2 marked with a white triangle. The numbering
scheme is always in relation to the PCB as viewed from above, even if
all contacts extend to the bottom of the board.
The numbering scheme is thus consistent for both the module’s
phyCORE-connector as well as mating connectors on the phyCORE
Development Board LD 5V or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCORE-connector’s receptacle socket is
usually assigned a single designator for its position (X1 for example).
In this manner the phyCORE-connector comprises a single, logical
unit regardless of the fact that it could consist of more than one
physical connector. The location of row 1 on the board is marked by a
white triangle on the PCB to allow easy identification.

Pin Description
PHYTEC Messtechnik GmbH 2005 L-602e_3 9
The following figure (see Figure 4) illustrates the numbered matrix
system. It shows a phyCORE-P8xC51Mx2 mounted on a phyCORE
Development Board LD 5V. The shaded area of the phyCORE-
connectors shown below indicates the remaining pins not used in
conjunction with the phyCORE-P8xC51Mx2 which, when plugged
onto the Development Board, does not span the entire length of the
receptacle socket. The phyCORE Development Board LD 5V can
house all phyCORE modules with standard-width (2.54 mm / 0.10 in.)
pin header rows and a maximum of 32 pins per pin header row, A, B,
C, D, E and F.
Figure 4: Numbered Matrix Overview of the phyCORE-Connector
(Viewed from Above)
Many of the controller port pins accessible at header pins along the
edges of the board have been assigned alternate functions that can be
activated via software.
A B C
11
D E F
G
H
114

phyCORE-P8xC51Mx2
10 PHYTEC MMesstechnikGmbH 2005 L-602e_3
Table 1 provides an overview of the pinout of the phyCORE-
connector and shows possible alternative functions of the pins. Please
refer to the microcontroller User’s Manual/Data Sheet for details on
the functions and features of controller signals and port pins.
Pin Number Signal I/O Description
Pin Row X1A
1A ClkIn I Optional external clock generator input
connected directly to XTAL1 of µC
2A P3.3/INT1 I/O Port pin µC
3A P3.5/T1 I/O Port pin µC
4A /CS2 O Pre-decoded Chip Select signal #2
5A /RD O /RD signal
6A, 7A, 8A,
9A, A0, A3, A5, A7 O Address bus from address latch (A0, A3, A5, A7)
10A,
11A, 12A A10A18, A12A20, A15 O Address bus / upper address lines from µC
13A, 14A,
15A AD1, AD3, AD6 O Multiplexed address/data bus from µC
16A, 17A,
18A A16, A19, A21 O Upper address lines from address latch 2 (A16, A19, A21)
Pin Row X1B
1B ClkOut O Optional external clock generator output
connected directly to XTAL2 of µC
2B, 3B, 5B, 7B,
8B, 10B, 12B,
13B, 15B
17B, 18B
GND - Ground 0 V
4B ALE O Address Latch Enable output µC
6B A1 O Address line from address latch 1 (A1)
9B,
11B A8A16, A13A21 O Address bus /upper address lines from µC
14B AD4 I/O Multiplexed address/data line from µC
16B A17 O Address line from address latch 2 (A17)

Pin Description
PHYTEC Messtechnik GmbH 2005 L-602e_3 11
Pin Number Signal I/O Description
Pin Row X1C
1C,
2C P3.2 / /INT0, P3.4 / T0 I/O Port pins µC
3C, 4C /CS1, /CS3 O Pre-decoded Chip Select signal #1, #3
5C /WR, P3.6 I/O /WR signal µC
6C, 7C, 8C A2, A4, A6 O Address bus from address latch 1
(A2; A4; A6)
9C,
10C,
11C
A9A17,
A11A19,
A14A22
O Address bus /upper address lines from µC
12C, 13C,
4C, 15C AD0, AD2, AD5, AD7 I/O Multiplexed address/data bus µC
16C, 17C,
18C A18, A20, A22 O Upper address lines from address latch 2 (A18, A20, A22)
Pin Row X1D
1D VCC - Voltage input +5 VDC
2D, 14D, 15D,
17D, 18D NC - Not used
3D VPP - Porgramming voltage
4D VBAT I Input for connection to external buffer
battery (+)
5D WDI I WDI input of the Reset controller
6D BOOT I Boot = 1 during Reset →starts the Boot
sequence
7D,
8D,
9D,
10D,
11D
P1.0,
P1.1,
P1.3,
P1.6 (SCL),
P3.0 (RxD)
I/O Port pins µC
12D,
13D P4.0 P4.1 I/O Port pins µC
16D SCL O I2C clock output

phyCORE-P8xC51Mx2
12 PHYTEC MMesstechnikGmbH 2005 L-602e_3
Pin Number Signal I/O Description
Pin Row X1E
1E VCC - Voltage input + 5 V
2E, 3E NC - Not used
4E VPD O Voltage output for external buffer
5E, 7E, 8E,
10E, 12E,
13E, 15E
17E, 18E
GND - Ground 0 V
6E /RESET O Reset output of the module,
directly connected with Reset input
9E,
11E P1.4, P3.1 (TxD) I/O Port pins µC
14E A_RxD1 I/O Differential A signal of the RS-485 transceiver
or RxD1 input of the RS-232 transceiver
16E SDA I/O I2C data
Pin Row X1F
1F, 2F, 3F GND - Ground 0 V
4F PFI I Power Fail Input of Reset IC
5F /PF0 O Power Fail Output of Reset IC
6F /RESin I Reset input of the module
7F, 11F, 12F,
17F, 18F NC - Not used
8F, 9F,
10F P1.2, P1.5, P1.7 (SDA) I/O Port pins µC
13F B_TxD1 I/O Differential B signal of the RS-485 transceiver
or TxD1 output of the RS-232 transceiver
14F TxD0 O Transmit output of the RS-232 transceiver
15F RxD0 I Receive input of the RS-232 transceiver
16F /INTRTC O Interrupt output RTC
Table 1: Pinout of the phyCORE-Connector X1