Phytec phyCORE-TC1796 User manual

A product of a PHYTEC Technology Holding company
phyCORE-TC1796
Hardware Manual
Edition May 2009

phyCORE-TC1796
©PHYTEC Messtechnik GmbH 2009 L-719e_2
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark (™) and copyright (©) symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibi-
lity for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guar-
antee nor accepts any liability whatsoever for consequential damages resulting
from the use of this manual or its associated product. PHYTEC Messtechnik
GmbH reserves the right to alter the information contained herein without prior
notification and accepts no responsibility for any damages which might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
©Copyright 2009 PHYTEC Messtechnik GmbH, D-55129 Mainz. Rights -
including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part -
are reserved. No reproduction may occur without the express written consent from
PHYTEC Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
[email protected] 1 [phone] [email protected]
Technical
Support: [phone]
[email protected] 1 [phone] [email protected]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
2st Edition: May 2009

Table of Contents
©PHYTEC Meßtechnik GmbH 2009 L-719e_2
Preface 1
1Introduction.........................................................................................3
1.1 Block Diagram .............................................................................6
1.2 View of the phyCORE-TC1796...................................................7
2Pin Description....................................................................................9
3Jumpers..............................................................................................22
4Power System and Reset Behavior..................................................30
5Power-On-Reset Characteristics .....................................................31
6System Memory.................................................................................33
6.1 Memory Model following Reset................................................33
6.2 Runtime Memory Model............................................................33
6.3 Flash Memory ............................................................................35
6.3.1 Standard Flash...............................................................35
7Serial Interfaces.................................................................................36
7.1 RS-232 Interface (U5)................................................................36
7.2 CAN Interface ............................................................................38
7.3 On-Chip Debug Support (OCDS1)............................................39
7.4 USB to UART Bridge (U10)......................................................42
8Hardwired TCP/IP Ethernet Controller (U21)..............................43
8.1 MAC Address.............................................................................43
9SPI to IIC Master Controller SC18IS600 (U11 / U12)..................45
10 SPI Memory, EEPROM / FLASH (U13)........................................46
11 Real-Time Clock RTC-8564 (U14)..................................................47
12 Standby Power Supply .....................................................................48
13 OCDS2 debugging.............................................................................48
14 microSD-card slot X4 .......................................................................49
15 Technical Specifications ...................................................................50
16 Hints for Handling the phyCORE-TC1796....................................53
17 Revision History................................................................................54
Appendice A ...............................................................................................55
A.1 Release Notes.............................................................................55
Index 56

phyCORE-TC1796
©PHYTEC Messtechnik GmbH 2009 L-719e_2
Index of Figures
Figure 1: Block Diagram phyCORE-TC1796........................................... 6
Figure 2: View of the phyCORE-TC1796 (Controller Side).................... 7
Figure 3: View of the phyCORE-TC1796 (Connector Side).................... 8
Figure 4: Pinout of the phyCORE-Connector (view from Connector Side)11
Figure 5: Numbering of the Jumper Pads................................................ 22
Figure 6: Location of the Jumpers (Controller Side) .............................. 22
Figure 7: Location of the Jumpers (Connector Side).............................. 23
Figure 8: OCDS1/JTAG interface X1 ( connector side)........................ 40
Figure 9: Physical Dimensions TOP VIEW............................................ 50

Table of Contents
©PHYTEC Meßtechnik GmbH 2009 L-719e_2
Index of Tables
Table 1: Pinout of the phyCORE-Connector X3...................................21
Table 2: Jumper Settings........................................................................28
Table 3: Runtime Memory Map.............................................................34
Table 4: OCDS1 Connector X1 Pin Assignment...................................41

Preface
Preface
This phyCORE-TC1796 Hardware Manual describes the board's
design and functions. Precise specifications for Infineon’s TC1796
TriCore microcontroller series controller can be found in the enclosed
microcontroller Data Sheet/User's Manual. If software is included
please also refer to additional documentation for this software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration of Electro Magnetic Conformance of the
PHYTEC phyCORE-TC1796
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 1

phyCORE-TC1796
2©PHYTEC Meßtechnik GmbH 2009 L-719e_2
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformance only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-TC1796 is one of a series of PHYTEC Single Board
Computers that can be populated with different controllers and, hence,
offers various functions and configurations. PHYTEC supports all
common 8- and 16-bit as well as selected 32-bit controllers in two
ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 3
1Introduction
The phyCORE-TC1796 belongs to PHYTEC’s phyCORE Single
Board Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.

phyCORE-TC1796
4©PHYTEC Meßtechnik GmbH 2009 L-719e_2
The phyCORE-TC1796 is a subminiature (71,5 x 57) insert-ready
Single Board Computer populated with Infineon’s TC1796 Tricore
microcontroller. Its universal design enables its insertion in a wide
range of embedded applications. All controller signals and ports
extend from the controller to high-density pitch (0.635 mm)
connectors aligning two sides of the board, allowing it to be plugged
like a “big chip” into a target application.
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. The
descriptions in this manual are based on the Infineon TC1796 Tricore
microcontroller. No description of compatible microcontroller
derivative functions is included, as such functions are not relevant for
the basic functioning of the phyCORE-TC1796.

Introduction
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 5
The phyCORE-TC1796 offers the following features:
•subminiature SBC in phyCORE dimensions 71,5 x 57 mm with
two 160-pin high-density (0.635 mm) Molex connectors, enabling
it to be plugged like a “big chip” into target application
•Processor: Infineon Tricore TC1796, 20 MHz external clock
•Internal Components of the phyCORE-TC1796:
-High performance 32-bit TriCORE CPU
-2MByte Program Flash Memory
-DMA Controller
-two synchronous serial interfaces
-two UARTs
-MultiCAN 2.0B (4 Nodes) (one CAN node supports TTCAN)
-Capture and Compare units
-Two General Purpose Timer Unit (GPTU) timers with
additional Local Timer Cell Array (LTCA2)
-Two 16-channel Analog-to-Digital Converter units (ADC) with
selectable 8-bit, 10-bit, or 12-bit resolution
-One 4-channel Fast Analog-to-Digital Converter unit (FADC)
-44 analog input lines for ADC and FADC
-Multi-purpose I/O signals
•Memory Configuration1:
-SRAM (2 Banks): 8MByte maximum
-Flash-ROM: 64 MByte Intel Strata Flash maximum;
-SPI memory: 32Kbyte EEPROM or 2MByte Flash
•two I2C – Bus Master –Controller (SC18IS600)
•I2C Real-Time Clock with calendar and alarm functions
•Ethernet-Controller mit HW TCP/IP-Stack (W5300) 10/100Mbit
(PHY)
•Optional USB to UART Bridge
•UART: RS-232 transceiver for two channels
(RxD/TxD); TTL level can be configured
•MultiCAN port: SN65HVD23x transceiver for all
channels; TTL level can be configured
•JTAG/Debug port
1: Please contact PHYTEC for more information about additional modul configurations.

phyCORE-TC1796
Operating temperature:: -40°C to +85°C
1.1 Block Diagram
6©PHYTEC Meßtechnik GmbH 2009 L-719e_2
Figure 1: Block Diagram phyCORE-TC1796

Introduction
1.2 View of the phyCORE-TC1796
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 7
Figure 2: View of the phyCORE-TC1796 (Controller Side)

phyCORE-TC1796
8©PHYTEC Meßtechnik GmbH 2009 L-719e_2
Figure 3: View of the phyCORE-TC1796 (Connector Side)

Pin Description
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 9
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user's responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector). This allows the
phyCORE-TC1796 to be plugged into any target application like a
"big chip".
A new numbering scheme for the pins on the phyCORE-connector has
been introduced with the phyCORE specifications. This enables quick
and easy identification of desired pins and minimizes errors when
matching pins on the phyCORE module with the phyCORE-connector
on the appropriate PHYTEC Development Board or in user target
circuitry.
The numbering scheme for the phyCORE-connector is based on a two
dimensional matrix in which column positions are identified by a letter
and row position by a number. Pin 1A, for example, is always located
in the upper left hand corner of the matrix. The pin numbering values
increase moving down on the board. Lettering of the pin connector
rows progresses alphabetically from left to right
(refer to Figure 4).

phyCORE-TC1796
10 ©PHYTEC Meßtechnik GmbH 2009 L-719e_2
The numbered matrix can be aligned with the
phyCORE-TC1796 (viewed from above; phyCORE-connector
pointing down) or with the socket of the corresponding phyCORE
Development Board/user target circuitry. The upper left-hand corner
of the numbered matrix (pin 1A) is thus covered with the corner of the
phyCORE-TC1796 marked with a white triangle. The numbering
scheme is always in relation to the PCB as viewed from above, even if
all connector contacts extend to the bottom of the module.
The numbering scheme is thus consistent for both the module’s
phyCORE-connector as well as mating connectors on the phyCORE
Development Board or target hardware, thereby considerably reducing
the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCORE-connector is usually assigned a
single designator for its position (X3 for example). In this manner the
phyCORE-connector comprises a single, logical unit regardless of the
fact that it could consist of more than one physical socketed connector.

Pin Description
The following figure (Figure 4) illustrates the numbered matrix
system. It shows a phyCORE-TC1796 with SMT phyCORE-
connectors on its underside.
Figure 4: Pinout of the phyCORE-Connector (view from Connector Side)
Many of the controller port pins accessible at the connectors along the
edges of the board have been assigned alternate functions that can be
activated via software.
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 11
/ D C
X3
BA
X
3
1 1
80
80
11
80 80

phyCORE-TC1796
12 ©PHYTEC Meßtechnik GmbH 2009 L-719e_2
Table 1 provides an overview of the pinout of the phyCORE-
connector (X3) , as well as descriptions of possible alternative
functions. Please refer to the Infineon TC1796 User’s Manual/Data
Sheet for details on the functions and features of controller signals
and port pins.
Pin Number Signal I/O Description
Pin Row X3A
1A NC - not connected
2A, 7A, 12A, 17A,
22A, 27A, 32A,
37A, 42A, 47A,
52A, 57A, 62A,
67A, 72A, 77A
GND - Ground 0 V
3A P11 I/O Microcontroller's port P1.1,
used as interrupt input (REQ1)for onboard
I2C Master controller U11
P1.1 free to use if J39 is NOT populated
default: J39 is populated
4A /NMI I /NMI Interrupt of the controller
5A /CS3 O Microcontroller's Chip Select output.
Used for onboard Ethernet Controller U21
Free to use if the (U21) is NOT populated
or jumper J24 is open
(refer to jumper J24)
6A /ADV O Microcontroller's Address Valid Output
8A /BC0 O Microcontroller´s Byte Control signal for
data lines D[0..7].
9A, 10A, 11A,
13A, 14A, 15A,
16A, 18A, 24A,
25A, 26A, 28A
A1, A2, A4,
A7, A9, A10,
A12, A15, A17,
A18, A20, A23
O Microcontroller's Address lines, are used
to access on-board memory
19A, 20A, 21A,
23A, 29A, 30A,
31A, 33A, 38A,
39A, 40A, 41A,
43A, 44A, 45A,
46A
D1, D2, D4,
D7, D9, D10,
D12, D15, D17,
D19, D20, D22,
D25, D27, D28,
D30
I/O Microcontroller´s Data lines, are used to
access on-board memory
34A /WAIT I Microcontroller's wait signal
35A /CS0 O Microcontroller's Chip Select output.
Used for onboard ext.Flash U3/U4
Free to use if (U3/U4) is NOT populated
or jumper J11 is open
(refer to jumper J11)
36A /HLDA O Hold acknowledge I/O of the
Microcontroller

Pin Description
©PHYTEC Meßtechnik GmbH 2009 L-719e_2 13
Pin Number Signal I/O Description
Pin Row X3A
48A LAN_/CS I Chip Select input of the onboard
Ethernet Controller (U21).
Can be used if jumper J24 is open
(refer to jumper J24)
49A /WR O Microcontroller’s write signal
50A BFCLKI I Microcontroller´s burst flash clock input
(clock feedback)
51A BFCLKO O Microcontroller´s Burst flash clock
output
53A /CSRAM2 I Chip Select input of the second RAM
BANK.
can be used if jumper J18 is open
(refer to jumper J18)
54A P115 I/O Microcontroller's port P1.15
Used for onboard red LED
(refer to jumper J19)
55A P113 I/O Microcontroller´s port P1.13
56A P111 I/O Microcontroller´s port P1.11
58A P18 I/O Microcontroller´s port P1.8
59A P17 I/O Microcontroller´s port P1.7
60A P16 I/O Microcontroller´s port P1.6
61A P14 I/O Microcontroller´s port P1.4
63A P314 I/O Microcontroller´s port P3.14
64A P312 I/O Microcontroller´s port P3.12
65A P311 I/O Microcontroller´s port P3.11
66A P39 I/O Microcontroller´s port P3.9
68A P36 I/O Microcontroller´s port P3.6
69A P34 I/O Microcontroller´s port P3.4
70A P33 I/O Microcontroller´s port P3.3
71A P31 I/O Microcontroller´s port P3.1
73A P214 I/O Microcontroller´s port P2.14
74A P212 I/O Microcontroller´s port P2.12
75A P211 I/O Microcontroller´s port P2.11
76A P29 I/O Microcontroller´s port P2.9
78A P26 I/O Microcontroller´s port P2.6
79A P24 I/O Microcontroller´s port P2.4
80A P23 I/O Microcontroller´s port P2.3

phyCORE-TC1796
14 ©PHYTEC Meßtechnik GmbH 2009 L-719e_2
Pin Number Signal I/O Description
Pin Row X3B
1B RTC_CLKOUT O Realtime Clock Clockout
(refer to jumper J35)
2B P10 I/O Microcontroller´s port P1.0,
used as interrupt (REQ0) input for onboard
Ethernet controller U21
P1.1 free to use if J25 is open
(refer to jumper J25)
3B P12 I/O Microcontroller´s port P1.2
used as interrupt (REQ2) input for onboard
I2C Master controller U12
P1.2 free to use if J40 is NOT populated
default: J40 is populated
4B, 9B, 14B, 19B,
24B, 29B, 34B,
39B, 44B, 49B,
54B, 59B, 64B,
69B, 74B, 79B
GND Ground 0 V
5B /CS2 O Microcontroller´s Chip Select signal.
Used for second onboard SRAM-BANK
U19/U20
Free to use if the second RAM-Bank is
NOT populated or Jumper J18 is open
(refer to jumper J18)
6B /CS1 I/O Microcontroller´s Chip Select signal.
Used for first onboard SRAM-BANK
U17/U18
Free to use if the first RAM-Bank is NOT
populated or Jumper J17 is open
(refer to jumper J17)
7B x/RD O Microcontroller´s read signal
8B, 10B, 11B,
12B, 13B, 15B,
16B, 17B, 23B,
25B, 26B, 27B
A0, A3, A5,
A6, A8, A11,
A13, A14, A16,
A19, A21, A22
O Microcontroller´s Address lines, are used to
access on-board memory
18B, 20B, 21B,
22B, 28B, 30B,
31B, 32B, 37B,
38B, 40B, 41B,
42B, 43B, 45B,
46B
D0, D3, D5,
D6, D8,D11,
D13, D14, D16,
D18, D21, D23,
D24, D26, D29,
D31
I/O Microcontroller´s Data lines, are used to
access on-board memory
33B /BC1 O Microcontroller´s Byte control signal for
data lines D[8..15].
35B /HOLD I Microcontroller´s hold request input
36B /BREQ O
Microcontroller´s EBU Bus request
47B /CSCOMB O Microcontroller´s Chip Select Output for
combination function
48B MR/W O Microcontroller´s Motorola-style
Read/Write output
50B /ADV O Microcontroller´s address valid output