PLX Technology PEX 8647-AA RDK Quick user guide

PEX 8647-AA RDK
Hardware Reference Manual
Version 1.2
November 2008
Website: www.plxtech.com
Technical Support: www.plxtech.com/support
Copyright © 2008 by PLX Technology, Inc. All Rights Reserved – Version 1.2
November 10, 2008

© 2008 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor
variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX8647-AA-RDK-HRM-1.2
November 10, 2008

PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved i
PREFACE
NOTICE
This document contains PLX confidential and proprietary information. The contents of this document may not be
copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely
verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured
products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this
information. The information in this document is subject to change without notice. Although every effort has been
made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential
damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes
no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which
may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of
malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8647-AA RDK, a Rapid Development Kit, from a hardware perspective. It
contains a description of all major functional circuit blocks on the board and also is a reference for the creation of
software for this product. This manual also includes complete schematics and bill of materials.
This Hardware Reference Manual is specific to the PEX 8647RDK. In the event of a discrepancy between this
Hardware Reference Manual and the PEX 8647 Data Book, please be sure to follow the instructions and
guidelines as stated in the PEX 8647 Data Book when designing your systems.
REVISION HISTORY
Date Version Comments
December
2007 0.8 Hardware Reference Manual initial release.
January
2008 0.81 Modified Table 2-1, updated BOM and Schematics
April
2008 1.0 Updated BOM and Schematics.
June
2008 1.1 Updated BOM.
November
2008 1.2 Updated Schematics.

PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved iii
CONTENTS
1. General Information.............................................................................................................1
1.1 PEX 8647 Features ..................................................................................................... 2
1.2 PEX 8647-AA RDK Features....................................................................................... 3
2. PEX 8647-AA RDK Hardware Architecture .........................................................................4
2.1 PCI Express Gen 2 Connections................................................................................. 5
2.1.1 PEX 8647 PCI Express Gen 2 Switch.................................................................. 5
2.1.2 PCI Express Card Edge P1.................................................................................. 7
2.1.3 PCI Express Slot Connectors............................................................................... 7
2.1.3.1 PCI Express Connector SLOT 1....................................................................... 7
2.1.3.2 PCI Express Connector SLOT 2....................................................................... 7
2.2 Reference Clock Circuitry............................................................................................ 7
2.3 Reset Circuitry............................................................................................................. 8
2.4 Serial EEPROM........................................................................................................... 8
2.5 I2C Interface ................................................................................................................ 8
2.6 Power Distribution ....................................................................................................... 8
2.7 LED Indicators............................................................................................................. 9
2.7.1 Port Link Status Indication (D10 – D12) ............................................................. 10
2.7.2 Fatal Error Indication (D13) ................................................................................ 10
2.7.3 PEX_INTA# Interrupt Indication (D14) ............................................................... 10
2.7.4 PEX 8647 Voltage Level Monitoring (D8 – D9) .................................................. 10
2.8 GPIO Pins ................................................................................................................. 10
2.9 Upstream Port Select Pins ........................................................................................ 10
2.10 Reserved Pins ........................................................................................................... 11
3. On-Board Connectors, Switches, and Jumpers.................................................................12
3.1 DIP Switches ............................................................................................................. 12
3.1.1 I2C Address Selection (SW2) ............................................................................. 12
3.2 Push-Button Switches ............................................................................................... 12
3.2.1 Manual Reset# (S1) ........................................................................................... 12
3.3 MidBus Footprints (JP1 – JP6).................................................................................. 13
3.4 2.5V Header (JP7)..................................................................................................... 14
3.5 JTAG Header (JP8)................................................................................................... 14
3.6 I2C Port (JP9 – JP10) ................................................................................................ 14
3.7 Reference Clock Header (J1).................................................................................... 15
3.8 ATX HD Power Connector (J2 – J3).......................................................................... 15
4. Bill of Materials/ Schematics..............................................................................................16

PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
iv Copyright © 2008 by PLX Technology, Inc. All rights reserved
FIGURES
Figure 1-1. PEX 8647-AA RDK Component Side View ............................................................. 1
Figure 2-1. PEX 8647-AA RDK Hardware Architecture ............................................................. 4
Figure 2-2. PCI Express Gen 2 Connections............................................................................. 5
Figure 2-3. PEX 8647-AA RDK Reference Clock Circuit ........................................................... 7
Figure 2-4. PEX 8647-AA RDK Reset Circuit ............................................................................ 8
Figure 2-5. PEX 8647-AA RDK Power Subsystem.................................................................... 9
Figure 3-1. Switch SW2 Default Settings................................................................................. 12
Figure 3-2. Midbus 2.0 footprint Dimensions, pin numbering and specification
(Copied from Agilent’s document) .................................................................................... 13
TABLES
Table 2-1. PEX 8647-AA RDK LED Indicator descriptions ........................................................ 9
Table 2-2. Port Link Status LED Functions.............................................................................. 10
Table 2-3. Voltage Level Monitoring LED Functions................................................................ 10
Table 2-4. Strap_Reserved Pin Connections........................................................................... 11
Table 3-1. Switch SW2 Description ......................................................................................... 12
Table 3-2. Signal Names of x8 PCI Express Midbus Footprints .............................................. 13
Table 3-3. Midbus probe footprints vs. Lanes of PEX 8647..................................................... 14
Table 3-4. Pin assignment of JP8............................................................................................ 14
Table 3-5. Pin assignment of JP9 and JP10............................................................................ 14
Table 3-6. Pin assignment of J1 .............................................................................................. 15
Table 3-7. Pin assignment of J1 .............................................................................................. 15

1. General Information
The PLX PEX 8647-AA RDK is a Rapid Development Kit (RDK) based on the PEX 8647, a 48-lane, 3-port
PCI Express Gen 2 (5.0 GT/s) switch. The PEX 8647-AA RDK provides a complete hardware and software
development platform in order to facilitate and accelerate the evaluation of the PEX 8647 while lowering the
design risk and reducing time-to-market. This RDK has a x16 PCI Express edge connector on the upstream port
of the PEX 8647 and it allows the RDK to be directly plugged into a x16 PCI Express connector on a system
board. The PEX 8647-AA RDK can also be plugged into an x8/x4/x1 PCI Express connector by using card edge
adapters.
Figure 1-1. PEX 8647-AA RDK Component Side View
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 1

PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
2 Copyright © 2008 by PLX Technology, Inc. All rights reserved
1.1 PEX 8647 Features
•48-lane, 3-port PCI Express Gen 2 switch with integrated on-chip 5.0 GT/s SerDes
•480 GT/s aggregate bandwidth
•27mm2676-ball Flip-Chip Plastic Ball Grid Array (FCBGA) package
•Typical Power – 3.75W
•Cut-Thru packet latency of less than 140ns (x16 to x16)
•Low power SerDes (under 90mW per lane)
•Fully non-blocking switch architecture
•Ports configurable as x16, with auto link-width negotiation to x8, x4, x2 and x1
•Flexible device configuration
oConfigurable via serial EEPROM, I2C, hardware strapping, or by the host
•Maximum packet payload size of 2,048 bytes
•Lane reversal and polarity reversal support
•Designate any Port as the Upstream Port (Port 0 is recommended)
•Dynamic Buffer Pool Architecture
•Dual-Casting (enhances performance by sending date from one ingress port to two egress ports)
•Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation
•Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic
density)
•Lane and polarity reversal
•Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with
Vaux not supported)
•Conventional PCI-compatible Device Power Management states – D0 and D3hot
•Active State Power Management
•Quality of Service (QoS)
oOne Virtual Channels (VC0) and Eight Traffic classes (TC)
oRound-Robin and Weighted Round-Robin Port arbitration
•Reliability, Availability, Serviceability (RAS) features
oElectromechanical Interlock supported with Power Enable output
oBaseline and Advanced Error Reporting capability
oPerformance Monitoring
Per-Port Payload and Header Counters
Per-traffic type (write, Read, Completion) Counters
oJTAG AC/DC boundary scan
o3-port link status indicators (PEX_PORT_GOOD[8,4,0]#)
o17 GPIO pins
•INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball
support
•Compliant to the following specifications:
oPCI Local Bus Specification, Revision 3.0 (PCI r3.0)
oPCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
oPCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2)
oPCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1)
oPCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
oPCI Express Card Electromechanical (CEM) Specification, Revision 2.0
oPCI ExpressCard CEM r2.0)
oPCI Express Mini Card Electromechanical (CEM) Specification, Revision 1.1
(PCI ExpressCard Mini CEM r1.1)
oIEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,
1990 (IEEE Standard 1149.1-1990)
oIEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture
oIEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions
oIEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture
Extensions (IEEE Standard 1149.6-2003)
oThe I2C-Bus Specification, Version 2.1 (I2C Bus v2.1)

PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 3
1.2 PEX 8647-AA RDK Features
•PLX PEX 8647 PCI Express switch in a 676-ball Flip-Chip Plastic BGA package
•Form factor based on PCI Express Card Electromechanical (CEM) Specification 2.0
•Two downstream PCI Express slot connectors that are spaced to accommodate SLI and Cross-Fire
cables
•Six x8 Gen 2 Midbus footprints for 48 lane PCI Express signal probing
•On-board PCI Express RefClk buffer which supports Spread Spectrum Clocking
•Socketable Serial EEPROM (2.5V)
•Two standard 2x2 headers provides the I2C interface to an I2C master
•DIP switch for I2C address settings
•Manual push-button PERST# capability
•Three Port Status indicator LEDs for visual inspection of link speed and status
•Two ATX Hard disk Power connectors supply a maximum of 150 watts to the downstream slots
•Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8647

2. PEX 8647-AA RDK Hardware Architecture
Figure 2-1. PEX 8647-AA RDK Hardware Architecture
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
4 Copyright © 2008 by PLX Technology, Inc. All rights reserved

2.1 PCI Express Gen 2 Connections
The PEX 8647-AA RDK is designed around the PEX 8647 and is based on the form factor defined in the PCI
Express CEM 2.0 specification. The RDK contains one upstream port, two downstream ports, and six midbus
footprints to allow access to test equipment, such as protocol analyzers, to all PCI Express differential signals.
Each midbus footprint accommodates eight lanes. See Figure 2-2 for details.
Figure 2-2. PCI Express Gen 2 Connections
2.1.1 PEX 8647 PCI Express Gen 2 Switch
The PEX 8647 is a 48-lane, 3-port PCI Express Gen 2 switch with 5GT/s SerDes. As shown in Figure 2-2, port 0
contains lane 0 to lane 15, port 4 contains lane 16 to lane 31, and port 8 contains lane 32 to lane 47.
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 5

2.1.2 PCI Express Card Edge P1
The PEX 8647-AA RDK can plug directly into a x16 PCI Express slot. Port 0, which consists of lane 0 to lane 15,
is connected to the PCI Express Card Edge connector (P1) through two midbus probe footprints (JP5 and JP6).
The PEX 8647-AA RDK uses Port 0 as the upstream port. The card edge provides the main source of +12V and
+3.3V power, along with the reset signal (PERST#) and the system reference clock (REFCLK_P/REFCLK_N).
2.1.3 PCI Express Slot Connectors
The PEX 8647-AA RDK contains two PCI Express slot connectors which connect to the downstream ports of the
PEX 8647. The two downstream ports (port 4 and port 8) are each x16 wide and each is connected to x16 sized
connector. The slots are physically spaced 40.64mm apart in order to allow the insertion of two double slot-wide
endpoints particularly high power and high performance PCI Express graphic cards with SLI or Cross Fire
capabilities. If the number of lanes implemented by the endpoint is less than the sixteen lanes implemented on
the downstream ports of the PEX 8647, they will auto-negotiate to the highest common link width. For example, if
a x8 card plugs into SLOT1, the negotiated link width will be x8. If an x2 card plugs into SLOT2, the negotiated
link width will be x2.
2.1.3.1 PCI Express Connector SLOT 1
Connector SLOT 1 is a vertical-mount (through-hole), x16 PCI Express connector. Cards plugging into SLOT 1
will be perpendicular to the RDK. Lanes 16 to 31 from PEX 8647 are connected to the PCI Express SLOT 1.
Power to SLOT 1 is provided from the ATX hard disk connector J2 and J3.
2.1.3.2 PCI Express Connector SLOT 2
Connector SLOT 2 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into SLOT 2 will
be perpendicular to the RDK. Lanes 32 to 47 from PEX 8647 are connected to the PCI Express SLOT 2. Power to
connector SLOT 2 is provided from the ATX hard disk connector J2 and J3.
2.2 Reference Clock Circuitry
The PEX 8647-AA RDK reference clock circuitry contains a one-to-four differential clock fan out buffer (U2). The
clock fan out buffer is produced by SpectraLinear with part number of CY28400-2. It supports four 100 MHz PCI
Express reference clocks with the option for constant frequency and spread spectrum outputs. When the RDK is
plugged into a PC x16 PCI Express slot, the differential reference clock is taken from the PCIe card-edge, and
distributed to the PEX_REFCLK_P/PEX_REFCLK_N input, two downstream slot connectors, and the reference
clock header. The 3-pin reference clock header J1 provides the reference clock for probing the PCI Express
differential signals on the midbus probe footprints. (See Figure 2-3 for details)
x16
x16
Figure 2-3. PEX 8647-AA RDK Reference Clock Circuit
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 7

2.3 Reset Circuitry
The PEX 8647-AA RDK reset circuitry includes a MAX6420 adjustable reset timer (U4) and manual reset push-
button switch (S1). The reset timer accepts PERST# from the card edge (P1) and from S1 (logical-OR via U3).
The MAX6420 has the capability of adjusting the reset timeout period by changing the value of C122 (0.001μF ≈
3ms). (See Figure 2-4 for details)
Figure 2-4. PEX 8647-AA RDK Reset Circuit
2.4 Serial EEPROM
The PEX 8647-AA RDK contains an 8-pin DIP socket for a serial EEPROM (U9). The board is populated with a
blank Atmel AT25256A 32-Kbit device. The AT25256A device can directly interface to the PEX 8647. When
programmed correctly, the serial EEPROM can be used to change the default configuration of the PEX 8647. A
blank EEPROM results in the default register values set in the PEX 8647. Please refer to the Software
Development Kit (SDK) documentation for additional information on how to program the serial EEPROM.
2.5 I2C Interface
The PEX 8647 implements an I2C slave interface, which allows an external I2C master to read and write device
registers through an out-of-band mechanism. The PEX 8647 I2C interface is accessible via a 7-bit address, at
data rates from 100 Kbps up to 3.4 Mbps. The RDK provides a dipswitch (SW2) to set the lower three bit I2C
address, I2C_ADD[2:0], of PEX 8647 and two cascaded 2x2, 0.1” pitch headers (JP9 and JP10), which interface
to the PEX 8647’s I2C port. This allows for cascading multiple RDKs together using standard ribbon cable, or
connecting various 3rd party I2C test equipment such as the Total Phase Aardvark I2C controller. (See Table 3-5
for pin assignments of JP9 and JP10).
2.6 Power Distribution
The PEX 8647-AA RDK has two sources for DC power. The first source is the card edge connector (P1). The x16
connector provides up to 5.5A at 12V and 3.0A at 3.3V. Card edge power is intended to power only RDK board
components. The dc/dc converter U7 converts 12V from the Card Edge connector to 1.0VCC to support the
SerDes and core power for the PEX 8647. The LDO (U8) converts 3.3V to 2.5VCC to support the IO power for the
PEX 8647. A 2-pin header (JP7) is used to measure the 2.5V current to the PEX 8647.
The second source includes two ATX HD power connectors, J2 and J3, and a 5V to 3.3V step down dc/dc
converter U6. J2 and J3 directly provide 12VCC up to 5.5A to each of PCI Express Edge Card Connectors
SLOT 1 and SLOT 2. The J2 and J3 also provide enough 5V power for the dc/dc converter (U6) to generate
3.3VCC up to 3A for each of SLOT 1 and SLOT 2. In other words, the second power source provides up to 150W
of power to SLOT 1 and SLOT 2 for high power graphic cards application. (See Figure 2-5 for details).
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
8 Copyright © 2008 by PLX Technology, Inc. All rights reserved

ATX HD
Power
Connectors
(J2 & J3)
5V to 3.3VCC
DC/DC
converter
(U6)
12V_A
GND 12V_A
3.3V_A
GND
PCIe Edge Card Connectors
SLOT 1
SLOT 2
12V to 1V
DC/DC
converter
(U7)
PEX 8647
3.3V to2.5V
LDO
(U8)
On board
3.3V Circuits
1.0VCC
GND
PCIe Card
edge
Connector
P1 GND
GND
3.3VCC
2.5VCC
5V_A
JP7
12VCC
Voltage
Monitoring
Circuit
Figure 2-5. PEX 8647-AA RDK Power Subsystem
2.7 LED Indicators
The PEX 8647-AA RDK provides a number of LED indicators including power-on indication, PEX 8647 port link
status indication, fatal error indication, event/error indication, and voltage level monitoring indications. Table 2-1
provides a quick explanation of the various board indicators.
Table 2-1. PEX 8647-AA RDK LED Indicator descriptions
Indicator Type Locations LED On LED Off
Slot Power LED/green color D1 12V power on at PCI Express connectors SLOT 1 and 2 12V power off
Slot Power LED/green color D3 5V power on at PCI Express connectors SLOT 1 and 2 5V power off
Slot Power LED/green color D5 3.3V power on at PCI Express connectors SLOT 1 and 2 3.3V power off
Board Power LED/green color D2 12V power on at PCI Card Edge connector P1 12V power off
Board Power LED/green color D4 3.3V power on at PCI Card Edge connector P1 3.3V power off
PEX 8647 Port Link Status
LED/green color D10 Port 0 activity (see Table 2-2 for details) If LED off, Port 0
link is down
PEX 8647 Port Link Status
LED/green color D11 Port 4 activity (see Table 2-2 for details) If LED off, Port 4
link is down
PEX 8647 Port Link Status
LED/green color D12 Port 8 activity (see Table 2-2 for details) If LED off, Port 8 link is down
PEX 8647 Fatal Error LED/
red color D13 PEX 8647 detected a fatal error. No fatal errors reported
PEX 8647 Event/Error
LED/green color D14 PEX 8647 detected events or errors. No event/error
reported
Voltage level monitoring /bi-
color LED D8 1V to the PEX 8647 (see Table 2-3 for details)
Voltage level monitoring / bi-
color LED D9 2.5 V to the PEX 8647 (see Table 2-3 for details)
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 9

2.7.1 Port Link Status Indication (D10 – D12)
The PEX 8647-AA RDK provides three green color link status LEDs (D10, D11 and D12) to indicate its port 0, port
4, and port 8 link states respectively. LED on, off, and three blinking patterns cover all five states of port link
status. (See Table 2-2 for details)
Table 2-2. Port Link Status LED Functions
Port Link State LED Pattern
Link down off
Link up, 5Gbps, all lanes are up on
Link up, 5Gbps, reduced lanes are up Blinking: 0.5 second on, 0.5 second off
Link up, 2.5Gbps, all lanes are up Blinking: 1.5 second on, 0.5 second off
Link up, 2.5Gbps, reduced lanes are up Blinking: 0.5 second on, 1.5 second off
2.7.2 Fatal Error Indication (D13)
The PEX 8647 provides an output status pin (FATAL_ERR#) which reports the event of a PCI Express fatal error
condition. The RDK connects this output to a red LED (D13) which is lit when a fatal error condition is detected.
Examples of fatal error conditions are data link layer protocol errors, receiver overflow and malformed TLPs. The
PCI Express Base specification provides a complete listing of fatal error conditions. The PEX 8647 Data Book
also provides additional details on the assertion of FATAL_ERR#.
2.7.3 PEX_INTA# Interrupt Indication (D14)
The PEX 8647 provides an output status pin (PEX_INTA#) for signaling various programmable events. The RDK
connects this output to a green LED (D14) for this interrupt output. Please refer to the PEX 8647 Data Book for
additional information on the programmable events for PEX_INTA#.
2.7.4 PEX 8647 Voltage Level Monitoring (D8 – D9)
The PEX 8647-AA RDK provides a voltage level monitoring circuit for the 1V and 2.5V power supplies to the
PEX 8647. The circuit uses an Intersil multiple voltage supervisory chip (ISL6132), two bi-color LEDs (D8 and D9),
and various resistors. When the supplies fall below the +/- 10% range the red LED will turn on. (See Table 2-3 for
details)
Table 2-3. Voltage Level Monitoring LED Functions
LED Green LED on/ Red LED off Green LED off/Red LED on
D8 1V to PEX 8647 within +/- 10% range 1V to PEX 8647 out of +/- 10% range
D9 2.5V to PEX 8647 within +/- 10% range 2.5V to PEX 8647 out of +/- 10% range
2.8 GPIO Pins
The PEX 8647 has twenty GPIO pins. Three of them, PEX_PORT_GOOD[0,4,8]#, are use for port link status and
GPIO pins [19:12] are connected to the external test points on the PEX 8647-AA RDK to be used by external
applications.
2.9 Upstream Port Select Pins
The PEX 8647 has four strap pins, STRAP_UPSTRM_PORSEL[3:0], for upstream port selection. On the RDK, all
these four pins are hard wired to ground with zero ohm resistors. That means port 0 is always the upstream port
on the RDK.
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
10 Copyright © 2008 by PLX Technology, Inc. All rights reserved

2.10 Reserved Pins
The PEX 8647 has seventeen STRAP_RESERVED pins. They are for factory use only and should be set to know
logic states. Table 2-4 shows the list of these reserved pins and their connections in the RDK.
Table 2-4. Strap_Reserved Pin Connections
Name Pin Location Connections on PEX 8647-AA RDK
STRAP_RESERVED0 W3 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED1 Y1 Pull-down with a 1K ohm resistor
STRAP_RESERVED2 W1 Pull-down with a 1K ohm resistor
STRAP_RESERVED3 H3 Pull-down with a 1K ohm resistor
STRAP_RESERVED4 AD24 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED5 AF24 Pull-down with a zero ohm resistor
STRAP_RESERVED6 C4 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED7 G1 Pull-down with a zero ohm resistor
STRAP_RESERVED8 C23 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED9 B24 Pull-down with a zero ohm resistor
STRAP_RESERVED10# A3 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED11 A2 Pull-down with a 1K ohm resistor
STRAP_RESERVED12 G6 Pull-down with a 1K ohm resistor
STRAP_RESERVED14 AC25 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED15 AE25 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED16 AE24 Pull-down with a zero ohm resistor
STRAP_RESERVED17# H24 Set DIP switch to OFF (logic ‘HIGH’)
STRAP_RESERVED18# AB2 Pull-up with a 4.7K ohm resistor
STRAP_RESERVED19# B3 Pull-up with a 4.7K ohm resistor
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 11

3. On-Board Connectors, Switches, and Jumpers
3.1 DIP Switches
The PEX 8647-AA RDK contains one user controllable DIP switch (SW2) for selecting the lower three bits of I2C
address. Each DIP switch position can be either ON (logic ‘LOW) or OFF (logic ‘HIGH). The white squares
in Figure 3-1 indicate which way the switch is connected. The default settings of the I2C address are I2C_ADD[2:]
= 000 or “ON, ON, ON”.
3.1.1 I2CAddress Selection (SW2)
1
ON
23 4
Figure 3-1. Switch SW2 Default Settings
Table 3-1. Switch SW2 Description
SW2 Functional Description Switch Position Settings
PEX 8647 I2C Address bits[2:0].
Default setting is 000b.
1: I2C_ADDR[0]
2: I2C_ADDR[1]
3: I2C_ADDR[2]
4: RSV_17#
I2C_ADD[2:0] PEX 8647 I2C Slave Address
000b 68h
001b 69h
010b 6Ah
011b 6Bh
100b 6Ch
101b 6Dh
110b 6Eh
111b 6Fh
RSV_17#: PLX use only and should be set to “HIGH”
3.2 Push-Button Switches
3.2.1 Manual Reset# (S1)
The PEX 8647-AA RDK provides a manual switch (S1) for PERST# capability. Note that manual PERST# will
only apply warm reset to the PEX 8647 as well as SLOT 1 and SLOT 2.
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
12 Copyright © 2008 by PLX Technology, Inc. All rights reserved

3.3 MidBus Footprints (JP1 – JP6)
PEX 8647-AA RDK provides six strategically placed midbus probe footprints. Each footprint provides 16 channels
and each can support eight PCI Express lanes. The midbus footprints are based on Agilent’s Soft Touch Midbus
Probe, as shown in Figure 3-2, and can be used with Agilent, LeCroy as well as Tektronix retention
mechanism. Table 3-2 shows the signal names and pin locations for each midbus probe.
Figure 3-2. Midbus 2.0 footprint Dimensions, pin numbering and specification
(Copied from Agilent’s document)
Table 3-2. Signal Names of x8 PCI Express Midbus Footprints
Pin # Signal Name Pin # Signal Name
G1 GND
2 GND 1 C0p-Upstream
4 C0p-Downstream 3 C0n-Upstream
6 C0n-Downstream 5 GND
8 GND 7 C1p-Upstream
10 C1p-Downstream 9 C1n-Upstream
12 C1n-Downstream 11 GND
14 GND 13 C2p-Upstream
16 C2p-Downstream 15 C2n-Upstream
18 C2n-Downstream 17 GND
20 GND 19 C3p-Upstream
22 C3p-Downstream 21 C3n-Upstream
24 C3n-Downstream 23 GND
26 GND 25 C4p-Upstream
28 C4p-Downstream 27 C4n-Upstream
30 C4n-Downstream 29 GND
32 GND 31 C5p-Upstream
34 C5p-Downstream 33 C5n-Upstream
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 13

Pin # Signal Name Pin # Signal Name
36 C5n-Downstream 35 GND
38 GND 37 C6p-Upstream
40 C6p-Downstream 39 C6n-Upstream
42 C6n-Downstream 41 GND
44 GND 43 C7p-Upstream
46 C7p-Downstream 45 C7n-Upstream
48 C7n-Downstream 47
G2 GND
Table 3-3. Midbus probe footprints vs. Lanes of PEX 8647
Midbus Probe Footprint Lanes of PEX 8647
JP5 Lane 0 – Lane 7
JP6 Lane 8 – Lane 15
JP1 Lane 16 – Lane 23
JP2 Lane 24 – Lane 31
JP3 Lane 32 – Lane 39
JP4 Lane 40 – Lane 47
3.4 2.5V Header (JP7)
This 2-pin header provides the mechanism for 2.5 volt measurement. It is for internal use only. For regular RDKs,
no header will be assembled and instead a wire will be used to connect pin 1-2 of JP7.
3.5 JTAG Header (JP8)
Header JP8 provides a direct connection to the PEX 8647 JTAG interface. The 10-pin connector is designed to
allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E controller. The pin
assignment for the JTAG header (JP8) is listed on Table 3-4.
Table 3-4. Pin assignment of JP8
Pin # Signal name
1 JTAG_TRST
3 JTAG_TDI
5 JTAG_TDO
7 JTAG_TMS
9 JTAG_TCK
2,4,6,8,10 GND
3.6 I2CPort (JP9 – JP10)
Table 3-5. Pin assignment of JP9 and JP10
Pin # Signal name
1 I2C_SCL
2 GND
3 I2C_SDA
4 NC
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
14 Copyright © 2008 by PLX Technology, Inc. All rights reserved

3.7 Reference Clock Header (J1)
Table 3-6. Pin assignment of J1
Pin # Signal name
1 Refclkp (+)
2 GND
3 Refclkn (-)
3.8 ATX HD Power Connector (J2 – J3)
Table 3-7. Pin assignment of J1
Pin # Signal name
1 +12VDC
2 COM (GND)
3 COM (GND)
4 +5VCC
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved 15

4. Bill of Materials/ Schematics
Item
# Qty Man. Man. Part # Description Package Type Comp. Designator(s) Distributor/pn
SURFACE MOUNT COMPONENTS
1 1 PLX PEX8647-
AA50BC F
IC, PCI Express Gen 2
switch, 48 lane and 3
ports
SMT 676-pin
BGA,
27X27mm,
1mm pitch
U1
2 1
SpectraLine
ar
CY28400OX
C-2
IC, 100MHz Differential
Clock Buffer
SMT, 28-pin
SSOP U2 www.spectralin ear.com
3 1 Fairchild
NC7S08M5
X
IC, Tiny Logic 2-input
AND gate
SMT, 5-pin
SOT-23 U3
4 1 Maxim
MAX6420UK
29-T
IC, Reset controller, Adj.
reset timeout SMT, SOT23-5 U4
5 1 Intersil ISL6132IR IC, multiple voltage
supervisory
SMT, 4x4mm
2
QFN package U5
6 2 Belfuse S7AH-
08E1A0
IC, Non-iso DC/DC
converter, 4.5-14V-to-
0.8/3.63V @ 8A
SMT, 7-pin U6-U7
7 1 Micrel MIC37100-
2.5BS
IC, LDO linear regulator,
output: 2.5V@1A SMT, SOT-223 U8
8 5
Chicago Mini
Lamp
CMDA5CG7
D1Z
LED, green Vf=2.1V,
20mA SMT, 0805 D1-D5
9 4
Chicago Mini
Lamp
CMDA5CG7
D1Z
LED, green, Vf=2.1V,
20mA, SMT, 0805 D10-D12, D14
10 1
Chicago Mini
Lamp
CMDA5DR7
D1Z LED, red, Vf=1.7V, 20mA SMT, 0805 D13
11 2
Chicago Mini
Lamp
CMD15-
22SRUGC
LED, bi-color LED, green-
red
SMT, 4-pin
1206 D8-D9 L6221115CT-
ND
12 1 Omron B3S1002 Switch, Push Button SMT S1
13 1 C&K SDA04H1SK
D
Dip Switch, 4-pos, SDA
series, with extended
actuator
SMT SW2
30 1 Kemet C0603C102
J5RACTU
Cap, Ceramic, 0.001uF,
X7R, 50V, 5% SMT, 0603 C122
31 8 Murata
GRM033R6
1A103KA01
D
Cap, Ceramic, 0.01uF,
X5R, 10V, 10% SMT, 0201
C126-
C128,C143-
C146, C159
490-3166-1-
ND
32 3 Kemet C0603C103
J5RAC
Cap, Ceramic, 0.01uF,
50V, 5% SMT, 0603 C104-C106,
33 4 Muurata
GRM033R6
0J223KE01
D
Cap, Ceramic, 0.022uF,
X5R, 6.3V, 10% SMT, 0201
C129-
C130,C147-
C148
490-3169-1-
ND
34 4 Murata
GRM033R6
0J333KE01
D
Cap, Ceramic, 0.033uF,
X5R, 6.3V, 10% SMT, 0201
C131-
C132,C149-
C150
490-3170-1-
ND
35 4 Murata
GRM033R7
1C102KD01
D
Cap, Ceramic, 0.001uF,
X7R,,16V, 10% SMT, 0201
C133-
C134,C151-
C152
490-1261-1-
ND
36 98 Kemet C0402C104
K4RACTU
Cap, Ceramic, 0.1uF,
X7R, 16V, 10% SMT, 0402
C3-C34,C37-
C68,C71-
C102, C124-
C125
37 8 Panasonic ECJ-
ZEB1A104M
Cap, Ceramic, 0.1uF,
X5R, 10V, 20% SMT, 0201 C135-C138,
C153-C156
PCC2424CT-
ND
38 2 AVX 0603YC104
KAT2A
Cap, Ceramic, 0.1uF,
X7R, 16V, 10% SMT, 0603 C108,C123,
39 6 AVX 0603YD105
KAT2A
Cap, Ceramic, 1uF, X5R,
16V, 10% SMT, 0603
C110,C112,C1
14,C116,
C119-C120
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
16 Copyright © 2008 by PLX Technology, Inc. All rights reserved