PLX Technology PEX 8615A Quick user guide

PEX 8615BA Base Board RDK
Hardware Reference Manual
Version 1.0
April 2009
Website: www.plxtech.com
Technical Support: www.plxtech.com/support
Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.0
April 15, 2009

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 2
© 2009 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor
variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX8615BA-Base Board RDK-HRM-1.0
April 15, 2009

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved i
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may not be
copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely
verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured
products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this
information. The information in this document is subject to change without notice. Although every effort has been
made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential
damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes
no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which
may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of
malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8615BA-Base Board RDK, a Rapid Development Kit, from a hardware
perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for
the creation of software for this product. This manual also includes complete schematics and bill of materials.
REVISION HISTORY
Date Version Comments
April 2009 1.0 Initial Release

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved ii
CONTENTS
NOTICE .........................................................................................................................................................................i
ABOUT THIS MANUAL .....................................................................................................................................................i
REVISION HISTORY....................................................................................................................................................i
1.General Information...........................................................................................................................................1
1.1PEX 8615 Features ................................................................................................................................... 1
1.2PEX 8615BA-BB RDK Features................................................................................................................ 3
2.System Architecture...........................................................................................................................................4
3.Hardware Architecture.......................................................................................................................................4
3.1PEX 8615................................................................................................................................................... 5
3.2PCI Express Interfaces.............................................................................................................................. 5
3.2.1RDK Configuration Modules and Their Receptacles......................................................................... 5
3.2.2PCI Express Lane 0 to Lane 3........................................................................................................... 5
3.2.3PCI Express Lane 4 to Lane 7........................................................................................................... 6
3.2.4PCI Express Lane 8 to Lane 11......................................................................................................... 7
3.3Reference Clock Circuits........................................................................................................................... 8
3.4Reset Circuits ............................................................................................................................................ 8
3.5Serial Hot-Plug (SHP) Controller Circuits.................................................................................................. 9
3.6Serial EEPROM....................................................................................................................................... 10
3.7I2C Interface............................................................................................................................................. 10
3.8Power Distribution Circuits....................................................................................................................... 11
3.9FPGA Interface........................................................................................................................................ 12
3.10LED and 7-Segment Displays ................................................................................................................. 13
3.10.1LED Indicators................................................................................................................................. 13
3.10.27-Segment Displays......................................................................................................................... 14
3.11GPIO Pins................................................................................................................................................ 15
3.12Reserved Pins ......................................................................................................................................... 15
4.On-Board Connectors, Switches, and Jumpers...............................................................................................16
4.1DIP Switches ........................................................................................................................................... 16
4.1.1Dip Switch Group 1.......................................................................................................................... 16
4.1.2Dip Switch Group 2.......................................................................................................................... 17
4.1.3Dip Switch Group 3.......................................................................................................................... 19
4.2Push-Button Switches.............................................................................................................................. 20
4.2.1Manual Reset# (S1)......................................................................................................................... 20
4.2.2FPGA Manual Reset# (S2).............................................................................................................. 20
4.2.3Serial Hot-Plug Controller Attention Button (S3)............................................................................. 21
4.3Connectors and Headers......................................................................................................................... 21
4.3.1ATX Peripheral Power Connectors (J1-J4 & J7-J8)........................................................................ 21
4.3.2x4 PCI Express External Cable Connectors (J5 & J6).................................................................... 21
4.3.3ATX Main Power Connector (J9)..................................................................................................... 22
4.3.4ATX +12V Power Connector(J10)................................................................................................... 22
4.3.5Xilinx JTAG Connector (J12)........................................................................................................... 22
4.3.6Xilinx Mode Setting Header (J13).................................................................................................... 23
4.3.7PEX 8615 JTAG Header (JP3)........................................................................................................ 23
4.3.8SMBus Header (JP5)....................................................................................................................... 23
4.3.9PCI Express x8 Midbus Probe Footprint (JP6)................................................................................ 23
4.3.10PEX 8615 I2C Port (JP8) ................................................................................................................. 24
4.3.11Debug Signal Header (JP9 & JP11)................................................................................................ 24
4.3.12Debug Input Header (JP10)............................................................................................................. 26
4.3.13Reference Clock Header (JP100).................................................................................................... 26
5.RDK Port Configurations..................................................................................................................................27
6.Bill of Materials/ Schematics............................................................................................................................30

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved iii
FIGURES
Figure 1. PEX 8615BA Base Board RDK Front View................................................................................................ 2
Figure 2. Connecting The RDK to a PC with x1 or x4 link......................................................................................... 4
Figure 3. Lanes 0-3 Hardware Connections on the RDK.......................................................................................... 6
Figure 4. Lanes 4-7 Hardware Connections on the RDK.......................................................................................... 7
Figure 5. Lanes 8-11 Hardware Connections on the RDK........................................................................................ 7
Figure 6. RDK Reference Clock Circuits................................................................................................................... 8
Figure 7. RDK Reset Circuits .................................................................................................................................... 9
Figure 8. SERIAL HOT-PLUG Circuits.................................................................................................................... 10
Figure 9. RDK ATX Power Connectors................................................................................................................... 11
Figure 10. RDK Power Distribution Circuits ............................................................................................................ 12
Figure 11. FPGA Interface on RDK......................................................................................................................... 13
Figure 12. RDK Dip Switch Groups......................................................................................................................... 16
Figure 13. Group1 of Switches................................................................................................................................ 16
Figure 14. Group 2 of Dipswitches.......................................................................................................................... 17
Figure 15. Group 3 of Dip Switches......................................................................................................................... 19
Figure 16. x1 upstream and 11x1 downstream (PCFG=0000) ............................................................................... 27
Figure 17. x4 upstream 8x1 downstream (PCFG=0001) ........................................................................................ 28
Figure 18. x4 upstream, 1x4 and 4x1 downstream (PCFG=0010).......................................................................... 29
TABLES
Table 1. Port Configurations Supported by the RDK................................................................................................. 5
Table 2. RDK LED Indicator descriptions................................................................................................................ 13
Table 3. RDK 7-Segment Display Functions........................................................................................................... 14
Table 4. Strap_Reserved Pin Connections............................................................................................................. 15
Table 5. Functional Description of Group 1 Dip Switches....................................................................................... 17
Table 6. Functional Description of Group 2 Dip Switches....................................................................................... 18
Table 7. Port Configurations use Dipswitch SW2.................................................................................................... 19
Table 8. Functional Descriptions of SW3, SW6, SW13-SW14 ............................................................................... 20
Table 9. Signal Names of J1-J4 & J7-J8................................................................................................................. 21
Table 10. Signal Names of J5 and J6...................................................................................................................... 21
Table 11. Signal Names of J9 ................................................................................................................................. 22
Table 12. Signal Names of J10 ............................................................................................................................... 22
Table 13. Signal Names of J12 ............................................................................................................................... 22
Table 14. Signal Names of J13 ............................................................................................................................... 23
Table 15. Pin assignment of JP3............................................................................................................................. 23
Table 16. Signal Names of JP5............................................................................................................................... 23
Table 17. Signal Names of JP6............................................................................................................................... 23
Table 18. Pin assignment of JP8............................................................................................................................. 24
Table 19. Pin assignment of JP9 & JP11................................................................................................................ 24
Table 20. Pin assignment of JP10........................................................................................................................... 26
Table 21. Pin assignment of JP100......................................................................................................................... 26

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 1
1. General Information
The PLX PEX 8615BA Base Board RDK is a Rapid Development Kit based on the PEX 8615, a 12-lane, 12-port
PCI Express switch based in the PCI Express Specification rev 2.0 with SerDes capable of running at 5 GT/s. The
PEX 8615BA Base Board RDK provides a complete hardware and software development platform that facilitates
getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK consists a base
board containing three hardware configuration Modules, a PCI Express cable adapter board that plugs into the
host system, and up to two x4 PCI Express cables that used to connect the RDK to the cable adapter. This
manual primarily focuses on the PEX 8615BA Base Board RDK, and its use with other parts to demonstrate the
various functions of PEX 8615 chip. Figure 1 provides a top view (component side) of the PEX 8615BA Base
Board RDK.
1.1 PEX 8615 Features
•12-lane, 12-port PCI Express Gen 2 switch with integrated on-chip SerDes
•120 GT/s aggregate bandwidth (5.0GT/s/Lane x 16 Lanes x 2 (full duplex))
•19mm2324-ball Plastic Ball Grid Array (PBGA) package
•Typical Power – 1.7W
•Cut-Thru packet latency of less than 160ns
•Low power SerDes (under 90mW per lane)
•Fully non-blocking switch architecture
•Flexible port configuration
o12 flexible and configurable ports (x1, or x4 ), x2 is also supported
•Flexible device configuration
oConfigurable via serial EEPROM, I2C, hardware strapping, or by the host
•Maximum packet payload size of 2,048 bytes
•Designate any Port as the Upstream Port (Port 0 is recommended)
•Dynamic Buffer Pool Architecture
•Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient
performance)
•Dual-Cast (enhances performance by sending date from one ingress port to two egress ports)
•Integrated Direct Memory Access (DMA) engine
•Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation
•Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic
density)
•Lane and polarity reversal
•Non-Transparent Bridging support
oEnables Dual-Host, Host-Failover applications
•Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with
Vaux not supported)
•Conventional PCI-compatible Device Power Management states – D0 and D3hot
•Active State Power Management
•Spread-Spectrum Clock Isolation
oDual-clock Domain
•Quality of Service (QoS)
oTwo Virtual Channels (VC0 and VC1) and Eight Traffic classes (TC)
oWeighted Round-Robin Port and Virtual Channel arbitration
•Reliability, Availability, Serviceability (RAS) features
oAll ports are Hot-Plug capable through I2C (Serial Hot-Plug Controller on every port)
oAdvanced Error Reporting capability
oPerformance Monitoring
Per-Port Payload and Header Counters
Per-traffic type (write, Read, Completion) Counters
oJTAG AC/DC boundary scan
o12 Lane status balls (PEX_LANE_GOOD[11:0]#)

o32 GPIO balls (GPIO[31:0]
1.0VCC
2.5VCC
J9
SLOT15
SLOT14
SLOT13
SLOT12
SLOT11
SLOT10
SLOT9
SLOT8
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
J1 J7 J3 J8 J4 J2
1
24
J5
4x PCIE
cable
connector
J6
4x PCIE
cable
connector
U100
PEX
8615
Xilinx
FPGA
U115
Configuration
Module
0108
Configuration
Module
0108
SW15 SW11 S2 SW10
ON ONON
JP9 JP10
S2
J13 JP5
1 23
4
1
J12
1
SW7
ON
SW5
ON
SW4
ON
SW2
ON
SW14
ON
SW13
ON
SW3
ON
SW6
ON
JP8
1 23
4
JP10
11
JP3
D1 12V_A D2 5V_A
D29 12V_SLT_8_HP D30 3.3VCC_SLT_8_HP
D32 Interlock_S
D31 ATNLED#_S
D28 PWRLED#_S D3 3.3VCC
D9 3.3VCC1
JP6
Midbus Probe
Footprint
Mictor
Connectors
Debug Input
Header
I2C Port
JTAG Port
2.5VCC
GND
BJ9
BJ10
GND
BJ6
1.0VCC_A
BJ5
BJ4
BJ3
GND
1.0VCC
Port #
Link Width
Port #
Link Width
Port #
Link Width
Port #
Link Width
S1
FPGA JTAG
Port
Manual Reset
FPGA Reset
I2C Port for
Thermal Sensor
FPGA Mode
User debug
J10
D10
D8
2.5VCC_A
D4
1.0VCC_A
D6
D7
D5
PEX8615-BB RDK
Configuration
Module
0108
D12
D16D20D24D13D17D21D25D14D18D22D26
D15D27 D23 D19
JP100
1.0VCC
2.5VCC
Figure 1. PEX 8615BA Base Board RDK Front View
PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 2

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 3
•INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball
support
•Compliant to the following specifications:
oPCI Local Bus Specification, Revision 3.0 (PCI r3.0)
oPCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
oPCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2)
oPCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1)
oPCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
oIEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,
1990 (IEEE Standard 1149.1-1990)
oIEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture
oIEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions
oIEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture
Extensions (IEEE Standard 1149.6-2003)
oThe I2C-Bus Specification, Version 2.1 (I2C Bus v2.1)
1.2 PEX 8615BA-BB RDK Features
•PLX PEX 8615 PCI Express switch in a 324-ball Plastic BGA package
•Based on PCI Express Card Electromechanical (CEM) Specification 2.0 and PCI Express External
Cabling Specification 1.0
•Supports up to 3 different port configurations with 4x PCI Express cable connection(s) to the upstream
PC
•Non-Transparent Bridging support
•One x8 Gen 2 Midbus probe footprint for upper 4 lanes of PCI Express signal probing for the chip
•PCI Express RefClk Circuits supports Spread-Spectrum Clock Isolation
•Serial Hot-Plug circuits on one PCI Express card edge connector
•In system programmable Serial EEPROM (2.5V)
•A standard 2x2 header provides the I2C interface to an I2C master
•DIP switches for port configuration, upstream port or NT port select and I2C address settings
•Manual push-button PERST# capability
•Up to sixteen dual color LEDs for visual inspection of link speed and status
•7-Segment displays for port numbers and link width
•Up to 3-digit display for junction temperature of PEX 8615
•Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8615

2. System Architecture
PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 4
The PEX 8615BA-Base Board RDK is a 21” x 10” bench top board for silicon evaluation and design reference for
the PEX 8615 PCI Express Gen 2 switch. This RDK consists of three main hardware components: the base
board, the PCI Express External Cable Adapter and PCI Express Cable assembly. Figure 1 represents the
placement of major component blocks on the RDK base board. Figure 2 and Figure 3 provide diagrams of the
RDK being used in a PC. The RDK provides up to 11 PCI Express slots for add-in cards and visual indicators for
port, link status and speed information. The RDK is designed to be powered up with an ATX power supply.
Figure 2. Connecting The RDK to a PC with x1 or x4 link
signed around the PEX 8615, a 12-port, 12-lane Gen 2 switch, and
m
3. Hardware Architecture
The PEX 8615BA Base Board RDK is de
based on the PCI Express CEM 2.0 Specification. The RDK offers PCI Express interfaces to 11 PCI Express
Edge Card Connectors, two x4 PCI Express External cable connectors, and three configuration modules. The
RDK is designed to support 3 different port configurations (see Table 1 for details) and to connect to its upstrea
PC through its PCI Express Cable Connectors. The RDK relies on the PC connected to its PCI Express Cable
Connector J5 to obtain it primary PCI Express reference clock and reset to support the RDK normal functions.
Also, the RDK provides visual indications for power, link speed, port status, port number, and link width.

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 5
3.1 PEX 8615
The PEX 8615 is a 12-lane, 12-port PCI Express Gen 2 (5.0GT/s) switch. It is in 19mmx19mm package. It
supports 4 different types of port configurations with any port can be upstream or NT port. It supports Spread-
Spectrum Clocking Isolation function. It also provides 12 lane status drivers and 32 GPIOs.
3.2 PCI Express Interfaces
The RDK provides 11 PCI Express connectors and one x4 PCI Express External Cable Connectors for PCI
Express connections of PEX 8615. The RDK supports 3 different port configurations of PEX 8615. With the
correct port configuration STRAP pin settings and the right Configuration Modules are installed, the RDK can
demonstrate up to 12 ports and a up to x4 link upstream connection PCI Express Gen 2 switch. Table 1 shows all
port configurations supported by the RDK while sections 3.2.1 to 3.2.5 describe the Configuration Modules and
hardware configurations of grouped of each four PCI Express lanes in details.
Table 1. Port Configurations Supported by the RDK
Strap pin Settings
STRAP_PORTCFG[3:0] Port Configurations Configuration Modules Used*
0000 x1x1x1x1x1x1x1x1x1x1x1x1 0108 at U74;0108 at U75; and 0108 at U76
0001 x4x1x1x1x1x1x1x1x1 0107 at U74;0108 at U75; and 0108 at U76
0010 x4x4x1x1x1x1 0107 at U74;0108 at U75; and 0107 at U76
Note: * Three Configuration Modules may use for the RDK. They are “configuration Module 0107-0109”; U74, U75
and U76 are receptacles on the RDK for Configuration Modules to be installed
3.2.1 RDK Configuration Modules and Their Receptacles
Each Configuration Module is a plug of a 200-pin board-to-board Mezzanine Connector assembled on a PCB. For
the RDK, it is used to connect x4 link of PCI Express signals from PEX 8615 to one particular hardware
connections. Only three Configuration Modules may be used on the PEX 8615BA base board RDK. These
modules are labeled on their PCB silk screen as:
•Configuration Module 0107
•Configuration Module 0108
•Configuration Module 0109
On the RDK side, three receptacles of same Mezzanine Connectors are placed at U74, U75 and U76 where the
Configuration Modules can be manually plugged in to complete the RDK PCI Express hardware configurations.
3.2.2 PCI Express Lane 0 to Lane 3
PCI Express lanes 0 - 3 of PEX 8615 are routed to the receptacle U74 as shown in Figure 4. When Configuration
Module 0108 is plugged into U74 at Case (a), lanes 0-3 will be separately connected with a single line going to
the following: PCI Express cable connector J5, PCI Express SLOT 1, PCI Express SLOT 2 and PCI Express
SLOT 3. This results in x1 links to form port 0, 4, 6, and 8. When Configuration Module 0107 is plugged into U74
at Case (b), all four lanes will be connected to x4 PCI Express cable connector J5 to form a x4 link at port 0. Note
that the PCIe signals to PCIe Cable Connector J5 can be an independent x4 port or the lower lanes of a x8 port.

x16 PCI Express Connectors
x1link to upstream
SLT3
Port 0
SL2 SLT1
4x PCIe
Cable
Connector
J5
Configuration Module
PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 6
0108
Lane 0 Lane 1
Lane 2
Lane 3
x16 PCI Express Connectors
x4 link to
upstream
SLT3
Port 8 Port 6 Port 4
Port 0
Lane 0-3
SL2 SLT1
Configuration Module
0107
4x PCIe
Cable
Connector
J5
Lane 0-3
U74U74
Lane 0-3
PEX 8615
(U100)
Lane 3-0
Lane 8-11
Lane 4-7
A1 A1
Lane 3-0
PEX 8615
(U100)
Lane 8-11
Lane 4-7
(a) (b)
Figure 3. Lanes 0-3 Hardware Connections on the RDK
3.2.3 PCI Express Lane 4 to Lane 7
PCI Express lanes 4-7 of PEX 8615 are routed to the receptacle U75 as shown in Figure 5. When Configuration
Module 0108 is plugged into U75 at Case (a), lanes 4-7 will be separately connected to PCI Express SLOT 4 to
SLOT 7 with x1 link each to form ports 2, 10, 12, and 14. When Configuration Module 0107 is plugged into U75 at
Case (b), four lanes will be connected to SLOT 4 to form a x4 link (port 4).

Figure 4. Lanes 4-7 Hardware Connections on the RDK
3.2.4 PCI Express Lane 8 to Lane 11
PCI Express lanes 8-11 of PEX 8615 are routed to the receptacle U76 as shown in Figure 6. When Configuration
Module 0108 is plugged into U76 at Case (a), lanes 8-11 will be separately connected to PCI Express SLOT 8 to
SLOT 11 with x1 link each to form ports 1, 5, 7, and 9. When Configuration Module 0107 is plugged into U76 at
Case (b), four lanes will be connected to SLOT 8 to form a x4 link (port 1).
PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 7
Figure 5. Lanes 8-11 Hardware Connections on the RDK

3.3 Reference Clock Circuits
The RDK reference clock circuits contain one crystal-to HCSL clock generator ( U108) from On Semiconductor
(NB3N5573), two one-to-four differential clock fan out buffer (U28 and U61) from SpectraLinear (CY28400-2), two
1-to-10 differential clock drivers (U113-U114) from On Semiconductor (MC100LVEP111), AC coupling capacitors,
and resistors for source terminations and voltage dividers. The clock circuits are designed to perform two major
clock functions: reference clock fan out and Spread-Spectrum Clock Isolation. Refer to Figure 8, the PCI Express
clock (CREFCLKp and CREFCLKn) from x4 PCI Express External Cable Connector J5 feeds into 1-to-4 fan out
buffer U28. The outputs from U28 support the primary REFCLK of the PEX 8615 and connect to the inputs of
clock drivers U113 and U114. The Constant frequency output from the clock generator (U108) is connected to a
1-to-4 fan out buffer U61. The outputs from U61 support the input to CFC_REFCK on the PEX 8615 as well as
inputs to U113 and U114. When Spread Spectrum Clocking Crossing is enabled, the PEX 8615 can be made part
of two clock domains. Port 0 is part of the SSC domain while all on-board PCI Express SLOT 1 to SLOT 11 are
part of the constant frequency domain. Add-in cards connected to SLOT1 – SLOT11 will operate in a constant
frequency clock. The SSC isolation feature can be enabled with a pull-down resistor on
STRAP_SSC_ISO_ENABLE# pin. On the RDK, this can be done in Dipswitch SW6 position 1 set to ‘ON’. This
feature is disabled on the RDK by default.
Figure 6. RDK Reference Clock Circuits
3.4 Reset Circuits
Refer to Figure 9, the RDK reset circuits include two National NC7S08 2-input AND gate (U17&U21), two Maxim
MAX6420 reset controllers (U18 and U20), one Xilinx FPGA (U115), a Serial Hot-Plug controller, momentary
switches (S1 and S3), resistors and capacitors.
PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved 8

Slot 1
Slot 2
PEX8615
PS_PWR_GOOD
from ATX 24-P
Mainboard Power
Connector J9
R
3.3V
R
3.3V
S3
PCI Express Connectors
NC7S08 MAX6420
(U20)
R
3.3V
(U100)
NC7S08
(U21)
C153
U115
Xilinx
FPGA
FPGA_RESET
CPERST_n from 4x
PCIe Cable
Connector J5
R
3.3V
R
3.3V
S1
NC7S08 MAX6420
(U18)
R
3.3V
NC7S08
(U17)
C88
PERST_n_SL1
Slot 3
Slot 4
PERST_n_SL2
PERST_n_SL3
PERST_n_SL4
Slot 5
Slot 6
PERST_n_SL5
Slot 7
Slot 9
PERST_n_SL6
PERST_n_SL7
PERST_n_SL9
Slot 10
Slot 11
PERST_n_SL10
PERST_n_SL11
PEX_PERST_n
7_Segmen
Displays
Lane Status
LEDs
SHP
Controller
Slot 8
PERST_n_SL8
FPGA_PEX_RE
SET_n
Figure 7. RDK Reset Circuits
The Reset Circuits contains two independent circuits: (a) the circuits reset the FPGA; (b) the circuits reset PEX
8615 and sends resets to 11 PCI Express connectors. The first one detect the power good signal,
PS_PWR_GOOD, from the ATX 24-pin Main Power Connector and reset from momentary switch S3 to generate
reset, FPGA_RESET, to the FPGA U115. The second detect the reset input, CPERST_n from the PCI Express
Cable Connector J5 and the reset from momentary switch S1 input them to the FPGA that fans out the resets,
PERST_n_SL[15:9, 7:1] , to 10 PCI Express slots, PEX_PERST_n to reset the PEX 8615, and PERST_n_SL8 to
reset the PIC Express SLOT 8 through the Serial Hot-Plug Controller (see Figure 9 an Figure 10 for details)
3.5 Serial Hot-Plug (SHP) Controller Circuits
With external IO expenders and Hot-Plug controllers, PEX 8615 supports up to 12 PCI Express Serial Hot-Plug
ports/ SLOTs. The RDK implements a serial Hot-Plug controller circuitry to PCI Express SLOT 8 for the SHP
function demonstration. By default, the serial Hot-Plug circuit is enabled.
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Figure 8. SERIAL HOT-PLUG Circuits
Refer to Figure 10 above, the serial Hot-Plug controller consists of MAX7311 I/O expander (U71), a TI TPS2311
dual hot–swap power controller (U70), a quad TI SN74LVC157 2-to-1 multiplexer (U72), two power MOSFET
IRF7470 (Q1 and Q2), LEDs, manual switch, dipswitches and resistors. The PEX 8615 master I2C interface is
designed for the specific control use of the serial Hot-Plug controller. The master I2C interface connected to the
I/O expander and the interrupt output from the I/O expander connects to the SHP_INT# of the PEX 8615. When
power is applied to the PEX 8615, the master I2C interface will scan the bus and attempts to detect the presence
of the I/O expander. If an I/O expander is detected, the I2C master will program it as a “remote parallel Hot-Plug
controller” and assign an available serial Hot-Plug port to the I/O expander. The IO expender then generates
PWREN, CLKEN#, and PERST# outputs to control the power enable, clock enable# and reset# of the SHP
SLOT8 and drives the LEDs at PWRLED#, ATNLED# and INTERLOCK# outputs. Also, it accepts BUTTON#,
PWRFLT#, PWRGOOD, PRSNT# and MRL# inputs and generates interrupts to PEX 8615 for SHP status
changes.
The RDK also provides dip switch (SW10) for setting the SLOTID [3:0]for the SLOT 8, and another dipswitch
(SW11) to control the Serial Hot-Plug controller functions (enable/disable it), a test point for access the GPIO pin,
and three pull-down resistors to set ADD [2:0] of the I/O expander U71. The LEDs D29 and D32 are 12V and 3.3V
power indicators when power reaches PCI Express connector SLOT 82.
3.6 Serial EEPROM
The PEX 8615BA Base Board RDK contains a blank surface mount Atmel AT25256A 32-Kbit serial EEPROM
(U19) which is directly interfaced to the PEX 8615. When programmed correctly, the serial EEPROM can be used
to change the default configuration and internal register values of the PEX 8615. A blank EEPROM results in the
default register values set in the PEX 8615. Refer to the Software Development Kit (SDK) documentation for more
information of how to program the serial EEPROM.
3.7 I2C Interface
The PEX 8615 implements an I2C slave interface (I2C port 0), which allows an external I2C master to read and
write device registers through an out-of-band mechanism. The PEX 8615 I2C interface is accessible via a 7-bit
address, at data rates from 100 Kbps up to 3.4 Mbps. The RDK provides a 2x2, 0.1” pitch header (JP8), which
interface to the PEX 8615’s I2C port. This allows using standard ribbon cable, and/or connecting to an I2C master
such as Total Phase Aardvark I2C controller. (See 4.3.10 for pin assignment of JP8.)
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3.8 Power Distribution Circuits
To support the power of the RDK and the power of the PCI Express add-in cards plug into up to 15 PCI Express
Edge Card connectors, an external ATX power supply is required. Refer to Figure 11, the RDK has 8 different
ATX power connectors for power connections. These include one 24-pin ATX Main Power Connector J9, six 4-pin
Peripheral Power Connectors J1- J4 & J7 - J8, and one 8-pin +12 V Power Connector.
J9
SLOT11
J1
J7
J3
J8
J4
J2
1
24 D1 12V_A
D2 5V_A
D29 12V_SLT_8_HP
D30 3.3VCC_SLT_8_HP
D32 Interlock_S
D31 ATNLED#_S
D28 PWRLED#_S
D3 3.3VCC
D9 3.3VCC1
J10
Figure 9. RDK ATX Power Connectors
The 24-pin ATX Power Connector should be connected to J9 and two or three 4-pin ATX Peripheral Power
Connectors should be connected to either J1-J4 or J7-J8 depending on the power consumption requirements of
the PCI Express add-in cards plugging into the PCI Express slots of the RDK.
Note Some 600 watt power supplies in the market such as the NSpire model PSH600V-D 600 Watt power supply
requires a minimum power consumption at +12V output to stabilize its +5V outputs. Without 0.8A loading at +12V
outputs, the NSpire 600 watt power supply will drop its +5V output to near 3.9V-4.2V levels. The RDK only uses
+5V output from the ATX power supply to generated lower DC voltages to support the PEX 8615 chip and the on
board FPGA and other circuits. This particular power supply does not operate correctly unless there is enough
loading on the +12V supply. An Nvidia Geforce 8800GT high power graphic card can be plugged into one of PCI
Express slots on the RDK in order to provide enough loading on the +12V supply.
PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
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Figure 10. RDK Power Distribution Circuits
Refer to Figure 12, 11 PCI Express slots including the Serial Hot-Plug controlled SLOT 8 get 3.3 volt and 12 volt
power from 24-pin ATX Main Power Connector, 4-pin ATX Peripheral Power Connectors and the +12V Power
Connector. The RDK on board circuits and the PEX 8615 get their power from the +5V input from the ATX power
supply. DC/DC converter U4 uses 5V input generates 3.3VCC1 to the on board circuit. The 3.3VCC1 further steps
down by voltage regulator U117 to generate 2.5V and 1.2V for Xilinx FPGA (U115). Three DC/DC converters U2,
U3 and U5 use 5V input to generate 1.0VCC, 1.0VCC_A and 2.5VCC for PEX 8615. Dip switch SW15 can be set
to turn off these dc/dc converters for external power margin tests for PLX use only.
3.9 FPGA Interface
The RDK contains a Xilinx Spartan-3 FPGA which is used to perform 6 major functions (see Figure 13 for details):
•Connects to GPIOs, lane and chip status and spare pins of PEX 8615 ( for PLX use only)
•Controls the 7-segment displays for port numbers and link width for PCI Express Cable Connectors J5
and J6 and PCI Express connectors SLOT 1 to SLOT11
•Decodes lane status and converts them to link speed and status LED display
•Communicates with the thermal sensor and displays the junction temperature of PEX 8615 in 4 digits
•Connects to users defined Dipswitches
•Fans out reset signals to PEX 8615 and PCI Express slots
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Figure 11. FPGA Interface on RDK
3.10 LED and 7-Segment Displays
The RDK provides 31 LEDs and forty 7-segment displays for power indicators, Hot-Plug output indicators, link
speed/status, port numbers and link width of each port.
3.10.1 LED Indicators
All LED indicators and their associated functions are described in the Table 2 below.
Table 2. RDK LED Indicator descriptions
Indicator Type Locations LED Functions
Power LEDs/green color
D1 On: 12V_A is applied to the RDK from the ATX power supply
D2 On: 5V_A is applied to the RDK from the ATX power supply
D3 On: 3.3VCC is applied to the RDK from the ATX power supply
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PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
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Indicator Type Locations LED Functions
D9 On: 3.3VCC1 from dc/dc converter U4
D4 On: 2.5VCC_A is applied to PEX 8615
D5 On: 2.5VCC is applied to PEX 8615
Power LEDs/dual color: green
and red
D8 Green LED on: 2.5VCC to PEX 8615 is within 10% range
Red LED on: 2.5VCC to PEX 8615 is out of 10% range
D10 Green LED on: 1.0VCC to PEX 8615 is within 10% range
Red LED on: 1.0VCC to PEX 8615 is out of 10% range
SERIAL HOT-PLUG (SHP)
LEDs/green color
D28 On: SHP power LED output active at SLOT 8
D29 On: 12V is applied to PCI Express SLOT 8
D30 On: 3.3V is applied to PCI Express SLOT 8
D31 On: SHP Attention LED output active at SLOT 8
D32 On: SHP Interlock LED output active at SLOT 8
Port Link Status and Speed
LEDs / Dual color: green and
yellow
D12 Green LED on: port 0 link up with GEN 2 speed (5Gbps) at connector J5 Yellow LED on: port 0 link up with GEN 1 speed (2.5Gbps) at connector J5
Both LED off: port 0 link down or no connected or no configured
D16 Same function as D12 for port 4 at SLOT1
D20 Same function as D12 for port 6 at SLOT2
D24 Same function as D12 for port 8 at SLOT3
D13 Same function as D12 for port 2 at SLOT4
D17 Same function as D12 for port 10 at SLOT5
D21 Same function as D12 for port 12 at SLOT6
D25 Same function as D12 for port 14 at SLOT7
D14 Same function as D12 for port 1 at SLOT8
D18 Same function as D12 for port 5 at SLOT9
D22 Same function as D12 for port 7 at SLOT10
D26 Same function as D12 for port 9 at SLOT11
3.10.2 7-Segment Displays
The RDK has forty 7-segment displays. Thrity-four of them are used for port number and link width indicators of
each PCI Express SLOTs, two are user defined 7-segment displays, and four of them are used for junction
temperature display. (See Table 3 for details).
Table 3. RDK 7-Segment Display Functions
Location of Display 7-Segment Display Functions
DS37 For port 0 at cable connector J5, When enabled, LED display is 0
DS39 Link Width of port0, LED display is 1 or 4 depending on the port configuration
DS33 Copy DS37 if cable connector J6 is used. Otherwise it would be off
DS35 Copy DS39 if cable connector J6 is used. Otherwise it would be off
DS2 For port 4 at SLOT1, When enabled, LED display is 4
DS6 Link Width of port 4, When enabled, LED display is 1
DS9 For port 6 at SLOT2, When enabled, LED display is 6
DS13 Link Width of port 6, When enabled, LED display is 1
DS1 For port 8 at SLOT3, When enabled, LED display is 8
DS5 Link Width of port 8, When enabled, LED display is 1
DS12 For port 2 at SLOT4, When enabled, LED display is 2

PEX 8615BA Base Board RDK Hardware Reference Manual – Version 1.0
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Location of Display 7-Segment Display Functions
DS16 Link Width of port 2, it can be 1 or 4 depends the port configuration
DS4 For port 10 at SLOT5, When it is on, it would be A
DS8 Link Width of port 10, When it is on, it would be 1
DS11 For port 12 at SLOT6, When it is on, it would be C
DS15 Link Width of port 12, When it is on, it would be 1
DS3 For port 14 at SLOT7, When it is on, it would be E
DS7 Link Width of port 14, When it is on, it would be 1
DS26 For port 1 at SLOT8, When it is on, it would be 1
DS30 Link Width of port 1, it can be 1 or 4 depends the port configuration
DS18 For port 5 at SLOT9, When it is on, it would be 5
DS22 Link Width of port 5, When it is on, it would be 1
DS25 For port 7 at SLOT10, When it is on, it would be 7
DS29 Link Width of port 7, When it is on, it would be 1
DS17 For port 9 at SLOT11, When it is on, it would be 9
DS21 Link Width of port 9, When it is on, it would be 1
DS10 and DS14 Users’ defined 7-segment displays
DS34, DS36, DS38,
DS40 They are used to display junction temperature of PEX 8615 in degree C
3.11 GPIO Pins
The PEX 8615 has thirty-two GPIO pins. Depends on the TEST MODE pin settings, 16 of them, GPIO[15:0], can
be configured to perform Serial Hot-Plug reset output functions (PERSTx#).
3.12 Reserved Pins
The PEX 8615 has 2 STRAP_RESERVED pins. They are factory use only and should be set to know logic states.
Table 4 shows the list of these reserved pins and their connections in the RDK.
Table 4. Strap_Reserved Pin Connections
Name Pin Location Connections on PEX 8615BA Base Board RDK
STRAP_RESERVED16 D14 Pull-down with a 1K ohm resistor
STRAP_RESERVED17# F1 Pull-up with a 4.7K ohm resistor