PLX Technology PEX 8311RDK Quick user guide

PEX 8311RDK
Hardware Reference Manual

PEX 8311RDK
Hardware Reference Manual
Version 0.90
December 2005
Website: http://www.plxtech.com
Support: http://www.plxtech.com/support
Phone: [phone]
800 759-3735
Fax: [phone]

© 2005 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX8311-RDK-HRM-P1-0.90
Printed in the USA, December 2005

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. v
CONTENTS
1. General Information ............................................................................................................................... 1
1.1 PEX 8311 Features ......................................................................................................................... 2
1.2 PEX 8311RDK Features.................................................................................................................. 2
2. PEX 8311RDK System Architecture ...................................................................................................... 3
3. PEX 8311RDK Hardware Architecture .................................................................................................. 4
3.1 PEX 8311 PCI Express Bridge Device............................................................................................ 4
3.2 Serial EEPROM............................................................................................................................... 4
3.2.1 SPI EEPROM............................................................................................................................ 5
3.2.2 Microwire Serial EEPROM........................................................................................................ 5
3.2.2.1 Microwire Serial EEPROM Contents ............................................................................... 6
3.3 Local and PCI Express Hardware Elements ................................................................................... 7
3.3.1 Local Clock................................................................................................................................ 8
3.3.2 Synchronous Burst SRAM ........................................................................................................ 8
3.3.3 Xilinx CPLD ............................................................................................................................... 8
3.3.4 Internal Clock ............................................................................................................................ 8
3.3.5 PLX Option Module Connector ................................................................................................. 9
3.3.6 Hardware Memory Map .......................................................................................................... 10
3.4 PCI Express Interface.................................................................................................................... 10
3.4.1 RefClk ..................................................................................................................................... 10
3.4.2 PERST# .................................................................................................................................. 10
3.4.2.1 Reset Circuitry ............................................................................................................... 11
3.5 LED Indicators ............................................................................................................................... 11
3.6 PEX 8311RDK Power.................................................................................................................... 11
3.6.1 PEX 8311 Bridge Device Power ............................................................................................. 11
3.6.2 PEX 8311 Power Jumpers and Resistor options.................................................................... 12
3.7 Power Management Signaling....................................................................................................... 13
3.7.1 Wakeup ................................................................................................................................... 13
3.8 Endpoint/Root Complex operation ................................................................................................ 13
4. Mechanical Architecture....................................................................................................................... 15
4.1 Monitoring Points, Test headers, Indicators, Control, and DIP Switch Summary ......................... 16
4.1.1 Monitoring Points .................................................................................................................... 16
4.1.2 Headers................................................................................................................................... 16
4.1.2.1 Test Headers ................................................................................................................. 16
4.1.2.2 JTAG Headers ............................................................................................................... 16
4.1.3 Indicators................................................................................................................................. 17
4.1.4 Controls................................................................................................................................... 17
4.2 PEX 8311RDK Layout Information................................................................................................ 17
4.2.1 Trace Routing Design Rules ................................................................................................... 17
4.2.2 Power Decoupling ................................................................................................................... 17
4.2.3 PCB Stackup........................................................................................................................... 18
4.3 MidBus LAI Footprints ................................................................................................................... 19
4.4 Prototyping Area............................................................................................................................ 19
4.4.1 Surface Mount Footprints........................................................................................................19
4.4.2 Uncommitted FPGA footprint .................................................................................................. 20
4.4.2.1 Uncommitted FPGA connections .................................................................................. 20
4.4.2.2 Uncommitted FPGA to PEX 8311 local bus .................................................................. 20
4.4.2.3 Programming the uncommitted FPGA........................................................................... 24
4.4.2.3.1 Programming the FPGA through the JTAG interface................................................ 24
4.4.2.3.2 Programming the FPGA through the GPIO............................................................... 27
4.4.2.3.3 Programming the uncommitted FPGA from the configuration PROM....................... 28
4.4.2.4 Uncommitted FPGA power supplies.............................................................................. 29
4.4.2.5 Uncommitted FPGA Pull-ups/downs ............................................................................. 30
4.4.2.6 Increasing the number of unused uncommitted FPGA I/O ........................................... 30
5. RDK Mode Configuration ..................................................................................................................... 31
6. Examples of Testing the OnBoard 32Kx32 SBSRAM with PLXMon ................................................... 33
7. CPLD Verilog Code.............................................................................................................................. 35

PEX 8311RDK Hardware Reference Manual, Version 0.90
vi © 2005 PLX Technology, Inc. All rights reserved.
7.1 Verilog Code.................................................................................................................................. 35
8. References........................................................................................................................................... 39
9. Bill of Materials / Schematics ............................................................................................................... 41
FIGURES
Figure 1-1. PEX 8311RDK – Component Side View.................................................................................... 1
Figure 3-1. PEX 8311RDK Hardware Architecture ...................................................................................... 4
Figure 4-1. PEX 8311RDK Component Placement.................................................................................... 15
Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints..................................................................... 18
Figure 4-3. PEX 8311RDK Stackup ........................................................................................................... 18
TABLES
Table 3-1. Long Serial EEPROM Load Registers ........................................................................................ 6
Table 3-2. Extra Long Serial EEPROM Load Registers............................................................................... 7
Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map .................................................................. 10
Table 3-4. PEX 8311RDK LED Indicators.................................................................................................. 11
Table 3-5. PEX 8311RDK Power supply currents...................................................................................... 12
Table 3-6. PEX 8311RDK Power jumper and resistor options................................................................... 12
Table 4-1. PEX 8311RDK Default Jumper Settings ................................................................................... 17
Table 4-2. Layer thickness ......................................................................................................................... 19
Table 4-3. Six (6) Surface Mount Footprints .............................................................................................. 19
Table 4-4. Uncommitted FPGA resistor configuration................................................................................ 21
Table 4-5. Altera Uncommitted FPGA JTAG interconnections .................................................................. 25
Table 4-6. Xilinx Uncommitted FPGA JTAG interconnections ................................................................... 26
Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO.............................................. 27
Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO............................................... 28
Table 4-9. Platform Flash to Xilinx interconnect......................................................................................... 29
Table 5-1. RDK Board Mode Configuration................................................................................................ 31
Table 9-1. PEX 8311RDK Bill Of Materials ................................................................................................ 41

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. vii
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8311RDK,
or for any damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8311RDK, the PEX 8311 Rapid Development Kit, from a
hardware perspective. It contains a description of all major functional circuit blocks on the board and also
is a reference for the creation of software for this product. This manual also includes a complete bill of
materials and schematics.
REVISION HISTORY
Date Version Comments
December
2005 0.90 Initial Blue Book Release

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. 1
1. General Information
The PLX PEX 8311RDK is a Rapid Development Kit based on the PEX 8311, a single-lane, PCI Express-
to-local bus bridge device. The PEX 8311RDK provides a complete hardware and software development
platform to facilitate getting designs up and running quickly, lowering risk and reducing time-to-market.
The PEX 8311RDK allows the upstream PCI Express port of the PEX 8311 device to be connected to a
host system slot by way of a standard PCI Express edge connector (the PEX 8311RDK is designed to
plug into a PCI Express motherboard slot). On board Synchronous burst SRAM allows testing of data
transfers and DMA operation.
The PEX 8311RDK is shipped pre-configured for de-multiplexed generic address/data bus (C mode)
operation, but is very easily reconfigured for multiplexed address/data bus (J mode) applications. The
RDK provides 5 surface mount QFP/SOIC/SSOP footprints and for hardware designers to easily add
processors, DSPs, ASICs, FPGAs, memory, and I/O devices to test, simulate, and debug their designs
without fabricating their own boards, saving considerable of time in the development process and
reducing time to market. The PEX 8311RDK’s software, hardware and registers are backward-compatible
with the PCI 9056RDK-LITE and PCI 9656RDK-LITE, simplifying the migration of existing PCI designs
into PCI Express products.
LED7
LED6
LED5
LED4
PLX Technology , Inc .
PEX8311 RDK
COPYRIGHT 2005
J3
JP1
U4
Regulator
J4
5V Power Connector
POM Module Connector
PEX-MCM
JP2
JP3
JP4
JP5
JTAG
Header
PEX8311
J5
Midbus
CPLD SYN_SRAM
66MHz
Oscillator for
LocalClock
Socket
FPGA
PQFP
SSOP
SSOP
Socket
1
Eeprom
Socket
1
Eeprom
U9
Regulator
Test Headers
+12V
+5V
PEXCLK
PERST#
LED 1
LED 2
LED 3
LED 4
PERST#
J1
U2
U5
U8
U3
Regulator
LAH1
LAH5
LAH2
LAH3 LAH6 LAH4
Prototyping Area
U6
SOIC
SSOP
J9
J7
J8
JTAG
Header
J2
TP11
TP10
TP5
TP8
TP9
TP4
TP2
TP3
TP7
TP1
TP6
Figure 1-1. PEX 8311RDK – Component Side View

PEX 8311RDK Hardware Reference Manual, Version 0.90
2 © 2005 PLX Technology, Inc. All rights reserved.
1.1 PEX 8311 Features
Compliant to PCI Express Base Specification, Revision 1.0a
Local bus and register compatibility with PCI 9056 and PCI 9656 allows systems to migrate to
PCI Express and leverage software compatibility
Integrated single PCI Express port and interface with x1 link, dual-simplex 2.5 Gbps SerDes
Configurable local bus supporting 8, 16 and 32 bit local bus architectures
Multiplexed and non-multiplexed local bus operation
Powerful high performance DMA engine supporting block, scatter gather, ring management and
demand mode
Supports Endpoint and Root Complex Modes
Small package, enabling compact design
Low power consumption
3.3V I/O and 5V tolerant local bus
Serial EEPROMs used for optional boot configuration with Serial Peripheral Interface (SPI) and
Microwire Interface
8-KB general-purpose shared RAM
1.2 PEX 8311RDK Features
PLX PCI Express-to-PCI bridge device in a 21 x 21 mm, 337-ball PBGA package
Single x1 PCI Express Edge connector for insertion into standard PCI Express slot of x1 or
greater link width
Supports 32-bit C (default) or J mode Processor/Local Bus operation with speeds up to 66MHz
128KB synchronous burst SRAM with the CPLD memory controller demonstrates the PEX 8311
continuous burst feature
Jumpers for PEX 8311 hardware configuration
Socketable SPI and Microwire serial EEPROMs (3.3V devices supported)
Onboard probing points and logic analyzer connections
LEDs for link status visual inspection and power supply operation
Auxiliary ATX hard disk connector for additional power requirement support
Prototyping area with five (5) surface mount footprints, one (1) voltage regulator footprint, and
one (1) 20x10, 0.1” through-hole grid
Pushbutton reset module
Socketed oscillator for Processor/Local Bus clock and local logic
PLX J-Bus Option Module (POM) connector for expansion
Option for on board PCI Express reference clock generation

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. 3
2. PEX 8311RDK System Architecture
The PEX 8311RDK assists customers in evaluating PLX Technology’s PEX 8311 PCI Express to local
bus bridge device, and to facilitate early development of customer designs with the PEX 8311. The board
is designed to operate with the PEX 8311 configured in Endpoint mode. This allows bridging between a
PCI Express base board and local bus processors or logic. The PEX 8311RDK is designed to showcase
many of the PEX 8311 features when operating in Endpoint mode.
The PEX 8311RDK’s form factor is a eight-layer assembled 6.6"L x 8.15"W PC board. The local bus
interface supports 8, 16 or 32-bit transfers, at up to 66 MHz. The PCI Express interface supports one lane
operating at 2.5 Gbps.
PEX 8311RDK power is generated from the +12VDC and +3.3VDC, provided through the PCI Express
edge connector. Additional +5VDC and +12VDC power can be provided using an external power supply
plugged into the on board 4-pin ATX header.

PEX 8311RDK Hardware Reference Manual, Version 0.90
4 © 2005 PLX Technology, Inc. All rights reserved.
3. PEX 8311RDK Hardware Architecture
PEX8311
PCI Express x1
Link
Serial
EEPROMs
Local Bus
Clock Circuit
66MHz
LOCAL BUS
Up to 32-bit 66MHz
Address Bus
Data bus
Control Bus
POM Connector Test Headers
Synchronous
SRAM
32Kx32
SRAM
Controller
Data Bus
Ready# Memory
Address
Bus
Controls
PEX 8311 RDK Hardware Block Diagram
732
8
SRAM Controller
Arbiter
Chip Select
Generator
Controls
8
Address
Xilinx CPLD
Bterm#
PCI Express
100MHz clock
PCI Express
100MHz Clock
Circuit
(not populated)
Midbus
Connector
(not
populated)
x
1
P
C
I
E
x
p
r
e
s
s
C
a
r
d
E
d
g
e
PCI Express
Pushbutton
Reset Circuit
Prototyping
Area &
Footprints
LED's for
GPIO's and
power
supplies
Internal Clock
Circuit
66MHz (not
populated)
Local
Clock
Figure 3-1. PEX 8311RDK Hardware Architecture
3.1 PEX 8311 PCI Express Bridge Device
The PEX 8311 (U1) is a high-performance PCI Express to local bus device that enables designers to
migrate legacy designs to the new, advanced serial PCI Express. This 2-port device is equipped with a
single-lane PCI Express port and a parallel local bus segment supporting multiplexed (J mode) and non-
multiplexed (C Mode) operating modes. The PEX 8311 is capable of operating as an Endpoint or a Root
Complex. The PEX 8311 bridge device is housed in a 21 x 21 mm, 337-ball PBGA package. Ball spacing
is 1.0 mm. No additional cooling is required.
The PEX 8311 supports Direct Slave and Direct Master data transfers; in addition there are two DMA
channels, and an Intelligent Messaging Unit. For more detailed information about the PEX 8311 please
see the PEX 8311 data book.
3.2 Serial EEPROM
The PEX 8311 bridge device has two EEPROM’s associated with it. These EEPROM’s can be used to
load configuration data on power-up.

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. 5
3.2.1 SPI EEPROM
The SPI EEPROM (U2) is the Express Configuration EEPROM. This is largely used to control PCI
Express performance and is not normally required to bring up the PEX 8311. The SPI EEPROM (U2) can
also be used to pre-configure the on-chip 8K shared memory.
The SPI EEPROM (U2) is connected to an 8-pin DIP socket to allow removal and programming with
external PROM programmer if required. The EEPROM can also be programmed through the PEX 8311
using the utilities provided. A pull-up resistor (R4) on the EERDDATA ball produces a value of FFh if there
is no serial EEPROM installed.
The PEX 8311 supports up to 16 MB SPI serial EEPROM’s, utilizing 1, 2, or 3-byte addressing. The PEX
8311 automatically determines the appropriate addressing mode. The SPI operates at up to 25 MHz and
can directly interface with the PEX 8311. The Atmel AT25640 device as used in the PEX 8311RDK is
recommended. Other compatible 128-byte serial EEPROM’s include the Atmel AT25010A, Catalyst
CAT25C01, and ST Microelectronics M95010W.
The SPI EEPROM on the PEX 8311RDK is blank when shipped.
3.2.2 Microwire Serial EEPROM
The socketed 2Kbit Microwire serial EEPROM (U6) is the Local Configuration EEPROM and is used to
control local bus behavior and assign appropriate address ranges. It is connected directly to the PEX
8311 and provides the configuration data to initialize the device after the system reset is removed. The
EEPROM image is compatible with those of the PLX PCI 9x56 devices and may be loaded with those
images to speed development.
The Microwire EEPROM will be required for most designs to ensure that the correct address space
ranges are assigned. A pull-up on EEDI/EEDO (R36) ensures that the RDK will boot if a blank EEPROM
is installed. If no EEPROM is installed then a pull-down will be required on EEDI/EEDO (R39) to ensure
that the device boots correctly.

PEX 8311RDK Hardware Reference Manual, Version 0.90
6 © 2005 PLX Technology, Inc. All rights reserved.
3.2.2.1 Microwire Serial EEPROM Contents
Table 3-1. Long Serial EEPROM Load Registers
Serial
EEPROM
Offset
Serial
EEPROM
Hex Value
Description Register Bits Affected
0h 86E1 Device ID PCIIDR[31:16]
2h 10B5 Vendor ID PCIIDR[15:0]
4h 0680 Class Code PCICCR[23:8]
6h 00AA Class Code, Revision of the PEX 8311 PCICCR[7:0] / PCIREV[7:0]
8h 0000 Maximum Latency, Minimum Grant PCIMLR[7:0] / PCIMGR[7:0]
Ah 0100 Interrupt Pin, Interrupt Line Routing PCIIPR[7:0] / PCIILR[7:0]
Ch 0000 MSW of Mailbox 0 (User Defined) MBOX0[31:16]
Eh 0000 LSW of Mailbox 0 (User Defined) MBOX0[15:0]
10h 0000 MSW of Mailbox 1 (User Defined) MBOX1[31:16]
12h 0000 LSW of Mailbox 1 (User Defined) MBOX1[15:0]
14h FFFE MSW of Range for PCI-to-Local Address Space 0 LAS0RR[31:16]
16h 0000 LSW of Range for PCI-to-Local Address Space 0 LAS0RR[15:0]
18h 0000
MSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 0 LAS0BA[31:16]
1Ah 0001
LSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 0 LAS0BA[15:0]
1Ch 0120 MSW of Mode/DMA Arbitration Register MARBR[31:16]
1Eh 0000 LSW of Mode/DMA Arbitration Register MARBR[15:0]
20h 2030
Local Miscellaneous Control Register 2 /
Serial EEPROM Write-Protected Address Boundary
LMISC2[7:0] /
PROT_AREA[7:0]
22h 8500
Local Miscellaneous Control Register 1 /
Processor/Local Bus Big/Little Endian Descriptor Register
LMISC1 [7:0] /
BIGEND [7:0]
24h 0000 MSW of Range for PCI-to-Local Expansion ROM EROMRR[31:16]
26h 0000 LSW of Range for PCI-to-Local Expansion ROM EROMRR[15:0]
28h 0000
MSW of Local Base Address (Re-map) for
PCI-to-Local Expansion ROM EROMBA[31:16]
2Ah 0000
LSW of Local Base Address (Re-map) for
PCI-to-Local Expansion ROM EROMBA[15:0]
2Ch 4343
MSW of Bus Region Descriptors for
PCI-to-Local Address Space 0 and Expansion ROM LBRD0[31:16]
2Eh 00C3
LSW of Bus Region Descriptors for
PCI-to-Local Address Space 0 and Expansion ROM LBRD0[15:0]
30h 0000 MSW of Range for Direct Master-to-PCI DMRR[31:16]
32h 0000 LSW of Range for Direct Master-to-PCI DMRR[15:0]
34h 6000 MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16]
36h 0000 LSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[15:0]
38h 5000
MSW of Processor/Local Bus Address for
Direct Master-to-PCI I/O Configuration DMLBAI[31:16]
3Ah 0000
LSW of Processor/Local Bus Address for
Direct Master-to-PCI I/O Configuration DMLBAI[15:0]
3Ch 0000 MSW of PCI Base Address (Re-map) for Direct Master-to-PCI DMPBAM[31:16]
3Eh 0000
LSW of Processor/Local Bus Address for
Direct Master-to-PCI Memory DMPBAM[15:0]
40h 0000
MSW of PCI Configuration Address Register for
Direct Master-to-PCI I/O Configuration DMCRGA[31:16]
42h 0000
LSW of PCI Configuration Address Register for
Direct Master-to-PCI I/O Configuration DMCFGA[15:0]

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. 7
Table 3-2. Extra Long Serial EEPROM Load Registers
Serial
EEPROM
Offset
Serial
EEPROM
Hex Value
Description Register Bits Affected
44h 8311 Subsystem ID PCISID[15:0]
46h 10B5 Subsystem Vendor ID PCISVID[15:0]
48h FFFE MSW of Range for PCI-to-Local Address Space 1 LAS1RR[31:16]
4Ah 0000 LSW of Range for PCI-to-Local Address Space 1 LAS1RR[15:0]
4Ch 0000
MSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 1 LAS1BA[31:16]
4Eh 0001
LSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 1 LAS1BA[15:0]
50h 0000
MSW of Bus Region Descriptors for
PCI-to-Local Address Space 1 LBRD1[31:16]
52h 01C3
LSW of Bus Region Descriptors for
PCI-to-Local Address Space 1 LBRD1[15:0]
54h 0000 Hot Swap Control/Status Register Reserved
56h 4C06
Hot Swap Control/Status Register /
Hot Swap Next Capability Pointer HS_NEXT[7:0] / HS_CNTL[7:0]
58h 0000 Reserved Reserved
5Ah 0000 PCI Arbiter Control PCIARB[15:4] / PCIARB[3:0]
5Ch 7A02 Power Management Capabilities PMC[15:9,2:0]
5Eh 4801
Power Management Next Capability Pointer /
Power Management Capability ID
(the LSB is reserved)
PMNEXT[7:0] / PMCAPID[7:0]
60h 0000
Power Management Data /
PMCSR Bridge Support Extensions
(the LSB is reserved)
PMDATA[7:0]/ PMCSR_BSE[7:0]
62h 0000
Power Management Control/Status
(Bits 15, 7:2, and 1:0 are reserved) PMCSR[15:0]
3.3 Local and PCI Express Hardware Elements
As shown in Figure 3-1, the RDK hardware contains:
•PEX 8311 PCI Express I/O Accelerator
•Four PEX 8311 Local Bus components (Local clock distribution, CPLD, SBSRAM, Test Headers,
and POM connector)
•LED’s for GPIO and power supply status
•Small prototyping area – including an uncommitted FPGA footprint
•PCI Express Reset Circuitry (see section 3.4.2.1 Reset Circuitry)
•A hardware development module for PCI Express clock generation (see section 3.4.1 RefClk)
•A hardware development module for the PEX 8311 internal reference clock (see section 3.3.4
Internal Clock)
The RDK’s Local Bus is pre-configured for non-multiplexed address and data bus operation (C mode), but
it is user-configurable to allow multiplexed address and data operation (J Mode). (See Section 5 RDK
Mode Configuration for details on re-configuring the RDK hardware for J Mode operation.) Once the
board is correctly installed into a PC computer system, a host, such as the motherboard’s processor, can
perform single cycle memory read/write cycles, multiple memory read/write cycles, and burst memory
read/write cycles from/to the on-board SBSRAM in Direct Slave mode. The host can also program the
PEX 8311 to perform DMA data transfers between the PCI Express bus and the SBSRAM.

PEX 8311RDK Hardware Reference Manual, Version 0.90
8 © 2005 PLX Technology, Inc. All rights reserved.
3.3.1 Local Clock
The PEX 8311 has a local clock input which is required for normal operation. The Cypress Semiconductor
CY2305 Zero Delay 1-to-5 clock buffer (U7) provides onboard local clock distribution to the PEX 8311,
SBSRAM, CPLD, test headers and the POM connector. The CY2305 input is sourced by the socketed
onboard oscillator (U8). The socketed oscillator (U8) can be changed to allow PEX 8311 local bus
operation at any frequency from 10 to 66MHz. The 10MHz minimum is a restriction of the CY2305, the
local bus of the PEX 8311 can run at any frequency from 0 to 66MHz.
3.3.2 Synchronous Burst SRAM
A 100-pin, 7.5ns, 32K x 32 Micron Synchronous Burst SRAM (U11) is used for Processor/Local Bus data
storage on the RDK. During Direct Slave memory burst cycles, the SBSRAM performs continuous back-
to-back single read cycles or single write cycles. The Xilinx CPLD SBSRAM controller (U10) does all of
the timing conversion and generates the lower 8 address bits to the SBSRAM. The SBSRAM takes 7
upper address lines (LA16-LA10) directly from the PEX 8311 and 8 lower address lines (MA[9:2]) from
the SBSRAM controller. The data lines of the SBSRAM are directly connected to the PEX 8311 local data
bus (LD31-LD0).
3.3.3 Xilinx CPLD
A 5ns Xilinx XC9572XL-5TQ100C CPLD (U10) is used as the SBSRAM controller, external
Processor/Local Bus arbiter, and chip select generator.
The SBSRAM controller in the CPLD generates the lower 8-bit memory address (MA[9:2]), SBSRAM chip
select (SRAMCS#), SBSRAM output enable (SRAMOE#), and SBSRAM byte write enables
(SRAM_BW_[3:0]) to the SBSRAM. It latches the starting address signals (LA[9:2] for C mode and
LAD[9:2] for J mode), and uses its built-in internal address counter to advance the addresses to the
SBSRAM. The SBSRAM controller also generates the active low ready signal (READY#) to terminate
normal PEX 8311 memory cycles and also generates the active low (BTERM#) input to the PEX 8311 to
break the continuous burst memory cycle when its internal address counter reaches the final count (FFh).
The external Processor/Local Bus arbiter in the CPLD accepts the Processor/Local Bus request signals
(LBR [1:0]) from Processor/Local Bus masters, if there are any, and the bus request from the PEX 8311
(LHOLD). It generates bus grant signals LBG [1:0] to the Processor/Local Bus masters and LHOLDA to
the PEX 8311.
The chip select generator in the CPLD generates the SBSRAM chip select (SRAMCS#) and four
additional active low chip selects for the Processor/Local Bus devices. The chip select signals are
partially decoded from the upper four address lines (LA31-LA28) on the Processor/Local Bus. They can
be re-programmed by altering the CPLD Verilog code.
3.3.4 Internal Clock
The PEX 8311 requires an internal clock source in addition to the PCI Express clock and the local clock.
When the PEX 8311 is operating in Endpoint mode the PEX 8311 will generate the internal clock itself.
The internal clock output (CLKOUT, ball A8) is fed directly to the internal clock input (CLKIN, ball A15) via
the 0 ohm series resistor R53.
When the PEX 8311 is operating in Root Complex mode then the internal clock must be provided from an
external source. While the PEX 8311RDK is not designed to operate in Root Complex mode provision
has been made for an external clock oscillator to provide the internal clock to the PEX 8311. The
components for the external clock are not assembled nor do they appear on the BOM. Customers who
require this feature must source and assemble the components themselves. PLX takes no responsibility
for boards damaged during this operation
If the external oscillator is to be used remove R53 and assemble R52, R150, C96, C97 and U13. The
maximum operating frequency for U13 should be 66MHz.

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. 9
3.3.5 PLX Option Module Connector
The PLX Option Module Connector (J3) assumes that the Local Bus is configured for 32-bit multiplexed
address/data bus (J mode) operation. (See Section 5 - RDK Mode Configuration - for details on re-
configuring the RDK hardware for J Mode operation.) It can be used for expansion and prototyping.
Both/either a master and/or slave devices may be connected to this connector, which resides at Local
Bus address range 1000 0000 – 1FFF_FFFFh. The external arbiter in the CPLD uses CS0# to select the
POM module. Schematic sheet 6 provides the connector signal details.
The connector to mate to J3 can be purchased from AMP distributors the part number is: 6-104652-0

PEX 8311RDK Hardware Reference Manual, Version 0.90
10 © 2005 PLX Technology, Inc. All rights reserved.
3.3.6 Hardware Memory Map
The PEX 8311RDK Local Bus memory map is shown in Table 3-3.
Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map
Hex Address
Range Device Chip Select Comments
FFFF FFFF
5000 0000 Unused _ Available
4FFF FFFF
4000 0000
Uncommitted FPGA
(FP2) CS3# Available &
Re-programmable
3FFF FFFF
3000 0000 Unused CS2#
Available &
Re-programmable
2FFF FFFF
2000 0000 Unused CS1#
Available &
Re-programmable
1FFF FFFF
1000 0000 J mode POM connector CS0# 32-bit, multiplexed
address/data bus
0FFF FFFF
0002 0000 Unused _ Available
0001 FFFF
0000 0000
Synchronous burst
SRAM
32Kx32
SRAMCS# 8-, 16-, or 32-bit access
3.4 PCI Express Interface
The PCI Express interface is a male card edge connector, based on the PCI Express Card
Electromechanical (CEM) Specification, Revision 1.0a for an x1 interface. In addition to the PCI Express
TX/RX pairs the card edge provides +12 VDC and +3.3 VDC, RefClk, and PERST#. The PCI Express
TX/RX signals are laid out as 100-Ohm, controlled-impedance, microstrip-differential pairs. Trace length
mismatch within signal pairs is not greater than 0.005".
3.4.1 RefClk
PCI Express RefClk enters the PEX 8311RDK through the PCI Express card edge (male) connector.
RefClk is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch
is not greater than 0.005".
Land is provided for the PCI Express RefClk to be generated onboard by an optional clock synthesizer
(U12), using a 25-MHz crystal for the seed frequency. The PEX 8311RDK can use the IC557G-03 part
from Integrated Circuit systems, Inc., though any comparable synthesizer is sufficient. RefClk is routed to
the PEX 8311. An unused 100MHz reference clock (REFCLK2) is also available from (U12). RefClk
routing is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch
within this pair is less than 0.005".
When using the optional on board clock generator R12 and R13 should be removed to ensure that the
locally generated clock is not driven to the PCI Express edge connector (P1). In addition, R1 and R2
should be populated to route the on board clock to the PEX 8311.
The components for the on-board PCI Express clock circuitry are not assembled nor do they appear on
the BOM. Customers who require this feature must source and assemble the components themselves.
PLX takes no responsibility for boards damaged during this operation.
3.4.2 PERST#
PERST# is the fundamental Reset signal to the PEX 8311, from the PCI Express edge connector.

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved. 11
3.4.2.1 Reset Circuitry
The reset pushbutton (SW1) allows the user to force the PEX 8311 PERST# signal low. This causes a full
reset of the device and the local bus logic. Pressing the reset button causes LRESET# to be asserted and
will cause all EEPROM values to be re-loaded.
Pressing the pushbutton reset will also clear all configuration registers including the PCI Express
configuration registers. The PEX 8311 will have to be re-enumerated by the host before it will respond to
PCI Express memory transactions.
3.5 LED Indicators
The PEX 8311RDK provides several LED indicators, including power-on indication and programmable
PEX 8311 GPIO lane status indication. Table 3-4 provides a quick explanation of each LED indicators.
By default GPIO[3:1] are configured as inputs and pulled high and GPIO0 shows the link status. By
changing GPIOCTL[13:12] in the SPI EEPROM (U2) the GPIO lines can be reconfigured to reflect the
lower four bits of the LTSSM state machine. See the PEX8311 data book for additional details.
Table 3-4. PEX 8311RDK LED Indicators
Indicator Type Location LED ON
LED5 PCI Express 12V power on
LED6 3.3V power is on
Board Power Indication
LED8 2.5V power is on
GPIO0 LED1
Output
OFF (0) – Link Down
ON (1) – Link Up
GPIO1 LED2 ON, GPIO1 = Input by default
GPIO2 LED3 ON, GPIO2 = Input by default
GPIO3 LED4 ON, GPIO3 = Input by default
3.6 PEX 8311RDK Power
The PEX 8311RDK has two sources for DC power. The first source is the card edge connector (P1). This
x1 connector provides up to 500 mA at +12VDC, and 3.0A at +3.3VDC. Card edge power is intended to
power only PEX 8311RDK components.
The second source, the ATX 4-pin connector (J4), provides +12VDC, and the +5VDC power supplied to
the POM connector.
The electronic devices on the RDK require +1.5V, +2.5V, and +3.3V DC power. A 5A LDO regulator (U4)
is used to convert the PCI Express +12 VDC to +3.3 VDC, a 2.5A LDO regulator (U9) is used to convert
the PCI Express +3.3 VDC to +2.5 VDC and a 250mA regulator (U3) is used to convert the PCI Express
+3.3 VDC to +1.5 VDC power for the on board devices. As long as the output current from the voltage
converter remains less than the maximum current outputs from the LDOs, the RDK board will function
correctly.
3.6.1 PEX 8311 Bridge Device Power
The PEX 8311 bridge device power requires the following:
VDD Core +1.5 VDC ±10%
+2.5 VDC ±10%
VDD I/O+3.3 VDC ±10%
Care must be taken to ensure that the power sequencing requirements of the PEX 8311 are met – please
refer to the PEX 8311 data book for further details.
As shipped the absolute maximum current required for the PEX 8311RDK supplies is detailed in Table
3-5.

PEX 8311RDK Hardware Reference Manual, Version 0.90
12 © 2005 PLX Technology, Inc. All rights reserved.
Table 3-5. PEX 8311RDK Power supply currents
Power Supply Maximum required by the RDK Maximum available from the Regulator
+1.5 VDC 240mA 250mA
+2.5 VDC 220mA 2.5A
+3.3 VDC 450mA 5A1
Note 1: A maximum of 1.8A is available when U4 is fed from the 12V supply of a 10W PCI Express connector.
When using the 1.5V supply to provide power to the uncommitted FPGA it may be necessary to change
U3 to a larger regulator to ensure sufficient power supply current is available.
3.6.2 PEX 8311 Power Jumpers and Resistor options
Various power jumpers and resistor options are available on the PEX 8311 RDK to allow the power
consumption of the PEX 8311 to be measured under different operating conditions.
Table 3-6 details the jumper and resistor settings for the main power options. For the uncommitted FPGA
power options please see section 4.4.2.4 Uncommitted FPGA power supplies.
Table 3-6. PEX 8311RDK Power jumper and resistor options
Jumper Factory Setting Description
J7 CLOSED +3.3V supply to PEX 8311
J8 CLOSED +1.5V supply to PEX 8311
J9 CLOSED +2.5V supply to PEX 8311
R21 ASSEMBLED Link PCI Express 12V supply to U4 (+3.3V regulator)
R22 NOT ASSEMBLED Link ATX (J4) 12V supply to U4 (+3.3V regulator)
R23 ASSEMBLED U4 (3.3V Regulator) provides +3.3V supply to RDK
R27 NOT ASSEMBLED PCI Express 3.3V supply (P1) provides +3.3V supply to RDK