PLX Technology PEX 8505 Quick user guide

PEX 8505RDK
Hardware Reference Manual

PEX 8505RDK
Hardware Reference Manual
Version 1.1
October 2007
Website: http://www.plxtech.com
Support: http://www.plxtech.com/support
Phone: [phone]
800 759-3735
Fax: [phone]

© 2007 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX 8505-RDK-HRM-1.1
Printed in the USA, October 2007

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. i
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any
damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8505RDK, a Rapid Development Kit, from a hardware perspective.
It contains a description of all major functional circuit blocks on the board and also is a reference for the
creation of software for this product. This manual also includes complete schematics and bill of materials.
REVISION HISTORY
Date Version Comments
May 2007 0.90 Hardware Reference Manual initial release.
June 2007 1.0 Minor content update.
October
2007 1.1 Fixed note in schematic.

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. iii
CONTENTS
1. General Information ................................................................................................. 1
1.1 PEX 8505 Features .......................................................................................... 2
1.2 PEX 8505RDK Features................................................................................... 2
1.3 RDK Port Expansion Kit Features .................................................................... 2
1.3.1 RDK Port Expansion Kit Components ....................................................... 3
2. PEX 8505RDK Hardware Architecture .................................................................... 5
2.1 PEX 8505 PCI Express Switch ......................................................................... 6
2.2 PCI Express Card Edge P1 .............................................................................. 6
2.3 PCI Express Connector J1 ............................................................................... 6
2.4 Reference Clock Circuitry ................................................................................. 6
2.5 Reset Circuitry .................................................................................................. 7
2.6 Serial EEPROM................................................................................................ 7
2.7 I2C Interface ..................................................................................................... 7
2.8 Power Distribution ............................................................................................ 7
2.8.1 Power Generation/Conversion .................................................................. 7
2.8.2 Power Sequencing .................................................................................... 8
2.9 LED Indicators .................................................................................................. 8
3. On-Board Connectors, Switches, and Jumpers..................................................... 11
3.1 DIP Switches .................................................................................................. 11
3.1.1 Upstream Port Selection (SW1) .............................................................. 11
3.1.2 PEX 8505 I2C Address Selection (SW2)................................................. 11
3.2 Push-Button Switches..................................................................................... 12
3.2.1 Hot Plug Attention Button# (SW5) ........................................................... 12
3.2.2 Manual Reset# (SW6) ............................................................................. 12
3.3 EEPROM Enable Jumper (JP5) ..................................................................... 12
3.4 JTAG Header (JP1) ........................................................................................ 12
3.5 PCI Express Fatal Error Indication (D9).......................................................... 12
3.6 PEX INTA# (D19) ........................................................................................... 12
3.7 Slots J1 Power Fault Indication (D20) ............................................................ 13
4. Serial EEPROM Registers..................................................................................... 13
4.1 Serial EEPROM Contents............................................................................... 13
5. FAQ/Troubleshooting............................................................................................. 13
5.1 Frequently Asked Questions........................................................................... 13
6. Bill of Materials/ Schematics.................................................................................. 13

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. iv
FIGURES
FIGURE 1-1. PEX 8505RDK COMPONENT SIDE VIEW ...................................................................................... 1
FIGURE 1-2. RDK PORT EXPANDER ................................................................................................................ 3
FIGURE 1-3. PCIE CABLE ADAPTER ................................................................................................................. 3
FIGURE 1-4. PCIE 1-METER X1CABLE ............................................................................................................. 3
FIGURE 2-1. PEX 8505RDK HARDWARE ARCHITECTURE................................................................................. 5
FIGURE 2-2. PEX 8505RDK REFERENCE CLOCK CIRCUIT ............................................................................... 6
FIGURE 2-3. I2C CONNECTOR ORIENTATION FOR AARDVARD I2C CONTROLLER ................................................ 7
FIGURE 2-4. PEX 8505RDK POWER SUBSYSTEM............................................................................................ 8
FIGURE 3-1. SWITCH SW1 DEFAULT SETTINGS .............................................................................................. 11
FIGURE 3-2. SWITCH SW2 DEFAULT SETTINGS .............................................................................................. 11
TABLES
TABLE 2-1. PEX 8505RDK LED INDICATOR DESCRIPTIONS ............................................................................. 8
TABLE 3-1. SWITCH SW1 DESCRIPTION......................................................................................................... 11
TABLE 3-2. SWITCH SW2 DESCRIPTION......................................................................................................... 12
TABLE 3-3. JUMPER JP2 SETTINGS ................................................................................................................ 12

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 1
1. General Information
The PLX PEX 8505RDK is a Rapid Development Kit based on the PEX 8505, a 5-lane, 5-port PCI
Express switch. The PEX 8505RDK provides a complete hardware and software development platform to
facilitate getting designs up and running quickly, lowering risk and reducing time-to-market.
An RDK Port Expansion Kit is included, which is used to convert the PEX 8505RDK into a bench top
platform that supports the full 5-port/5-lane configuration. When mated to the RDK Port Expander, the
upstream port is connected to a PCI Express x1 Cable connector. The Expansion Kit includes a 1-meter
cable and adapter card, which allows the PEX 8505’s upstream port to connect to any standard PC. See
the RDK Port Expansion Kit Hardware Reference Manual for more details.
Figure 1-1. PEX 8505RDK Component Side View
PEX
8505
JTAG Header
Reference Clock Buffers
Reset Circuitry
3.3V-1V
Regulator
5V-3.3V DC/DC
converter
VTT Regulator
Manual PERST#
EEPROM
Socket
I2C
A1
U1
J1
J5
Main Board Power
Indicators
P1
Slots J1/J2/J3
Power Indicator
Lanes
0 1 2 3
4 5 6 7
Powered by J5
User Control DIP switch
U10
U11
U12
U13
SW6
U14
U2
JP3
JP4
JP1
U9
U8
SW1
SW2
JP2
JP5
Lanes
User Control DIP switch

PEX 8505RDK Hardware Reference Manual v1.1
2 © 2007, PLX Technology, Inc. All rights reserved.
1.1 PEX 8505 Features
•5-lane, 5-port (maximum) PCI Express switch
•PCI Express Base Specification revision 1.1 and PCI Standard Hot-Plug Controller and
Subsystem Specification, revision 1.0 compliance
•Five PCI Express lanes provide 25 Gbps aggregate bandwidth
•Cut-thru Packet latency of 210ns (x1 to x1)
•Non-blocking internal crossbar architecture supports full wire speed
•Out of band communication/initialization interfaces (Serial EEPROM and I2C)
•Maximum Payload Size up to 1024 bytes
•Performance tuning
•Up to 5-ports (Up to 4 possible port configurations)
•PCI Express Standard Hot Plug Controller for three ports
•Allows any port to be designated as upstream port
•Configuration with strapping pins and/or EEPROM
•Sideband INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) signaling
•Lane reversal
1.2 PEX 8505RDK Features
•PLX PEX 8505 PCI Express switch in a 196-ball PBGA package
•Form factor based on PCI Express Card Electromechanical (CEM) Specification 1.1
•Four downstream PCI Express Slot connectors
•DIP switches for hardware configuration of PEX 8505 and on-board clock circuitry
•Support for Spread Spectrum Clocking (SSC).
•One Hot Plug controllable slot
•Socketable Serial EEPROM (3.3V)
•Standard 0.1” headers to connect up to I2C
•Manual push-button PERST# capability
•Lane Status indicator LEDs for visual inspection of link status
•Auxiliary ATX Hard disk connector for supporting additional power requirements for add-in cards
1.3 RDK Port Expansion Kit Features
•Provides a 4-lane/4-port breakout for PEX 8505 RDKs
•Upstream Connection via standard PCI Express x1cable
•Three downstream PCI Express Slot connectors
•Support for Spread Spectrum Clocking (SSC).
•Standard 0.1” headers to connect up to SM bus
•Manual push-button PERST# capability
•Auxiliary ATX Hard disk connector for supporting additional power requirements for add-in cards

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 3
1.3.1 RDK Port Expansion Kit Components
Figure 1-2. RDK Port Expander
Figure 1-3. PCIe Cable Adapter
Figure 1-4. PCIe 1-meter x1 cable
J3
J4
J5
J6
J2
U4
J1
SW1
1
2
3
RDK SLOT
PCI Express
Cable Connector
(Upstream Port)
Downstream
Slots
Manual
PERST#
J1
U3
PCI Express x1
cable adapter
PCI Express x1
Card Edge

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 5
2. PEX 8505RDK Hardware Architecture
Figure 2-1. PEX 8505RDK Hardware Architecture
Port 0 Port 1 Port 2 Port 3
PEX 8505
x4 Card Edge
EEPROM
I2C
DIP
switch 82
4
Reset
Timer
PERST#
REFCLK
JTAG
connector
5
P1
J5
J4
J1
Port 4
x16 Connector
J6
RefClk
Buffer
RefClk
Buffer
x1
x16 Connector
x16 Connector
x16 Connector
x1
x1
x1
x1
RDK Port Expander
PCIe x1 Cable
x16 Connector J3
J1
PEX 8505RDK

PEX 8505RDK Hardware Reference Manual v1.1
6 © 2007, PLX Technology, Inc. All rights reserved.
2.1 PEX 8505 PCI Express Switch
The PEX 8505 is a 5-lane, 5-port (maximum) PCI Express switch, which can be configured using strap
pins or EEPROM. The RDK’s onboard PEX 8505 is set up as a 5-port switch, with one x1 upstream port
(Port 0) and four x1 downstream ports (Ports 1 - 4). Ports 0 - 3 connects to the card edge (P1), while Port
4 connects to x16-sized slot connectors (J1). The PEX 8509RDK plugs into an RDK Port expander which
breaks out four lanes connected to P1 into a PCI Expressx1 cable connector and three downstream slots.
2.2 PCI Express Card Edge P1
The RDK form factor is based on the PCI Express CEM 1.1 specification. The board can directly plug into
the RDK Port Expander, which in turn provides a break out of the lower four lanes. All four lanes from the
The default configuration of the PEX 8505RDK sets Port 0 to be the upstream port.
2.3 PCI Express Connector J1
Connector J1 is a straddle-mount (SMT), x16 PCI Express connector. Cards plugging into this slot will be
in-line with the RDK. Port 1 connects one lane (x1) to the lower four lanes of connector J1. The upper
fifteen lanes are unconnected. Power is provided to connector J1 from the ATX hard disk connector J5.
2.4 Reference Clock Circuitry
Two Cypress CY28400-2 1-to-4 PCI Express clock buffers (U10 and U11) provide on-board REFCLK
distribution to the PEX 8505 and the downstream slot (J1). The first CY28400-2 (U11) input is sourced by
the card edge P1. U11 provides two differential CML (current mode logic) clock outputs. One pair drives
the PEX 8505’s PEX_REFCLKP/N input. This pair is AC-coupled (C74 and C75). This is required to block
the DC information of the transmitter from the PEX 8505 clock receiver, which has on-chip biasing and
termination circuitry. The other pair drives the input of a second CY28400-2 (U10), which is used drive the
downstream slot.
Figure 2-2. PEX 8505RDK Reference Clock Circuit
PEX 8505
PEX_REFCLK
CY28400-2
CY28400-2
RefClk
Card-Edge
RefClk

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 7
2.5 Reset Circuitry
The PEX 8505RDK reset circuitry includes a MAX6420 adjustable reset timer (U9) and manual reset
push-button switch (SW6). The reset timer accepts PERST# from the card edge (P1) and from SW6
(logical-OR via U8). The MAX6420 has the capability of adjusting the reset timeout period by changing
the value of C63 (0.001 µF ~= 3 ms).
2.6 Serial EEPROM
The PEX 8505RDK contains an 8-pin DIP socket for a serial EEPROM (U2). The board is populated with
a blank Atmel AT25080A 8-Kbit device. To use the serial EEPROM, place a shunt between pins 1 and 2
of JP2 (see section 3.4 for more details). The AT25080A device can directly interface to the PEX8505.
2.7 I2C Interface
The PEX 8505 implements an I2C slave interface, which allows an external I2C master to read and write
device registers through an out-of-band mechanism. The PEX 8505 I2C interface is accessible via a 7-bit
address, at data rates up to 400kbits/sec. The RDK provides two cascaded 2x2, 0.1” pitch headers (JP3
and JP4), which interface to the PEX 8505’s I2C port. This allows for cascading multiple RDKs together
using standard ribbon cable, or connecting various 3rd party I2C test equipment such as the Total Phase
Aardvark I2C controller.
Figure 2-3. I2C Connector Orientation for Aardvard I2C Controller
2.8 Power Distribution
2.8.1 Power Generation/Conversion
The PEX 8505RDK has two sources for DC power. The first source is the card edge connector (P1),
which gets it’s power from the RDK Port Expander. Card edge power is intended to power only RDK
board components. Slot J1 receives power via a 4-pin ATX hard disk connector (J5).
PEX8505 core and SerDes +1.0V supply is derived from the +3.3V rail through a Micrel MIC49150 LDO
regulator (U13). The PEX 8505’s +3.3V I/O supply receives power directly from the +3.3V card edge
power rail. The VTT supply for the PEX8505 PCI Express transmitters, is regulated from the +3.3V card
edge power via a Maxim MAX1806 adjustable LDO regulator (U14). The regulator output voltage is
normally set to +1.50V, but can be adjusted by changing the values of R98 and R102.
The ATX 4-pin connector provides +12V and +5V DC power. The +5V is converted down to +3.3V for slot
J1 through a Bel S7AH-08B330/-08E1A0 non-isolated DC/DC converter (U12). The +12V power rail is
used directly.
12
1
2
3
3
4
4
JP3
JP4

PEX 8505RDK Hardware Reference Manual v1.1
8 © 2007, PLX Technology, Inc. All rights reserved.
Figure 2-4. PEX 8505RDK Power Subsystem
2.8.2 Power Sequencing
The PEX 8505 device requires that the 1.0V power rails are supplied before the 1.5V and 3.3V rails are
powered. This power sequencing is accomplished via three bipolar transistors (Q3, Q4, Q6), biasing
resistors and one power MOSFET (Q5).
2.9 LED Indicators
The PEX 8505RDK provides a number of LED indicators including power-on indication, PEX 8505 lane
status indication, and Hot Plug status indication. Table 2-1 provides a quick explanation of the various
board indicators.
Table 2-1. PEX 8505RDK LED Indicator descriptions
Indicator
Type Locations LED On LED Off
Board Power
indication D16, D15, D17, D18 1.0V, 1.5V, 12V, 3.3V power on 1.0V, 1.5V, 12V,
3.3V power off
Slot J1 Power
Fault D14 +12V or +3.3V power to slot J1 had dropped below -15% on either supply.
+12V and +3.3V power
to slots J1 is good.
J5 Power
indication D20 ATX Hard disk connector is currently
supplying power
ATX hard disk
connector is not
supplying power
+12V +3.3V
PCI Express Card Edge
3.3V-to-1V
LDO Regulator
3.3V-to-
1.5V LDO
Pwr
Seq.
PEX_VTT
VDD10/VDD10S/VDD10A
VDD33/VDD33A
PEX 8505
ATX HD Conn.
5V-to-3.3V
DC/DC
+12V
+5V
+3.3V
ATX HD Conn.
5V-to-3.3V
DC/DC
+12V
+5V
+3.3V
PCI Express Connector
PCI Express Connector PCI Express Connector
RDK Port Expander
PCI Express Straddle Mount Connector
PCI Express Straddle Mount Connector

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 9
Indicator
Type Locations LED On LED Off
PEX 8505 Port
0 Lane Status D1 Port 0 link is up If LED is off, Port 0 link
is down
PEX 8505 Port
1 Lane Status D4 Port 1 link is up If LED is off, Port 1 link
is down
PEX 8505 Port
2 Lane Status D5 Port 2 link is up If LED is off, Port 2 link
is down
PEX 8505 Port
3 Lane Status D8 Port 3 link is up If LED is off, Port 3 link
is down
PEX 8505 Port
4 Lane Status D2 Port 4 link is up If LED is off, Port 4 link is down
PEX 8505
Fatal Error
Indication
D9 PEX 8505 detected a fatal error. No fatal errors reported
PEX 8505
INTA# D19 PEX 8505 has asserted sideband
interrupt Interrupt is not asserted

PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 11
3. On-Board Connectors, Switches, and Jumpers
3.1 DIP Switches
The PEX 8505RDK contains four user controllable DIP switches (SW1, SW2, SW3 and SW4) for
selecting various functionality. Each DIP switch position can be either ON (0b) or OFF (1b). The gray
squares in Figures 3-1 through 3-4 indicate which way the switch position is connected.
3.1.1 Upstream Port Selection (SW1)
Figure 3-1. Switch SW1 Default Settings
Table 3-1. Switch SW1 Description
SW1 Functional Description Switch Position Settings
STRAP_UPSTRM_PORTSEL [2:0]
Selects the PEX 8505 Upstream Port.
Default setting is 000b.
1: STRAP_UPSTRM_PORTSEL[0]
2: STRAP_UPSTRM_PORTSEL[1]
3: STRAP_UPSTRM_PORTSEL[2]
Bus Encodings [2:0] Upstream Port
000b 0
001b 1
010b 2
011b 3
100b 4
101b 5
110b 6
111b 7
3.1.2 PEX 8505 I2C Address Selection (SW2)
Switch SW2 is used to select the lower three address bits of the PEX 8505’s I2C slave address.
Figure 3-2. Switch SW2 Default Settings
SW1 ON
UP_PORT0
HIGH LOW
1
1
2
ON
2
3
3
UP_PORT1
UP_PORT2
SW2 ON
I2C_ADDR0
HIGH LOW
1
1
2
ON
2
3
3
I2C_ADDR1
I2C_ADDR2

PEX 8505RDK Hardware Reference Manual v1.1
12 © 2007, PLX Technology, Inc. All rights reserved.
Table 3-2. Switch SW2 Description
SW2 Functional Description Switch Position Settings
PEX 8505 I2C Address bits[2:0].
Default setting is 111b.
1: I2C_ADDR[0]
2: I2C_ADDR[1]
3: I2C_ADDR[2]
Bus Encodings [1:0] PEX 8505 I2C Slave Address
000b 38h
001b 39h
010b 3Ah
011b 3Bh
100b 3Ch
101b 3Dh
110b 3Eh
111b 3Fh
3.2 Push-Button Switches
3.2.1 Hot Plug Attention Button# (SW5)
Switch SW5 provides a push-button switch control for the PEX 8505 Hot Plug Controller’s
HP_BUTTON[3]# input pin. The PEX 8505 contains internal debounce circuitry for this input.
3.2.2 Manual Reset# (SW6)
The PEX 8505 RDK provides a manual PERST# capability. Note that manual PERST# will only apply
warm reset to the PEX 8505, and slot J1.
3.3 EEPROM Enable Jumper (JP5)
JP5 is used to enable an EEPROM presence detection to the PEX 8505. Install a shunt between pins 1 -
2 to indicate a Serial EEPROM is present. Un-install the shunt to indicate a Serial EEPROM is not present.
Table 3-3. Jumper JP2 settings
JP5 Setting EEPROM Status
Shunt installed (Default) Serial EEPROM present
Shunt not installed Serial EEPROM not present
3.4 JTAG Header (JP1)
Header JP1 provides a direct connection to the PEX 8505 JTAG interface. The 10-pin connector is
designed to allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E
controller.
3.5 PCI Express Fatal Error Indication (D9)
The PEX 8505 provides an output status pin (FATAL_ERR#), which reports the event of a PCI Express
fatal error condition. The RDK connects this output to D9, which is lit when a fatal error is detected.
Examples of fatal error conditions are data link layer protocol errors, receiver overflow, malformed TLPs,
etc… The PCI Express Base specification provides a complete listing of fatal error conditions.
3.6 PEX INTA# (D19)
PEX 8505 provides a side-band interrupt pin for signaling various programmable events.