PLX Technology PEX 8632-AA User manual

PEX 8632-AA Quick Start
Hardware Design Guide
Version 1.1
October, 2007
Website: www.plxtech.com
Support: www.plxtech.com/support
Phone: [phone]
408 774-9060
Fax: [phone]

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
iv © 2007 PLX Technology, Inc. All Rights Reserved.
© 2007 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX
Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX 8632-AA-SIL-DG-P1-1.1

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved. v
Contents
Preface ........................................................................................................................................................ vii
Notice ....................................................................................................................................................... vii
Revision History ....................................................................................................................................... vii
Introduction ................................................................................................................................................... 1
1Switch Interfaces.................................................................................................................................... 1
1.1 PCI Express Link Interface .............................................................................................................. 2
1.1.1 Transmitter ................................................................................................................................ 3
1.1.2 Receiver .................................................................................................................................... 5
1.1.2.1 Receiver Equalizer Registers – 8-Port Mode .................................................................. 5
1.1.2.2 Receiver Equalizer Registers – 12-Port Mode ................................................................ 5
1.1.3 Reference Clock........................................................................................................................ 6
1.1.4 Channel..................................................................................................................................... 7
1.2 NT Function ..................................................................................................................................... 8
1.3 Hot Plug Controller Interface ........................................................................................................... 9
1.4 JTAG Interface .............................................................................................................................. 11
1.5 I2C Interface ................................................................................................................................... 12
1.6 PCI Express Port Good Indicators................................................................................................. 12
1.6.1 PCI Express Port Good Indicators – 8-Port Mode .................................................................. 12
1.6.2 PCI Express Port Good Indicators – 12-Port Mode ................................................................ 12
1.7 Strapping Balls............................................................................................................................... 13
1.7.1 Strapping Balls – 8 Port Mode ................................................................................................ 13
1.7.2 Strapping Balls – 12 Port Mode .............................................................................................. 15
1.8 GPIO Balls..................................................................................................................................... 16
1.8.1 GPIO Balls – 8-Port Mode ...................................................................................................... 16
1.8.2 GPIO Balls – 12-Port Mode .................................................................................................... 16
1.9 Power Supplies, Sequencing, and De-Coupling ........................................................................... 17
1.9.1 Power Supplies ....................................................................................................................... 17
1.9.2 Power Sequencing .................................................................................................................. 18
1.9.3 Board-Level De-Coupling........................................................................................................ 19
2PCB Layout and Layer Stackup Considerations.................................................................................. 21
2.1 BGA Routing Escape and De-Coupling Capacitor Placement...................................................... 21
2.2 Add-In Board Routing .................................................................................................................... 23
2.3 System Board Routing................................................................................................................... 23
2.4 Midbus Routing.............................................................................................................................. 24
2.5 PCB Layer Stackup Considerations .............................................................................................. 24
3References........................................................................................................................................... 25

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
vi © 2007 PLX Technology, Inc. All Rights Reserved.
Figures
Figure 1. Sample PCI Express Link Block Diagram ..................................................................................... 2
Figure 2. Single-Ended versus Differential Voltage...................................................................................... 3
Figure 3. Transport Delay Delta ................................................................................................................... 7
Figure 4. PEX 8632 RefClk Circuitry ............................................................................................................ 7
Figure 5. Enable NT Function with NT Strapping Balls ................................................................................ 8
Figure 6. Disable NT Function with NT Strapping Balls ............................................................................... 8
Figure 7. PHPC Circuit Block Diagram......................................................................................................... 9
Figure 8. SHPC Interface to PEX 8632 Block Diagram.............................................................................. 10
Figure 9. JTAG Interface Block Diagram.................................................................................................... 11
Figure 10. I2C Interface Block Diagram ...................................................................................................... 12
Figure 11. Power Balls and Capacitor Placement...................................................................................... 17
Figure 12. Power Plane Impedance versus Frequency ............................................................................. 19
Figure 13. Capacitor Footprint Effects on Series Inductance.....................................................................20
Figure 14. Top Layer BGA Layout and Routing Escape ............................................................................ 22
Figure 15. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement ........................... 22
Figure 16. Add-In Board Routing to PCI Express Gold Fingers................................................................. 23
Figure 17. System Board Routing to PCI Express Slot .............................................................................. 23
Figure 18. PCI Express Midbus Routing Example ..................................................................................... 24
Tables
Table 1. Receiver Equalization Settings....................................................................................................... 5
Table 2. PEX 8632 LED On/Off Patterns, by State .................................................................................... 12
Table 3. Configuration Strapping Balls – 8-Port Mode ............................................................................... 13
Table 4. Active Lanes – 8- and 12-Port Modes .......................................................................................... 14
Table 5. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements – 8-Port Mode .. 14
Table 6. Configuration Strapping Balls – 12-Port Mode ............................................................................. 15
Table 7. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements – 12-Port Mode 16

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved. vii
Preface
Notice
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8632, or for
any damage or loss caused by deletion of data as a result of malfunction or repair.
Revision History
Date Version Comments
September 27, 2007 1.0 Initial release.
October 16, 2007 1.1
Reorganized document structure.
Split “Strapping Balls” section into 8- and 12-Port mode
specific text, updated the Configuration signal names,
and added new STRAP_RESERVED tables. Renumbered
existing tables accordingly.
Applied miscellaneous corrections and enhancements.

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
viii © 2007 PLX Technology, Inc. All Rights Reserved.
THIS PAGE INTENTIONALLY LEFT BLANK.

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved. 1
Introduction
This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8632
PCI Express Switch and provides examples of how to connect to the various switch interfaces.
1Switch Interfaces
The PEX 8632 device is a 32-Lane, 8- or 12-Port Gen2 switch, designed for high-availability and
high-performance systems. Its signal interface is grouped into the following functional blocks:
PCI Express Link interface
NT function
Hot Plug Controller interface
JTAG interface
I2C interface
PCI Express Port Good indicators
Strapping balls
GPIO balls
Power supply

1.1 PCI Express Link Interface
PLX’s PEX 8632 is a 32-Lane, 8- or 12-Port PCI Express 2.0 (that is, Gen2)-compliant switch. PCI
Express 2.0 supports transfer rates of 5.0 GT/s per Lane. The Physical Media Attachment (PMA) Layer
for each Lane is implemented as a SerDes transceiver, which is composed of a transmit path and receive
path. The transmit path typically contains a serializer, Phase Lock Loop (PLL), and Current Mode Logic
(CML) driver. The receive path consists of a CML Receiver buffer, Clock and Data Recovery circuit (CDR),
and a de-serializer.
Note: The PEX 8632 can be operated in 8- or 12-Port mode. For complete details, refer to the PEX 8632
Data Book.
As the PCI Express Base Specification, Revision 2.0, continues to mature, so does its description of the
Physical Layer Electrical sub-block. A PCI Express serial Link is described in terms of four components –
Transmitter, Receiver, Reference Clock, and Channel. The Transmitter and Receiver elements are
typically integrated into PCI Express silicon. The Channel and Reference Clock are implemented at the
system level. The PCI Express interoperability matrix implies that all four elements must support 5.0 GT/s
for the Link to successfully run at 5.0 GT/s. If any one element is not 5.0 GT/s-compliant, the Link will not
be able to operate beyond 2.5 GT/s. Another important concept is that 2.5 GT/s is not a subset of
5.0 GT/s. This implies that a design targeted to meet 5.0 GT/s might not successfully run in a 2.5 GT/s
environment, if those design criteria are not met, as well.
Figure 1 illustrates a block diagram of a sample PCI Express Link.
PLL1
CDR1 PLL2
CDR2
RefClk
Rx1
Rx2Tx1
Tx2
Channel
Channel
Device 1 Device 2
Figure 1. Sample PCI Express Link Block Diagram
PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
2 © 2007 PLX Technology, Inc. All Rights Reserved.

1.1.1 Transmitter
A PCI Express Transmitter is typically a differential CML driver that transmits an 8b/10b encoded
bitstream across the Channel to the Receiver. The minimum differential voltage swing (VTX-DIFF-PP) of the
Transmitter is 800 mV at both 2.5 GT/s and 5.0 GT/s. The DC common mode voltage can be anywhere
between 0 and 3.6V; hence, AC-coupling capacitors are required to isolate the Transmitter’s
DC component from the Receiver’s fixed 0V DC common mode voltage. The AC-coupling capacitor
values must range between 75 and 200 nF, to ensure that the lower frequency components of the 8b/10b
encoded data are not affected. Figure 2 illustrates what a generic PCI Express differential signal looks
like, as compared to a single-ended signal.
Note: The swing values listed in Figure 2 (400 mV and 800 mV) do not reflect default PLX register values.
PCI Express Transmitters are required to support de-emphasis. The role of de-emphasis is to increase
the resultant signal energy of the highest data frequencies and to counteract the frequency-dependent
Channel losses. De-emphasis does this by reducing the amount of energy used to transmit multiple
successive bits of the same polarity (that is, non-transition bits), compared to the amount of energy used
to transmit a set of transition bits (0 -> 1 or 1 -> 0). Transition bits have higher frequency components
than non-transition bits and are, therefore, more distorted by the low-pass Channel. This effect is one
aspect of Inter-Symbol Interference (ISI), which is a source of deterministic jitter in the system.
The PCI Express Base Specification, Revision 2.0, defines two de-emphasis levels for devices running at
5.0 GT/s, 3.0 to 4.0 dB and 5.5 to 6.5 dB. The desired de-emphasis level for a given Link is advertised by
the downstream Ports of a switch during Link recovery. Endpoints and the upstream device capture this
value and set their de-emphasis levels, accordingly. Longer Links should use 6.0 dB, whereas shorter
Links can use 3.5 dB.
The standard de-emphasis level is selectable by way of the PEX 8632 Link Control 2 register Selectable
De-Emphasis bit (Configuration register, offset 98h[6]).
TXp
PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved. 3
TXn
VTX-DC-CM
TXp - TXn
400mV
800mV
0V
Figure 2. Single-Ended versus Differential Voltage

PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
4 © 2007 PLX Technology, Inc. All Rights Reserved.
In addition to supporting the standard de-emphasis levels, the PEX 8632 has a number of programmable
registers to control the Transmitter’s characteristics, such as drive level and de-emphasis.
8-Port mode – The SerDes Transmitter Control registers exist in Station Ports 0 and 4, each
controlling a bank of 16 SerDes (Lanes [0-15] and [16-31], respectively).
12-Port mode – The SerDes Transmitter Control registers exist in Station Ports 0, 4, and 8.
Ports 0 and 4 each control a bank of 12 SerDes (Port 0 – Lanes [0-9, 12, 13]; Port 4 –
Lanes [16-25, 28, 29]). Port 8 controls a bank of 10 SerDes (Lanes [32, 33, 36, 37, 40, 41,
44, 45]).
Registers at offsets B84h to B90h are the SerDes Drive Level registers. Registers at offsets B94h to
BA0h are the Post-Cursor Emphasis Level registers. The SerDes Drive Level and Post-Cursor
Emphasis Level registers work in conjunction, to determine the transition and non-transition bits driver
swing and de-emphasis ratio. The PLX driver is implemented as a two-tap driver. When transition bits are
transmitted, the SerDes Drive Level and Post-Cursor Emphasis Level register levels are added
together; for non-transition bits, the two values are subtracted. Using Equation 1, Example 1 presents a
calculation of what the drive level and de-emphasis level would be for a given set of register values.
Systems with short Links and/or power-sensitive applications (such as mobile platforms) can optionally
decide to use low-swing output drive levels (40 0 mVP-P). In the PEX 8632, this can be accomplished by
setting the SerDes Drive Level register for a specific Lane to 01000b (400 mVP-P), and the Post-Cursor
Emphasis Level register to 00000b (no de-emphasis).
Equation 1. PEX 8632 Transmitter Drive Level
(a) VTRANS = VDRV_LVL + VPOST_EMP
(b) VNON-TRANS = VDRV_LVL - VPOST_EMP
(c) VTX-DE-RATIO-3.5DB = 20 log (VPOST_EMP/ VDRV_LVL)
Example 1. Setting for Lane 0 Transmitter to 3.5 dB
Port 0 SerDes Drive Level register, offset B84h[4:0] = 01111b (750 mVpp)
Port 0 Post-Cursor Emphasis Level register, offset B94h[4:0] = 01101b (162.5 mVpp)
VTRANS = 750 mV + 162.5 mV = 912.5 mVpp
VNON-TRANS = 750 mV - 162.5 mV = 587.5 mVpp
VTX-DE-RATIO-3.5 DB = 20 log (587.5/912.5) = -3.82 dB