PLX Technology USB3382-AIC Rapid Quick user guide

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 1 of 34 06Aug12, version 1.3
PLX Technology
Hardware Reference Manual
USB3382-AIC Rapid Development Kit

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 2 of 34 06Aug12, version 1.3
Preface
Notice
This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied
nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify
and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products.
PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The
information in this document is subject to change without notice. Although every effort has been made to ensure the
accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with
the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or
loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the
RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
About This Manual
This document describes the PLX USB3382-AIC RDK, a Rapid Development Kit, from a hardware perspective. It
contains a description of all major functional circuit blocks on the board and also is a reference for the creation of
software for this product. This manual also includes complete schematics and bill of materials.

Revision History
Date Version Comments
August
2011 1.0 Initial Release
October
2011 1.1 Correction on table 10 jumper setting.
November
2011 1.2 Added self powered mode jumper setting diagram.
August
2012 1.3 Modified for Rev 003 board jumper change. Corrected dipswitch low and high definition. Added ordering information.

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 3 of 34 06Aug12, version 1.3
Table of Contents
1GENERAL INFORMATION..........................................................................................................6
1.1USB3382 Features....................................................................................................................................................8
1.2USB3382 AIC RDK Features .................................................................................................................................9
1.3Getting Started.......................................................................................................................................................10
2USB3382 RDK HARDWARE ARCHITECTURE........................................................................13
2.1Architecture Block Diagram.................................................................................................................................13
2.2Board Components................................................................................................................................................14
2.3USB 3382 PCI Express to USB Client Bridge.....................................................................................................15
2.4PCI Express Upstream Port Connection.............................................................................................................15
2.5PCI Express Downstream Port Connections.......................................................................................................16
2.6USB Connection.....................................................................................................................................................16
2.7Clock Circuitry......................................................................................................................................................16
2.8Hardware Strap Pin Dipswitches.........................................................................................................................16
2.9Dipswitch Setting Tables.......................................................................................................................................17
2.10Serial EEPROM Interface.................................................................................................................................19
2.11JTAG Interface ..................................................................................................................................................20
2.12I2C/SMBUS Interface........................................................................................................................................20
2.138051 Debug port.................................................................................................................................................21
2.14FATAL_ERR#, INTA# and GPIO LEDs .......................................................................................................21
2.15Reference Clock Circuitry.................................................................................................................................22
2.16Reset Circuitry ...................................................................................................................................................22
2.17Port Status Indicator LEDs...............................................................................................................................22
2.18Hardware Strap Pins.........................................................................................................................................23

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 4 of 34 06Aug12, version 1.3
2.19Power Circuitry..................................................................................................................................................23
2.20PCIe Protocol Debug .........................................................................................................................................24
2.21WAKE# and Vaux Support ..............................................................................................................................24
3RDK CONFIGURATIONS ..........................................................................................................25
3.1x1x1 Add-In Card Strap Pin Setting....................................................................................................................25
3.2x2 Add-In Card Strap Pin Setting........................................................................................................................26
3.3x1x1 Root Complex Mode Strap Pin Setting.......................................................................................................27
3.4x2 Root Complex Mode Dipswitch Setting..........................................................................................................28
3.5Configuration Modules .........................................................................................................................................29
3.6Jumper Configurations.........................................................................................................................................29
4APPENDIX .................................................................................................................................33
4.1Board Revision Notes ............................................................................................................................................33

Figures
Figure1.USB3382 RDK Front View_________________________________________________________________________7
Figure2.GettingStarted‐AddinCardMode_____________________________________________________________________10
Figure3.GettingStarted–RootComplexMode,SelfPowered______________________________________________________11
Figure4.GettingStarted‐RootComplexMode,BusPowered_______________________________________________________12
Figure5.RDKArchitecture__________________________________________________________________________________13
Figure6.RDKComponentLocations___________________________________________________________________________15
Figure7:USB3.0StandardBPortCableandReceptacle__________________________________________________________16
Figure8.ConfigurationDipswitches___________________________________________________________________________17
Figure9.EEPROMinSocket_________________________________________________________________________________19
Figure10.PinAssignmentofJTAGPortHeader,JP1_____________________________________________________________20
Figure11.I2CPlugOrientation_______________________________________________________________________________20
Figure12.PinAssignmentofI2CConnectorJP2_________________________________________________________________21
Figure13:DB9MaleConnector______________________________________________________________________________21
Figure14.FatalError,INTA#andGPIOLEDs____________________________________________________________________21
Figure15.ManualPERST#button____________________________________________________________________________22
Figure16:24‐PinATXPowerConnector________________________________________________________________________23
Figure17:Midbus2.0ProbeFootprint_________________________________________________________________________24
Figure18.x1x1Add‐InCardDipswitchSetting__________________________________________________________________25
Figure19.x2Add‐InCardDipswitchSetting____________________________________________________________________26
Figure20.x1x1RootComplexModeDipswitchSetting___________________________________________________________27

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 5 of 34 06Aug12, version 1.3
Figure21.x2RootComplexModeDipswitchSetting______________________________________________________________28
Figure22:JumperSettingsforSystemPoweredMode____________________________________________________________30
Figure23:JumperSettingsforSelfPoweredMode_______________________________________________________________31
Figure24:JumperSettingsforBusPoweredMode_______________________________________________________________32
Figure25.RDKPartNumber_________________________________________________________________________________33
Figure26.JP9onRDKRev002_______________________________________________________________________________33
Figure27.JP9onRDKRev001_______________________________________________________________________________34

Tables
Table1.USB3382RDKConfigurations__________________________________________________________________________6
Table2.OrderingInformation________________________________________________________________________________6
Table3ComponentTable___________________________________________________________________________________14
Table4.SW1Functions_____________________________________________________________________________________17
Table5.SW2Functions_____________________________________________________________________________________18
Table6.SW3Functions_____________________________________________________________________________________18
Table7.SW4Functions_____________________________________________________________________________________19
Table8.PortIndicatorBlinkPattern__________________________________________________________________________22
Table9.USB3382StrapPortCfgSettings_______________________________________________________________________23
Table10.ConfigurationModuleDescription____________________________________________________________________29
Table11.PowerJumperSettings_____________________________________________________________________________29


USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 6 of 34 06Aug12, version 1.3
1GeneralInformation
TheUSB3382RDKisaPLXRapidDevelopmentKitintendedprimarilyforusebyPLXcustomersforsiliconevaluation
anddesignreference.TheformfactorisbasedonthePCIExpressCardElectromechanicalspecificationandcanbealso
usedasastandalonebaseboard.TheboardisdesignedtoworkbyeitherplugginginternallyintoaPCIExpress
compliantmotherboard,orexternallythroughaUSBportofthemotherboard.WhenpluggedinasaUSBdevice,it
canbepoweredexternallywithanATXpowersupply.Figure1showstheboardoutlineandcomponentplacement.

TheUSB3382RDKhas1x4upstreamportPCIegoldfinger,2x16PCIeslotsand1USB3.0TypeBSuperSpeedClient
Portconnector.Theupstreamedgeconnectorhasamaximumof2PCIeGen2laneselectricallyconnectedtoit.The
downstreamPCIeconnectorshave1or2PCIeGen2laneselectricallyconnectedtoitdependingonboard
configuration.
TheUSB3382RDKsupportstheuseofoneconfigurationmoduleslottoprovideflexibilityintheroutingoftwoPCIe
lanestoeitherax4PCIeedgeconnectorormultiplePCIeslots.TheConfigurationModulewillenabletheRDKto
supportthefollowingportconfigurations:
Table 1. USB3382 RDK Configurations
USB3382USB3.0
port
PCIeports
0hActivex1D,x1D
1hActivex2U
2hActivex1U,x1D
3hActivex2D

TheUSB3382RDKmeetstheROHSguidelinesforelectroniccomponents,andhardware.


Table 2. Ordering Information
Part NumberDescription
USB3382-AB-2U RDKUSB3382 (Rev-AB) Rapid Development Kit + CM107 (one x2 upstream port) 
USB3382-AB-1U1D RDKUSB3382 (Rev-AB) Rapid Development Kit + CM160 (one x1 upstream, one x1 downstream) 
USB3382-AB-1D RDK
USB3382 (Rev-AB) Rapid Development Kit + CM108 (two x1 downstream ports, Root
Complex Mode) 
USB3382-AB-2D RDK
USB3382 (Rev-AB) Rapid Development Kit + CM110 (one x2 downstream port, Root
Complex Mode) 



USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 7 of 34 06Aug12, version 1.3
Figure 1. USB3382 RDK Front View


USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 8 of 34 06Aug12, version 1.3
1.1 USB3382Features

•BridgesbetweenaPCIExpressinterfaceandUSBHost
•TwoPCIExpressx1Gen2Ports
oOperatesasaPCIExpressRootComplexorEndpoint
oPCIExpressswitchfunctionalityinEndpointmodeallowsoneupstreamPCIExpressPortandone
downstreamPCIExpressPort
•OneUSBr3.0SuperSpeedperipheralPort
•Four‐channelDMAScatter/GatherController
•Integrated8051Micro‐ControllerUnit(MCU)(referredtoherein,as8051)with32‐KBSRAMProgram/Data
memory
•USBSuperSpeed(5Gbps),High‐Speed(480Mbps),andFull‐Speed(12Mbps)modes
•USBAuto‐Enumeratemodes
•AutomaticRetryoffailedpackets
•MaximumPayloadSize–2,048bytes
•QualityofService(QoS)support
oAllPortssupportone,full‐featuredVirtualChannel(VC0)
oAllPortssupporteightTrafficClass(TC[7:0])mapping,independentlyoftheotherPorts
•4General‐PurposeInput/Output(GPIO)pinswithPulseWidthModulation(PWM)
•OtherPCIExpressCapabilities
oTransactionLayerPacket(TLP)Digestsupport
Poisonbit
End‐to‐endCyclicRedundancyCheck(ECRC)
oLanereversal
oPolarityreversal
oConventionalPCI‐compatibleLinkPowerManagementstates
L0,L0s,L1,L2/L3Ready,andL3(withVauxsupported)
oConventionalPCI‐compatibleDevicePowerManagementstates
D0andD3hot
D3cold(withVauxsupported)
oActiveStatePowerManagement(ASPM)
oDynamicLinkspeed(2.5or5.0GT/s)negotiation
oDynamicLinkwidthnegotiation
•Out‐of‐BandInitializationoptions
oSerialEEPROM
oI2CandSMBus(7‐bitSlaveaddresswith100Kbps)
•SerialEEPROMinterfaceforinitializingConfigurationregistersand8051firmware
•12‐MHzoscillatorwithinternalPhase‐LockedLoop(PLL)multiplier


USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 9 of 34 06Aug12, version 1.3
1.2 USB3382AICRDKFeatures
•USB3382‐AAPCIExpressGen2toUSB3.0SuperSpeedPeripheralController
•X4Upstreamgoldfinger
•TwodownstreamPCIExpressx16SlotConnectors
•DIPSwitchesforhardwareconfigurationofUSB3382
•SocketableSerialEEPROM
•Manualpush‐buttonPERST#capability
•I2C/SMBusheaderforOut‐of‐Bandregisteraccess
•JTAGheaderfortestability

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 10 of 34 06Aug12, version 1.3
1.3 GettingStarted

Figure 2. Getting Started-Addin Card Mode
FollowthefollowingstepstousetheRDKinAddincardmode.
1) PlugboardintoPCIExpressslotonmotherboard.
2) Checkandsetdipswitchesfordesiredportconfiguration.
3) Checkandinstalltheconfigurationmoduleforthedesiredmode.
4) CheckandsetthepowerjumpersforAddincardmodeoperation.
5) PluginaharddiskpowerconnectorintoJ2.Thisstepisnecessary;theRDKrequiresthe5Vsupplytopower
someoftheonboardcomponents.
6) PluginPCIExpressendpointintodownstreamslotsifneeded.
7) Afterallthesestepsarecompleted,systemcanbepoweredon.
8) PluginUSBdevicecableintheUSBStandardBconnector.

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 11 of 34 06Aug12, version 1.3
Figure 3. Getting Started –Root Complex Mode, Self Powered
FollowthefollowingstepstousetheRDKinAddincardmode.
1) Checkandsetdipswitchesfordesiredportconfiguration.
2) Checkandinstalltheconfigurationmoduleforthedesiredmode.
3) CheckandsetthepowerjumpersforSelfPoweredModeoperation.
4) PluginanATXpowersupply24pinconnectorpowerconnectorintoJ3.
5) PluginPCIExpressendpointintodownstreamslots.
6) Afterallthesestepsarecompleted,theATXpowersupplycanbepoweredon.
7) PluginUSBdevicecableintheUSBStandardBconnector.

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 12 of 34 06Aug12, version 1.3
1
2
3
5
4
Figure 4. Getting Started-Root Complex Mode, Bus Powered
FollowthefollowingstepstousetheRDKinRootComplexmode–BusPowered.
1) Checkandsetdipswitchesfordesiredportconfiguration.
2) Checkandinstalltheconfigurationmoduleforthedesiredmode.
3) CheckandsetthepowerjumpersforBusPoweredModeoperation.
4) PluginPCIExpressendpointintodownstreamslots.
5) PluginUSBdevicecableintheUSBStandardBconnector.

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 13 of 34 06Aug12, version 1.3
2USB3382RDKHardwareArchitecture
2.1 ArchitectureBlockDiagram


Figure 5. RDK Architecture

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 14 of 34 06Aug12, version 1.3
2.2 BoardComponents
(Refer to Figure 6. RDK Component Locations)

Table 3 Component Table
ComponentLocationComponentLocation
PCIExpressSlots(P4,P5)1PCIEGoldfinger(P3)10
Power‐onResetButton(S2)2VoltageIndicatorLEDs(D9,D10,D12,
D13,D14,D15,D17)
11
PERST#Button(S1)3ATXHardDiskConnector(J2)12
I2CConnector(JP2)4PowerConfigurationJumpers(JP3–
JP12)
13
EEPROMEnableJumper(JP4)524PinATXPowerConnector(J3)

14
EEPROMChipwithSocket(U2)6ConfigurationDipswitches(SW1‐SW4)15
JTAGconnector(JP1)7DSUB9Connector(P1)16
USBConnector(J1)8ConfigurationModuleSocket(P2)17
USB3382Chip(Chipnotinstalled
indiagram)(U1)
9



USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 15 of 34 06Aug12, version 1.3

Figure 6. RDK Component Locations

2.3 USB3382PCIExpresstoUSBClientBridge
TheUSB3382isaPCIExpressGen2toUSB3.0SuperSpeedClientBridge.Itfeatures2PCIexpressGen2x1portsand
1USB3.0SuperSpeedClientPort.Thedevicecomesina10x10mm2132leadpackage.

2.4 PCIExpressUpstreamPortConnection
Theupstreamx4connectorwillbeax1orx2linkconnectingtheUSB3382totheadd‐incardmaleedgeconnector.
TheUSB3382RDKcanplugintox1PCIExpressslotsbyusingaPCIExpresslaneconverter,suchasPCIExpressX4‐To‐X1
ConvertermadebyAdexElectronics.

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 16 of 34 06Aug12, version 1.3
2.5 PCIExpressDownstreamPortConnections
TheUSB3382RDKhas2x16typePCIerightangleconnectors.Configurationmodulescanconfigurethedownstream
slotsaseither1x2portor2x1downstreamports.
2.6 USBConnection
TheUSB3382RDKhas1USB3.0Standard‐Bhostreceptacle.TheStandard‐BreceptaclecanaccepteitheraUSB3.0
Standard‐BorUSB2.0Standard‐Bplug.
Figure 7: USB 3.0 Standard B Port Cable and Receptacle
2.7 ClockCircuitry
FortheAdapterModeconfiguration,theUSB3382RDKusesthePCIeRefClkprovidedatthemaleadd‐incardedge
connectorfortheUSB3382RefClkinputpins.AninternalclockbufferfansoutthisinputclocktotheRefClkoutput
pins,whichprovideRefClktothePCIeconnectors.

IntheRootComplexModeconfiguration,theRDKisnotconnectedtoaPCIeportonaPC.Inthiscase,anonboard
clockchipprovidesRefClktotheUSB3382device.Thisisuserselectablethroughadipswitchsetting.

TheUSB3382RDKalsohasa30MHzconstantfrequencyclocksourcefortheUSB3.0interface.AninternalPLLwill
generatemodulatedUSB3.0andUSB2.0requiredclocks.

2.8 HardwareStrapPinDipswitches
TheUSB3382hasanumberofstrappinswhichprovidethecapabilitytoperformvarioustypesofhardware
initializationwithouttheuseofEEPROM.Therearetwomaintypesofswitches.Theextendedactuatordipswitches
containthemainconfigurationdipswitchesandtherecessedswitchescontrolmoreadvancedandRESERVED
functions.

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 17 of 34 06Aug12, version 1.3

Figure 8. Configuration Dipswitches
2.9 DipswitchSettingTables
Dipswitchesaredesignedsuchthatthe“ON”stateselectsavalueof‘0’forthatswitch.
Table 4. SW1 Functions
SW1 Functional Description Switch Position Settings
PORTCFG0
UsedtoselecttheUSB3382’s
Portconfiguration.
L = x1 x1
H = X2
Default Setting = L
RC_MODE
RootComplexModeEnable
L = Adapter Mode
H = Root Complex Mode
Default Setting = L
SMBUS_EN#
System Management Bus
Enable
L = Enables SMBUS Mode
H = Enables I2C Mode
Default Setting = H
UPCFG_TIMER_EN#
Link Upconfigure Timer Enable
L =IfLinktrainingsequencefailsduringtheConfiguration
state,thenexttimetheLTSSMexitstheDetectstate,TS
Ordered‐Setsadvertiseonlythe2.5GT/s(Gen1)datarate
andnoAutonomousChangesupport.IfLinktraining

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 18 of 34 06Aug12, version 1.3
continuestofailwhentheLTSSMisintheConfiguration
state,theLTSSMcontinuestoalternatebetweenGen1and
Gen2advertisementeverytime
itexitstheDetectstate

H = TheDataRateIdentifiersymbolintheTSOrdered‐Sets
alwaysadvertisessupportforboththe5.0GT/s(Gen2)data
rateandAutonomousChange.
Default Setting = H

Table 5. SW2 Functions
SW2 Functional Description Switch Position Settings
TESTMODE[3:0]
FactoryTestonly
Default Setting = HLLL
CLKSEL
SelectsbetweenOnboard
RefClkandPCIEslotRefClk
L = Onboard RefClk
H = PCIE slot RefClk
Default Setting = H
I2CADDR[2:0]
I2C Lower Slave Address Bits
Usedtodefinethedefaultvalueofthethreeleastsignificant
bitsoftheUSB3382I2C/SMBus7‐bitSlaveaddress.

Default Setting = LLL

Table 6. SW3 Functions
SW3 Functional Description Switch Position Settings
PROBE_MODE#
FactoryTestOnly
Default Setting = H
SERDES_MODE_EN#
FactoryTestOnly
Default Setting = H
PLL_BYPASS#
FactoryTestOnly
Default Setting = H
FAST_BRINGUP#
FactoryTestOnly
Default Setting = H
DEBUG_SEL#

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 19 of 34 06Aug12, version 1.3
FactoryTestOnly Default Setting = H
LEGACY
USB Legacy Mode Select
L =TheUSB3382operateswithadvancedregistersand
endpoints.
H =theUSB3382’sUSBendpointsandregistersetare
backward‐compatibleforapplicationsthatrunontheNET
2282USBdeviceController.
Default Setting = L
SSC_CT#
SuperSpeedUSBCenter
SpreadClock
L=TheUSB3382’sUSBinterfacecansupportaUSBHostor
hubthatusesaCenter‐SpreadReferenceClock.

H=Center‐SpreadReferenceClockisnotsupported

DefaultSetting=H
DBGMODE
FactoryTestOnly
Default Setting = L
Table 7. SW4 Functions
SW3 Functional Description Switch Position Settings
DBG_PRBSEL[3:0]
FactoryTestOnly
Default Setting = HHHH
GPIO3PIN
FactoryTestOnly
Default Setting = H
2.10 SerialEEPROMInterface
TheUSB3382RDKprovidesasocketedSerialEEPROM.ThecontentsoftheserialEEPROMareusedtoinitializethe
USB3382afterpower‐onreset.TheRDKcontainsaMicrochip25AA128128KserialEEPROMdevice.Thereisajumper
JP4thatgivestheoptionofdisablingtheEEPROMbydisconnectingtheCS#pin.
NotetheEEPROMdeviceorientationasshownbelow.

Figure 9. EEPROM in Socket

USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 20 of 34 06Aug12, version 1.3
2.11 JTAGInterface
TheUSB3382RDKcontainsadedicated2x10JTAGheader(JP2).Thereisno“standard”JTAGheaderpinarrangement;
therefore,JTAGheadertypeandpinassignmentsaresomewhatarbitrary.Theheaderandpinassignmentchosenfor
thisboardiscompatiblewiththeScanworksUSB‐100JTAGcontroller).

GND
GND
GND
GND
Key
TDI
TRST
TMS
TDO
TCK
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
Figure 10. Pin Assignment of JTAG Port Header, JP1
2.12 I2C/SMBUSInterface
TheUSB3382providesatwo‐wireI2C/SMBuscompatibleslavemodeinterfacewiththreebitaddressing.Throughthis
out‐of‐bandchannel,theuserscanread,write,andconfiguretheUSB3382internalregisters,runinternaloutput
probemode,monitorerrorcounters,andmonitorstatusofallports.
TheUSB3382RDKprovidesa10pinI2Cheader(JP3).ThepinheaderincludediscompatiblewiththeAardvarkI2C/SPI
HostAdapterPartNumber:TP240141byTotalPhase.

Figure 11. I2C Plug Orientation