Quectel EC2 Series Instruction Manual

EC2x&EG2x-G Series
PCB Design Guideline
LTE Standard Module Series
Rev.Quectel_EC2x&EG2x-G_Series_PCB_Design_Guideline_V1.0
Date: 2020-07-23
Status: Released
www.quectel.com

LTE Standard Module Series
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About the Document
Revision History
Version
Date
Author
Description
1.0
2020-07-23
Lim PENG
Initial

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Contents
About the Document.................................................................................................................................. 2
Contents...................................................................................................................................................... 3
Table Index.................................................................................................................................................. 4
Figure Index................................................................................................................................................ 5
1Introduction......................................................................................................................................... 6
1.1. Applicable Modules.................................................................................................................... 6
1.2. Safety Information...................................................................................................................... 7
2PCB Design Overview ........................................................................................................................ 8
2.1. Footprint and Keepout Area....................................................................................................... 8
2.2. Design Priorities and Considerations for PCB Traces............................................................... 9
2.2.1. Design Priorities.............................................................................................................. 9
2.2.2. Design Considerations.................................................................................................... 9
3Interface Design................................................................................................................................ 10
3.1. Power Supply........................................................................................................................... 10
3.1.1. DC-DC Converter.......................................................................................................... 10
3.1.2. VBAT............................................................................................................................. 11
3.2. PWRKEY & RESET_N ............................................................................................................ 13
3.3. USB Interface........................................................................................................................... 14
3.3.1. USB_DM & USB_DP Signals ....................................................................................... 14
3.3.2. USB_VBUS Signal........................................................................................................ 16
3.4. Ethernet PHY........................................................................................................................... 17
3.4.1. SGMII Interface............................................................................................................. 17
3.4.2. Ethernet Components................................................................................................... 19
3.5. Audio Interfaces....................................................................................................................... 20
3.5.1. PCM Interface............................................................................................................... 20
3.5.2. Codec & Microphone & Speaker .................................................................................. 21
3.6. SD Card Interface .................................................................................................................... 23
3.7. WLAN Interface........................................................................................................................ 25
3.8. (U)SIM Interface....................................................................................................................... 27
3.9. ADC Interface........................................................................................................................... 28
3.10. GPIOs....................................................................................................................................... 29
3.11. Antenna Interfaces................................................................................................................... 30
3.11.1. PCB Structures of Microstrip And Coplanar Waveguide.............................................. 30
3.11.1.1. PCB Structure of Microstrip Waveguide............................................................ 30
3.11.1.2. PCB Structure of Coplanar Waveguide............................................................. 30
3.11.2. Reference Design of RF Layout.................................................................................... 32
3.11.3. PCB Layout Considerations of Coplanar Waveguide................................................... 33
4Thermal Design................................................................................................................................. 35
5Appendix References....................................................................................................................... 36

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Table Index
Table 1: Applicable Modules........................................................................................................................6
Table 2: Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB Structures
............................................................................................................................................................ 31
Table 3: Related Documents...................................................................................................................... 36
Table 4: Terms and Abbreviations.............................................................................................................36

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Figure Index
Figure 1: Overview of TE-A 1st Layer..........................................................................................................8
Figure 2: High-priority Signals to Be Designed (TE-A 1st Layer)................................................................ 9
Figure 3: DC-DC Converter (EVB 4th Layer) and Module Interfaces On TE-A (EVB 1st Layer)..............10
Figure 4: VBAT Traces (TE-A 1st Layer)...................................................................................................11
Figure 5: Traces of VBAT with Capacitors (TE-A 4th Layer).....................................................................11
Figure 6: Traces of VBAT with a TVS (TE-A 4th Layer)............................................................................12
Figure 7: VBAT & Sensitive Signal Traces (TE-A 1st Layer).....................................................................12
Figure 8: PWRKEY and RESET_N Traces (TE-A 1st Layer).................................................................... 13
Figure 9: PWRKEY and RESET_N Traces (TE-A 3rd Layer) ...................................................................13
Figure 10: Overview of USB_DM/DP Signal Traces (EVB 1st Layer).......................................................14
Figure 11: Overview of USB_DM/DP Signal Traces (EVB 3rd Layer) ...................................................... 15
Figure 12: Overview of USB_VBUS Signal Trace (EVB 1st Layer) ..........................................................16
Figure 13: Overview of USB_VBUS Signal Trace (EVB 3rd Layer)..........................................................16
Figure 14: Overview of SGMII Signal Traces (TE-A 1st Layer).................................................................17
Figure 15: Overview of SGMII Signal Traces (TE-A 3rd Layer)................................................................18
Figure 16: Recommended PCB Layout of SGMII Interface (TE-A 4th Layer)...........................................19
Figure 17: Recommended Reference PCB Layout of SGMII Interface (EVB 3rd Layer)..........................19
Figure 18: Layout of Recommended 4.7 μH Inductor, GND and Traces of AR8033 (EVB 1st Layer).....20
Figure 19: Overview of PCM Signal Traces (TE-A 3rd Layer)...................................................................21
Figure 20: Overview of Codec ALC5616 (EVB 1st Layer)......................................................................... 22
Figure 21: Overview of Analog Audio Signal Traces (EVB 1st Layer) ...................................................... 23
Figure 22: Overview of SD Card Signal Traces (EVB 1st Layer).............................................................24
Figure 23: Overview of SD Card Signal Traces (EVB 3rd Layer)............................................................. 24
Figure 24: Overview of SDIO Signal Traces (FC20 TE-A 1st Layer) ....................................................... 25
Figure 25: Overview of SDIO Signal Traces (FC20 TE-A 3rd Layer)....................................................... 26
Figure 26: Overview of (U)SIM Signal Traces (EVB 1st Layer)................................................................27
Figure 27: Overview of (U)SIM Signal Traces (EVB 2ndLayer)............................................................... 27
Figure 28: Overview of ADC Signal Traces (EVB 3rd Layer)...................................................................28
Figure 29: Overview of GPIO Signal Traces (TE-A without Copper Pouring)...........................................29
Figure 30: PCB Structure of Microstrip Waveguide...................................................................................30
Figure 31: PCB Structure of Coplanar Waveguide....................................................................................31
Figure 32: Microstrip Design on a 2-layer PCB ......................................................................................... 32
Figure 33: Coplanar Waveguide Design on a 2-layer PCB.......................................................................32
Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)....................33
Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)....................33
Figure 36: Overview of RF Traces (EVB 1st Layer)..................................................................................34
Figure 37: Overview of RF Traces (EVB 1st and 2nd Layers)..................................................................34

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1Introduction
This document mainly introduces the PCB reference design for Quectel LTE Standard EC2x&EG2x-G
series modules, and it takes EC25-TE-A, FC20-TE-A and UMTS&LTE EVB as examples.
1.1. Applicable Modules
Table 1: Applicable Modules
Module Series
Module
EC2x series
EC21 series
EC25 series
EC20 R2.1
EG2x-G
EG21-G
EG25-G

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1.2. Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating EC2x&EG2x-G series modules. Manufacturers of
the cellular terminal should notify users and operating personnel of the following safety information by
incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for
customers’ failure to comply with these precautions.
Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.
Wireless devices may cause interference on sensitive medical equipment, so
please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.
Cellular terminals or mobiles operating over radio signals and cellular network
cannot be guaranteed to connect in all possible conditions (for example, with
unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such
conditions, use emergency call. In order to make or receive a call, the cellular
terminal or mobile must be switched on in a service area with adequate cellular
signal strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as mobile phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders.

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2PCB Design Overview
2.1. Footprint and Keepout Area
A 4-layer PCB is strongly recommended.
First, check whether the module’s footprint is of the latest version provided by Quectel. For specific
footprint of each module, please refer to document [1],[2],[3] or [4].
Do not design pads 73–84 and do not route the keepout area with any traces or copper.
VABT
VABT Antenna
interfaces
Antenna
interfaces
WLAN
interface
WLAN
interface
SD card
interface
SD card
interface
USB
interface
USB
interface
SGMII
interface
SGMII
interface
Keepout
area
Keepout
area
Figure 1: Overview of TE-A 1st Layer

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2.2. Design Priorities and Considerations for PCB Traces
2.2.1. Design Priorities
Design priorities of PCB traces in order:
Antenna traces.
High-speed signal (SGMII, SDIO and USB) traces.
Power supply (VBAT_BB, VBAT_RF, USIM_VDD, SDIO_VDD, VDD_EXT) traces.
Other traces
2.2.2. Design Considerations
The radiation of PCM interface and power supply could affect RF performance, so keep them away
from RF signal traces and components.
Drill as fewer vias as possible for high-speed signal traces (SGMII, SDIO and USB interfaces) since
vias will affect the continuity of the impedance. Route the differential pair traces on the same layer.
To minimize the signal return path, the GND vias for signals such as USB, SDIO, SGMII, PWRKEY
and RESET_N should be close to the vias when the traces change layers.
VABT
VABT Antenna
Interfaces
Antenna
Interfaces
Other signals
(e.g. WLAN
interface)
Other signals
(e.g. WLAN
interface)
High-speed
signals
(SD card
interface)
High-speed
signals
(SD card
interface)
High-speed
signals
(USB
interface)
High-speed
signals
(USB
interface)
High-speed
signals
(SGMII
interface)
High-speed
signals
(SGMII
interface)
VDD_EXT
VDD_EXT USIM_VDD
USIM_VDD
Figure 2: High-priority Signals to Be Designed (TE-A 1st Layer)

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3Interface Design
3.1. Power Supply
3.1.1. DC-DC Converter
DC-DC converter should be away from the sensitive signal traces such as SDIO, USB, SGMII, audio
and RF. If possible, shield DC-DC converter with shielding cover and reserve spacing for shielding
frame.
Place the capacitor and inductor for the DC-DC converter as close as possible to the corresponding
pins of the DC-DC converter to minimize the loop area.
Place output capacitors near input capacitors to share common ground area on outer layers.
Provide adequate thermal relief area at the gound area on outer layers along with any additional
inner ground planes.
DC-DC
Converter
DC-DC
Converter
TE-A Interfaces
TE-A Interfaces
Figure 3: DC-DC Converter (EVB 4th Layer) and Module Interfaces On TE-A (EVB 1st Layer)

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3.1.2. VBAT
Place 100 μF, 100 nF, 33 pF and 10 pF capacitors for both VBAT_BB and VBAT_RF respectively.
The smaller the capacitance is, the closer the compositors are to the two VBAT pins.
The maximum current consumption of VBAT_RF is 1.8 A and its trace width is recommended to be
no less than 2 mm. The maximum current consumption of VABT_BB is 0.8 A and its trace width is
recommended to be no less than 1 mm. Moreover, please pay attention to the capability and quantity
of vias in the traces. The GND vias of the filter capacitors for VBAT should be drilled down to the
nearest main ground.
VBAT_RF
VBAT_RF
GND
GND
GND
GND
GND
GND
VBAT_BB
VBAT_BB
≥2 mm
≥2 mm
≥1 mm
≥1 mm
Vias
Vias
Figure 4: VBAT Traces (TE-A 1st Layer)
Capacitors
Vias
GND
GND
GND
Figure 5: Traces of VBAT with Capacitors (TE-A 4th Layer)

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TVS for VBAT should be placed close to module’s pin VBAT_BB and VBAT_RF.
VBAT traces should be away from sensitive signal traces such as SDIO, USB, SGMII, USB audio
and RF to avoid paralleling or crossing with them.
A layer with VBAT traces and reference ground plane is recommended. When a power plane is used,
a complete ground plane should be added in adjacent layer as the reference plane.
TVS
GND
Figure 6: Traces of VBAT with a TVS (TE-A 4th Layer)
VABT
VABT Antenna
Interfaces
Antenna
Interfaces
WLAN
interface
WLAN
interface
SD card
interface
SD card
interface
USB
interface
USB
interface
SGMII
interface
SGMII
interface
Keepout
area
Keepout
area
Figure 7: VBAT & Sensitive Signal Traces (TE-A 1st Layer)

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3.2. PWRKEY & RESET_N
PWRKEY and RESET_N signal traces are recommended to be surrounded with ground.
If filter capacitors for PWRKEY and RESET_N are required, put them near the two pins.
PWRKEY
GND
GND
RESET
Figure 8: PWRKEY and RESET_N Traces (TE-A 1st Layer)
PWRKEY
GND
GND
GND
RESET_N
Figure 9: PWRKEY and RESET_N Traces (TE-A 3rd Layer)

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3.3. USB Interface
3.3.1. USB_DM & USB_DP Signals
The spacing between USB_DP/USB_DM and other signal traces should be greater than 0.5 mm,
maintaining the integrity of the reference plane and avoiding crossing with signal lines on adjacent
layers.
USB_DP and USB_DM are recommended to be routed on the inner layer, with the differential
impedance controlled to 90 Ω. Keep the spacing and length between traces comparatively equal,
with the length tolerance less than 2 mm and the total length less than 120 mm.
When a TVS needs to be added for USB_DP and USB_DM signal traces, it should be close to USB
connector and the junction capacitance of the TVS should be less than 2 pF.
TE-A
interface
TE-A
interface
GND
GND
GND
GND
GND
GND
Test
points
Test
points
USB
connector
USB
connector
USB_DM/
DP
USB_DM/
DP
Figure 10: Overview of USB_DM/DP Signal Traces (EVB 1st Layer)

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USB_DM/DP
USB_DM/DP
GND
GND
GND
GND
GND
GND
Figure 11: Overview of USB_DM/DP Signal Traces (EVB 3rd Layer)

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3.3.2. USB_VBUS Signal
USB_VBUS is a USB detection signal, with maximum current of 1 mA. In general, a trace width of 0.1 mm
is sufficient.
TE-A
interface
TE-A
interface
GND
GND
GND
GND
GND
GND
Test
points
Test
points
USB
connector
USB
connector
USB_VBUS
USB_VBUS
Figure 12: Overview of USB_VBUS Signal Trace (EVB 1st Layer)
USB_VBUS
GND
GND
GND
Figure 13: Overview of USB_VBUS Signal Trace (EVB 3rd Layer)

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3.4. Ethernet PHY
3.4.1. SGMII Interface
Signal traces of SGMII_MCLK, SGMII_MDATA, EPHY_RST_N and EPHY_INT_N should be
surrounded with ground.
The spacing between SGMII_TX_M/SGMII_TX_P/SGMII_RX_M/SGMII_RX_P lines should be at
least 3 times wider than the traces, and that between the SGMII signal trace and other signal traces
should also be at least 3 times wider than SGMII traces.
Keep the maximum length of the SGMII signal traces less than 10 inches and the difference between
signals of the differential pairs (SGMII_TX_P and SGMII_TX_M, SGMII_RX_P and SGMII_RX_M)
less than 20 mil.
The differential impedance of SGMII signal traces is 100 Ω±10 %, and the reference ground of the
area should be complete.
The series capacitors for SGMII_TX_M/SGMII_TX_P should be close to PHY component, while the
series capacitors for SGMII_RX_M/SGMII_RX_P should be close to the two pins.
SGMII
interface
Figure 14: Overview of SGMII Signal Traces (TE-A 1st Layer)

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SGMII_RST
SGMII_INT
SGMII_DATA
SGMII_CLK
SGMII_TX_M
SGMII_TX_P
SGMII_RX_P
SGMII_RX_M
GND
GND
GND
GND
GND
Figure 15: Overview of SGMII Signal Traces (TE-A 3rd Layer)

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3.4.2. Ethernet Components
A four-layer PCB should be used when using the SGMII interface to implement the Ethernet function in
the application.
The first layer is for non-sensitive traces and 1.1 V power supply traces.
The second layer is strongly recommended for 3.3 V and 2.5 V power supply traces and ground
plane.
The third layer should be a reference ground.
The fourth layer is used for main signal traces.
Crystals
Crystals
Keepout area
Keepout area
AR8033
AR8033
SGMII signal
traces
SGMII signal
traces
GND
GND
GND
GND GND
GND GND
GND
GND
GND
Figure 16: Recommended PCB Layout of SGMII Interface (TE-A 4th Layer)
SGMII_INT_N
GND
GND
GND GND
GND
GND
SGMII_RST_N
SGMII_DATA
SGMII_CLK
Figure 17: Recommended Reference PCB Layout of SGMII Interface (EVB 3rd Layer)