Radio Shack TRS-80 User manual

FOR
RADIO SHACK SERVICE CENTERS
TRS-80 Technical Manual
Theory
Parts List
Schematics
CUSTOM MANUFACTURED IN U.S.A. BY RADIO SHACkHa DIVISION OF TANDY CORPORATION

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express permission, of editorial or pictorial con-
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information contained herein. While every pre-
caution has been taken in the preparation of this
book, the publisher assumes no responsibility
for errors or omissions. Neither is any liability
assumed for damages resulting from the use of
the information contained herein.
©Copyright 1978, Radio Shack,
ADivision of Tandy Corporation,
Fort Worth, Texas 76102, U.S.A.
Printed in the United States of America

TABLE OF CONTENTS
TITLE PAGE
INTRODUCTION 2
SYSTEM BLOCK DIAGRAM 2
THE MEMORY MAP 4
THEORY OF OPERATION 5
WAIT, INT*, TEST 6
CPU Address Lines 6
CPU Data Bus 6
CPU Control Group 7
Control Group Bus 7
Address Decoder 8
System RAM 11
Video Divider Chain 13
Video RAM Addressing 16
Alphanumeric Format 16
Video Processing 17
Keyboard 23
Input and Output Port 23
Cassette Motor Control 23
Cassette Audio Output 24
Cassette Audio Input 25
INSIG* 26
System Power Supply 27
Level II ROM's 28
PARTS LIST 30
SCHEMATICS 34

INTRODUCTION
"We've done so much, with so little, for so long, that now
we can do anything, with nothing, except weld the Crack of
Dawn and put wheels on aCarriage Return!"
Armed with only aschematic, attacking aTRS-80 com-
puter can be like trying to weld that crack. You may know
what "CPU" stands for. You may have the knowledge of
how amicroprocessor system works. So you grab the sche-
matic's book and attack that TRS-80 with soldering iron
smoking and adetermined gleam in your eye.
After awhile, you find you have problems. You know a4K
RAM needs 12 address lines. But you only found 7. You
know acomputer keyboard gives you ASCII. Yet, you
find the keyboard is shorting out an address line to adata
line. You know how aTV typewriter scrolls characters on
the screen, and you do find the video memory wired to do
the job. But where is all the hardware to make the display
scroll?
You know what aNAND gate symbol looks like and you
also know what an OR gate symbol looks like. But some
sadist has gotten all his symbols backwards. ANAND gate
is shown like an OR gate, and the OR gate looks like a
NAND gate. To top it all off, the power supply consists of
two large rectangles with transistors and resistors sticking
out of them; and the only voltages shown are the resulting
outputs. Welcome to the wonderful world of computer
electronics.
Now admit it. You don't really know your ASCII from a
scroll when it comes to the TRS-80 computer.
come back to the CPU. The address lines are outputs from
the CPU. They never receive data or addresses from other
sections. The data lines on the other hand can give or
receive data.
ROM
The ROM (Read Only Memory) could be considered the
brains, if the CPU has to be the heart, of the system. The
ROM tells the CPU what to do, how to do it and where to
put it after it's done. Without the ROM, the CPU would
just sit there and oscillate. When power is first applied to
the system, the CPU has just enough smarts to output an
address to the ROM that locates the CPU's first instruction.
The ROM shoots back the first instruction and then the
two really start communicating. In less than asecond, the
CPU, under ROM supervision, performs all the house-
keeping necessary to get the system alive and a"READY"
flashes on the screen;
If the CPU misses that first piece of ROM data, then it may
go bananas. It may tell the ROM that it is ready to load a
tape so the ROM tells it how to do that. The tape recorder
turns on. But since the CPU is now playing games in the
video memory, who cares about the tape? The CPU
operates at about 2MHz; therefore, digital screw-ups seem
instantaneous.
Remember that the CPU is the work horse and the ROM is
the boss. The ROM tells the CPU how to do it, when to do
it, and where to put it.
RAM
The purpose of this manual is to give you apractical
knowledge of system operation as it pertains to the
TRS-80. This manual will show you why there are only
seven address inputs to a4K RAM. You will be shown
when the microprocessor inputs data from the keyboard
the CPU thinks the keyboard is amemory, of all things!
You'll learn how the CRT screen is scrolled and you might
even learn to appreciate the backward symbolization. As far
as the power supply is concerned, you might find that it's
not nearly as complex as you thought. So, grab your sche-
matics and let's take atour of the TRS-80 computer.
SYSTEM BLOCK DIAGRAM
The 80 integrated circuits contained in the TRS-80 can be
broken down into about 10 major sections. Figure 1shows
these sections as they relate to other sections. The heart of
the system is definitely the CPU (Central Processing Unit).
You might consider the CPU as being avery dumb calcula-
tor circuit. It may be dumb, but it's afast dummy. Most of
the leads on the CPU are data lines and address lines. The
CPU tells the address bus where the data it wants is located,
and the data bus is agood place for the information to
The next major section in Figure 1is the RAM (Random
Access Memory). This memory is where the CPU may place
data it doesn't need until later. The RAM is also the place
where the programs are kept for use. If you tell the compu-
ter to count to 10,000, then the CPU stores your instruc-
tions in the RAM. If you tell the computer to do it NOW,
here is what happens:
The CPU tells the ROM someone wants in. The ROM tells
the CPU to go to the keyboard and find out who. The CPU
finds out, tells the ROM that it's the boss. The ROM tells
the CPU to find out what he wants. The CPU tells the ROM
that the boss wants US to RUN. The ROM tells the CPU to
go to RAM and find out what the boss wants done. The
CPU says the boss wants to count to 10,000. The ROM tells
the CPU how to do it. After it's done, the ROM tells the
CPU to find out what to do with it. The CPU informs the
ROM that the 10,000 has got to go on the display and must
be saved. The ROM tells the CPU how to put it on the dis-
play and then tells it to store the 10,000 somewhere in
RAM; but it had better remember where it is. The CPU tells
the ROM that the job is done. The ROM tells the CPU to
monitor the keyboard in case the boss wants something else.

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The CPU looks to the ROM for instructions. The CPU then
follows the ROM's instructions and looks to the keyboard,
then the RAM. In all cases, the CPU applies address loca-
tions to the ROM, RAM, and keyboard. The data lines are
then checked for input data that corresponds to these
address locations. In case of an output from CPU to RAM,
the CPU selects the address, puts data on the data lines,
then instructs the RAM to store the data that is on the data
lines.
Notice that only the CPU communicates with all other
sections. If the CPU is told by ROM to store something
from ROM into RAM, the CPU can't make the RAM
receive ROM data direct. Instead, the CPU takes the data
from ROM and then sends it to RAM. The CPU must act as
intermediary between the two. The reason for this is that
the CPU is the only section that can address locations and
pass data to all other sections.
KEYBOARD, VIDEO RAM,
VIDEO PROCESSING
The keyboard section is not necessary as far as the CPU is
concerned, but it is very necessary for the Operator. The
keyboard is our method of making known our instructions
to the CPU. The opposite is true for the video RAM. In this
case, the CPU wants to tell us it needs data or it may want
to show us the result of acomplex calculation. So, the
request for more information or the result is stuffed into
the video RAM. Anything in video RAM is automatically
displayed on the monitor. The video processing section
handles this. Data in the video RAM is in ASCII. Converting
ASCII into the alphanumeric symbols we recognize is the
job of the video processor. AROM contains all of the dot
patterns. The ASCII locates the character pattern, and the
video processor sends it out to the terminal.
VIDEO DIVIDER CHAIN
THE MEMORY MAP
Some customers call the Factory Customer Service Center
and ask "Which output port is the display?" These cus-
tomers are told that the TRS-80 does not use an output
port for the display. They are told that the TRS-80 is
memory-mapped. In amemory-mapped system an address
will define and select all other subsections.
Figure 2shows the memory map for aLevel ITRS-80.
From memory locations 0000 to 0FFF, the Level IROMS
are present. The keyboard is located from address 3800 to
380F. The video display is located from 3C00 to 3FFF.
The RAMs start at 4000 and, depending on how much
RAM is in the system, can extend down to address 7FFF.
HEX
ADDRESS DESCRIPTION OF CONTENTS/USAGE
0000
To
0FFF Level 1ROMS
1000
To
37FF Not used
3800
To
380 FKeyboard
3810
To
3BFF Not used
3C00
To
3FFF Video Display
4000
To
41FF
I
RAM Used by Basic Level 1J
K
1
MiK VM
4200
To
4FFF
fRAM
Useable RAM starts here»—^8
1
5000
To
5FFF RAM
6000
To
7FFF RAM
8000
To
FFFF Not used
NOTE: Mop not drawn to scale
Figure 2. Level IMemory Map
Composite video going to aterminal is extremely complex.
Aside from the video signal, there is the horizontal and
vertical sync. These signals must be very stable and be
outputted in the correct sequence. The CPU is busy enough
as it is, so the video divider chain handles the TV work. It
generates the sync signals and addresses the video RAM in a
logical order so that the video processor can handle video
data efficiently. Notice the block under the video RAM
labeled MUX. This is short for Multiplexer. It acts some-
what like amultipole, multiposition switch. When the
video divider chain is in control, the MUX is switched so
that only addresses from the divider chain are directed to
the video RAMS. The CPU may need to read or write data
into the video RAM. If so, the MUX is switched so that the
CPU has control over video RAM's address. After the CPU
is finished, the addressing task is reassigned to the divider
chain.
As stated before, upon power-on, an address location is out-
putted by the CPU requesting information from the ROMs.
Since the ROMs are located at addresses 0000 to 0FFF, the
CPU will be outputting addresses in this area. If the CPU
needs some kind of keyboard data, it will output addresses
3800 through 380F and see if anything is in this "memory"
location. If the CPU wants to show the programmer some-
thing on the display, all it has to do is address the video dis-
play section of the map and store data in these locations.
Something to remember: the video display shows exactly
what is in memory locations 3C00 through 3FFF.
Notice memory locations 4000 to 41 FF. At address 4000
RAM starts. But, part of the RAMs are used by Basic Ias
general housekeeping memory locations. Hence, the user
accessible RAM actually starts at address 4200.

THEORY OF OPERATION
System Clock
The system clock is shown on Sheet 2of the fold-out
schematics in the Schematic Section. Y1 is a10.6445 MHz,
fundamental cut, crystal. It is in aseries resonant circuit
consisting of two inverters. Z42, pins 1and 2, and 3and 4,
form two inverting amplifiers. Feedback between the
inverters is supplied by C43, a47 pF capacitor. R46 and
R52 force the inverters used in the oscillator to operate in
their linear region. The waveform at pin 5of Z42 will
resemble asine wave at 10.6445 MHz. The oscillator should
riot be measured at this point, however, due to the loading
effects test equipment would have at this node. Z42, pin 6,
is the output of the oscillator buffer. Clock measurements
may be made at this point. The output of the buffer is
applied to three main sections: the CPU timing circuit, the
video divider chain, and the video processing circuit.
CPU Timing
The Z80 microprocessor needs asingle phase clock source
for. operation. The 10 MHz signal from system clock is
applied to Z56, astandard ripple counter, which is used as a
divide-by-6 counter. The resulting signal at Z56, pin 8, is a
little over 1.774 MHz. The signal is applied to the input of
buffer Z72, pin 12. Pin 11 of Z72 is attached to pin 6of
the Z80 microprocessor. R64 pulls up pin 11 of Z72, and
insures arapidly increasing rise time for the clock signal.
Notice that pin 15 of Z72 is tied to ground. Since pin 15 is
the enable input to this part of Z72, pin 12 and 11 will
always be active. Notice also pins 7and 6of Z56. These
two pins enable the clear function for the counter. When
one or both of these pins is low, the counter operates nor-
mally. When high, the input forces the counter into its clear
or reset state. Z42, pins 9and 8, are used to disable counter
Z56 during automatic testing at the factory. R67 pulls
Z42's input to VrjC. which causes pin 8to stay at alogical
low. During testing, pin 9of Z42 may be pulled low, mak-
ing pin 8high, which disables and clears Z56. You might
also find early Board levels (A Boards for example) where
pins 6and 7of Z56 are tied directly to ground.
Power-Up-Clear and System Reset
Alow at this input forces the microprocessor to output the
starting address 0000 on its 16 address lines. When C42
charges up past about 1.4 volts, Z53, pin 11, goes low,
which causes Z52, pin 10, to go high. The CPU is now out
of its reset state, and will start executing instructions from
the ROM, starting at address 0000. Notice that the only
time pin 26 of the CPU is ever low is afew milliseconds
after power is applied. Once C42 charges up past the logical
ONE level, pin 26 stays high until C42 is discharged when
power is removed. Why is Z53, aNAND gate, drawn like
an OR gate? Notice that pin 11is high only when either of
the inputs are low. The NOT circles at the input immedi-
ately tell you that this gate is looking for asignal that is low
to cause an output that is high. Had the gate been drawn
"correctly", then it would not have been so obvious that
the output is active when high. This "functional" type of
logical symbolization is used throughout the schematics.
Directly above the power-up circuit, there is asimilar cir-
cuit. S2 is the reset switch located on the right side of the
Board. Although there is apower-on-delay type circuit on
the input of this network, it is not used as such. Notice that
C57 is smaller than C42. Hence, in apower-up "race", C57
would charge up faster than C42. Assume that C57 is
charged. Also assume that pin 2 of Z53 is high. This means
that Z53, pin 3, will be low and Z37, pin 13, will be high.
With pin 17 of the CPU held high, everybody is happy. If
S2 is pressed, C57 will discharge through the switch. The
resulting low is applied to pin 1of Z53 and pin 3goes high.
Z37, pin 13, is then forced low. Alow at pin 17of the CPU
forces the microprocessor to restart at address 0066. When
S2 is released, R65 begins to charge C57 until alogical high
is applied to pin 1of Z53. At this time, pin 17 of the CPU
goes back high and the CPU starts executing instructions
from address 0066 in the ROMs.
S2 is used to get the microprocessor back on the right road
when it is "lost". This switch forces the CPU toward a
known address to enable it to get on the right track. An
example of alost CPU would be during abad cassette load
attempt. If acassette is loading and suddenly there is
missing information on the tape (caused by dirt or age), the
recorder may never stop. S2 can then be pressed, which
directs the CPU out of the cassette load routine and back
into its ready mode.
As mentioned in the block diagram discussion, upon power-
on the CPU accesses aknown address in the ROM for
instructions. The circuitry which causes the starting address
output is shown just below the microprocessor clock
divider. Z53 is a2-input, quad NAND gate. (Note that Z53
is drawn like an inverted input OR gate.) When power is
first applied to the system, C42 is at volts. R47 is tied to
Vcc ar| dstarts charging C4 at aknown rate. While C4 is
charging, and before the voltage exceeds the logical 1level
for Z53, pin 11 outputs ahigh. This high is inverted by
Z52, pins 1 1 and 10, and alow is applied to pin 26 of Z40.
The output at pin 18 of Z40 is called "Halt". In Level I
BASIC, this output should never be low. It goes low only
when asoftware halt instruction is encountered by Z40. In
theory, this instruction is not included in the ROMs. But
you might find pin 18 held low because Z40 thought it was
told to halt. It could be due to some data malfunction, or
the CPU is lost and is playing around with display data
instead of ROM data. In acase like this, S2 is not effective
in bringing the CPU home, because Z53 is latched up.
About all you can do is shut the computer down and try
again.

Notice that Z53, pin 11and pin 3, are also tied to Z37, pins
2and 3. Z37, pin 1, is an output line labeled SYSRES*
(System Reset Not). It is normally-high and only goes low
during power up (Z53, pin 11, causes this), or when S2 is
pressed (Z53 pin 3, causes this). SYSRES* is used by the
expansion interface and is not used by the TRS-80 in
BASIC I.
One last thing to mention about these two circuits: When
you turn off power to the TRS-80 because of alost CPU,
wait at least 10 seconds before you reapply power. If you
do not wait, C42 may not discharge all the way and the
CPU may not go back to address 0000 during arestart. By
waiting, C42 will discharge and upon power-up, the system
will start at the correct ROM location.
WAIT, INT*, TEST
These three inputs to the CPU are pulled up to Vcc
through resistors. Since they are active low, you may not
have any use for them. But you should know what they are
for.
The WAIT input, pin 24 of Z40, will slow the CPU down if
there are slow memories it must access. If this line goes low,
the CPU will go into await status until it goes back high.
Once high, the CPU continues with the operation. For
example: Assume you have amemory system that takes
100 microseconds before addressed data can be guaranteed
to be present at the output. When the memory logic sees
that the CPU wants data, it will make the WAIT line low.
At the end of 100 microseconds time, the logic will make
the WAIT pin high, and the CPU will input the data.
The INT (Interrupt Request) is at pin 16 of Z40. This input
when low, will force the CPU into an interrupt request
section of the memory. It would then perform some
instruction associated with the interrupt. An example of
this use would be as follows: Assume there was adoor on
the back of the TRS-80 that should always be closed. There
was aswitch connected to the door such that when opened,
the switch contacts are shorted. The switch would be con-
nected to ground and to pin 16 of Z40. If the door were
opened, the computer would stop what it was doing and
print on the screen "Close Door." The CPU would be inter-
rupted, and it would henpeck you until you closed that
door! As you can see, pin 16 is tied to V(X through aresis-
tor and is not used. It is, however, used with the TRS-80
Expansion Interface.
The TEST input may be quite useful in your troubleshoot-
ing. Pin 25 of Z40 is labeled BUSRQ (Bus Request). When
this pin is brought low, it will force the data, the address
and the control lines into the disabled or floating state.
Although it is not used by the TRS-80 in normal operation,
it is quite useful when someone wants to "shut down the
CPU". We'll talk about this input when we discuss the
Control Logic Group.
CPU ADDRESS LINES
There are system outputs of the microprocessor labeled A0
through A15 that start the address bus. Since these lines
must go to ROM, RAM, the keyboard and the video RAM,
they must be buffered for two reasons. First, the buffers
must be able to supply the address bus with proper logical
levels. The microprocessor cannot supply the current neces-
sary to drive all of the sections connected to the address
bus, and buffers are needed for current gain. Secondly, it
may be necessary to switch off the address bus. For exam-
ple, if an Expansion Interface is connected to the bus, it
may be necessary to address RAM in the main unit for a
data transfer. Therefore, there must be some method to
take the CPU off the data bus. The buffers are tri-state
devices. This means they will either act as buffers or as
opened switches.
Z38, Z39 and part of Z22 and Z55 are the address line
buffers. Notice that in Z38 and Z39 there are two sections
of buffers. The first section contains four buffers and the
second section contains only two buffers. Each section is
controlled by asingle pin. The first is controlled by pin 1
and the second by pin 15. When these control pins are at a
logical low, the buffers are enabled and will operate normal-
ly. When the control pin is at alogical high, the buffers are
disabled, and will show ahigh impedance from input to
output. The signal that controls the address buffers is
labeled "ENABLE*" and is sourced at Z52, pin 4. Pin 3is
the input for control line inverter, Z52, and is tied to the
TEST* line. Notice that R58 keeps this line pulled high.
Hence, the address buffers' control line will alwavs be at a
logical low; and therefore, operating as buffers. If TEST*
is shorted to ground, the address buffers will be disabled.
This feature could be very useful in troubleshooting.
CPU DATA BUS
The data bus is buffered like the address bus, except for
one area. Notice that there are only eight data lines at the
CPU, labeled D0 through D7. But there are 16 buffers.
Remember that the CPU must receive data as well as send
data. The address lines are strictly CPU outputs, while the
data lines are inputs and outputs. Therefore, there must be
two sets of buffers for the data line. One set handles CPU
output data while the other set takes care of the CPU input
data.
The output data buffers consist of all of Z75 and one
section of Z76. The input buffers consist of one section of
Z55 and the last section of Z76. Notice that the input and
output buffers are connected "head to toe". This could
cause problems if both were on at the same time! The con-
trol inputs to the output buffers are all connected together
on the line labeled DBOUT*, and are in turn tied to Z53,
pin 6. Likewise, the input buffers' controls are tied together
on the line labeled 'DBIN*, and are connected to Z53, pin
8. DBOUT*, is tied to pins 9and 10 of Z53, the gate which
generates DBIN*.
6

As you can see, Z53, pin 6, is the major source of input or
output data control. If pin 6is high, DBOUT* is high and
DBIN* is low. Therefore, the input buffers are enabled and
the output buffers are disabled. If Z53, pin 6, is low,
DBOUT* is low and DBIN* is high. In this case, the output
buffers are enabled and the input buffers are off.
Pin 4of Z53 is tied to TEST*. If TEST* is grounded, not
only will we disable the address buffers, but we will also
cause pin 6of Z53 to go high. Hence, the data output
buffers will be off, robbing the CPU's control over the data
lines. Since DBIN* is now held low, the input data buffers
would be active. But, this would not cause any problem
since the address bus from the CPU has been disabled.
When TEST* is left alone, it is held high. If pin 21 of
the CPU (the Memory Read output) is high, Z53, pin 6, will
be low. The low causes DBOUT* to be low and DBIN* to
be high. Therefore, the CPU is outputting data; and the
buffers are switched accordingly. When pin 21 of Z40 goes
low, Z53, pin 6, will be high. We now have almost the same
condition as if TEST* went low. DBOUT* is high and
DBIN* is low but the address buffers are still enabled. The
data buffers arp now ready for the CPU to accept data.
CPU CONTROL GROUP
OK, we now know how the CPU accesses the address bus.
We know the data bus is used to gather data into the CPU
or pass data out of the CPU. What we do not know at this
point is how the CPU stores data in amemory or how it
tells the ROM or RAM that it is ready to receive data. The
CPU control group performs this task. These signals are:
RD,WR,OUT, and IN.
RD (Read)
RD is Read control. This signal, when activated, will tell
other sections that the CPU is ready to accept data. RD is
generated at Z23, pin 6. Pin 5is connected to pin 21 of
Z40, th eRD (Read) output. Pin 4of Z23 is tied to pin 19,
MREQ (Memory Request), of the CPU. Therefore, when
pins 19 and 21 of Z40 go low at the same time, an RD out-
put is generated. Notice the backward symbol for an OR
gate. It's drawn like an AND gate. When we get MREQ
and RD, then and only then will we get RD. We're looking
for two lows on the input for alow output.
WR (Write)
WR is Write control. This signal, when activated, will tell
other sections that the CPU is ready to write data into one
of the memory locations. WR is generated at Z23, pin 11.
Pin 12 of Z23 is connected to MREQ. Pin 13 of Z23 is
tied to WR (Memory Write), which is pin 22 of Z40. When
we get alow at the MREQ output and alow at the WR out-
put, then and only then will we get alow at WR.
OUT (Output)
OUT is Output control. This signal, when activated, will
enable circuitry to perform the cassette save functions. It
would also be used to control data movement from the
TRS-80 to the Expansion Interface. OUT is generated at
Z23, pin 3. Pin 1of Z23 is tied to the WR output on the
CPU. Pin 2 of Z23 is tied to IORQ (Input/Output Request)
which is pin 20 of the CPU. When we get alow at WR and
alow at IORQ, then and only then will we get alow at
OUT.
IN (Input)
IN is Input control. This signal, when activated will enable
circuitry to perform the cassette load function. It would
also be used to control data movement from the Expansion
Interface to the TRS-80. IN is generated at Z23, pin 8. Pin
10 of Z23 is connected to IORQ. Pin 9ofZ23 is tied to
RD. When we get alow at RD and alow at IORQ, then and
only then will we get alow at IN.
CONTROL GROUP BUS
The Control Group must be buffered for use by the dif-
ferent sections. Also, the bus may need to be switched off
at some time. Therefore, part of Z22 is used to buffer the
Control Group. Tri-State control at pin 1is tied to the
address bus control, and ENABLE* will affect the status of
the address and the control group bus in the same manner.

ADDRESS DECODER
As shown in Figure 2, the TRS-80 is memory mapped.
Therefore, the address 01AC (in HEX) is in the ROM part
of the map. Address 380A is in the keyboard area and
3CAA accesses the video display RAMs. Since the data and
address buses are connected in parallel to all the sections,
there must be some method to determine which section is
being accessed. Adecoding network monitors the higher
order address bits and selects which "memory" the CPU
wants to use. The address decoder is so important to the
operation of the system that it has been redrawn in Figure
3. Keep your schematic handy since there are signals shown
in Figure 3that need to be sourced or traced.
The address decoder uses six bits. A10 through A15 are
needed plus RD* and RAS* (RAM Address Select). A1 5is
the most significant bit of the address bus. Let's combine
the six high order bits and add acouple more, so that we
have two hex digits:
A15 A14 A13 A12 A11 A10 A9 A8
A12 through A15 form the most significant hex character.
A8 through A1 1form the next most significant hex charac-
ter. A8 and A9 are the two bits we had to add to complete
that last hex character. Now let's break down part of the
memory map into hex and binary.
A15 A14 A13 A12 A11
From: Hex 0000 00000
To: Hex0FFF 1
From: Hex 3800 111
To: Hex380F 111
From: Hex 3C00 111
A10
To: Hex3FFF 11
From: Hex 1
1
From: Hex 4000 10
To: Hex4FFF 10 1
To: Hex 7FFF 1111
1
1
1
1
A9 A8
11
1 1
11
11
Level IROMs
Keyboard
Display RAMS
4K RAM
16K RAM
Notice in the breakdown that we could use the two most
significant digits of the hex code in the decoding scheme
and handle the selection of all the memories. In the binary
columns, you can see that instead of using two hex digits,
which is eight binary lines, we can ignore two bits and use
only six binary lines. Adotted line separates the two
unused bits from the six that we'll use.
Looking at Figure 3, you'll see that bits A12, A13 and A14
are connected to Z21, adual, 2-input to 4-line decoder/
demultiplexer. The C1 and C2 inputs are connected in such
away as to make Z21 into a3-input to 8-line decoder. The
G1 and G2 inputs to Z21 are chip enables. As shown, when
these inputs are at a logical 0, Z21 is active. When high, Z21
is disabled and none of its eight outputs are low. The G
enables are controlled by OR gate Z73, pins 4, 5, and 6. Pin
4is tied to A1 5, the most significant bit of the address bus.
Notice in the memory map breakdown that A15 is always
low when addressing the various memories. Z73, pin 5, is
tied to RAS* (Row Address Select). Go back to the big
schematic. Sheet 1,and find I
stated earlier.
IREQatpin 19 of the CPU. As
1REQ only goes low when the CPU needs or
wants to output memory data. Follow pin 19 down to Z72,
pin 4. This buffer sources RAS* and it is the same signal as
MREQ. Back to Figure 3. When A15and RAS* are low at
the same time, alow will be outputted by Z73, pin 6. This
low will enable Z21. When Z21 turns on, one of its outputs
will go low, depending on the status of A12, A13 and A14.
For example, if these three inputs are at logical zero, pin 9
will go low. If all three inputs are high, pin 4will go low.
You might consider A12 through A14 as supplying an octal
address to Z21. Since there are eight states in an octal code,
then there could be one of eight lines selected (Output
through Output 7).
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