Sino Wealth SH79F3283 User manual

SH79F3283
Enhanced 8051 Microcontroller with 12bit ADC
1 V2.0
1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 32K Bytes
RAM: internal 256 Bytes, external 1280 Bytes, LCD
RAM: 28 Bytes
EEPROM-like: 1024 Bytes
Operation Voltage:
fOSC = 32.768kHz - 16MHz, VDD = 2.0V - 5.5V
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 16MHz
- Ceramic oscillator: 2MHz - 16MHz
- Internal RC: 12MHz (±2%)/128K
46/42/30 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Four 16-bit timer/counters: T2, T3, T4 and T5
One 12-bit PWM
One 8-bit PWM
Powerful interrupt sources:
- Timer2, 3, 4, 5
- INT0, 1, 2, 3
- INT40 - INT47
- ADC, EUART, SCM, LPD
- PWM, SPI
EUART0, EUART1 (No EUART1 in 32 PIN package)
SPI Interface (Master/Slave Mode)
Buzzer
9 channels 12-bits Analog Digital Converter
(ADC), with comparator function built-in
LED driver:
- 3-8 X 8 dots (1/3 - 1/8 duty)
LCD driver:
- 8 X 24 dots (1/8 duty, 1/4 bias)
- 6 X 26 dots (1/6 duty, 1/4 or 1/3 bias)
- 5 X 27 dots (1/5 duty, 1/3 bias)
- 4 X 28 dots (1/4 duty, 1/3 bias)
Low Voltage Reset (LVR) function (enabled by
code option)
- LVR voltage level 1: 4.1V
- LVR voltage level 2: 3.7V
- LVR voltage level 3: 2.8V
- LVR voltage level 4: 2.1V
CRC verify module built-in, check size is optional
Support SWE simulation, write and read
CPU Machine cycle: 1 oscillator clock
Watch Dog Timer (WDT)
Warm-up Timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package: TQFP48/LQFP44/LQFP32
2. General Description
The SH79F3283 is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch
structure, that helps the SH79F3283 can perform more fast operation speed and higher calculation performance, if compare
SH79F3283 with standard 8051 at same clock speed.
The SH79F3283 retains most features of the standard 8051. These features include internal 256 bytes RAM, UART and INT0,
INT1, INT2 and INT3. In addition, the SH79F3283 provides external 1280 bytes RAM, Four 16-bit timer/counters T2-T5. It also
contains 32K bytes Flash memory block both for program and data.
Also the ADC, EUART, SPI, LCD Driver, PWM timer and CRC module functions are incorporated in SH79F3283.
For high reliability and low power consumption, the SH79F3283 builds in Watchdog Timer, Low Voltage Reset function and
SCM function. And SH79F3283 also supports two power saving modes to reduce power consumption.

SH79F3283
2
3. Block Diagram
32K Bytes
Flash ROM
Internal 256 Bytes
External 1280Bytes
(Exclude System
Register)
Oscillator
Pipelined 8051 architecture
Timer2 (16bit)
Timer3 (16bit)
Timer4 (16bit)
Timer5(16bit)
Reset circuit RST
XTAL2
XTAL1
VDD
External Interrupt
Buzzer
Power
Watch Dog
oscillator fail
detector
12-bit PWM
8 bit PWM
Internal
Oscillator
Port 3
Configuration I/Os
Port 4
Configuration I/Os
P1.0 ~ P1.7
P2.0 ~ P2.7
P0.0 ~ P0.7
Port 2
Configuration I/Os
P3.0~ P3.7
EUART0/1
12-bit ADC
Jtag ports
(for debug)
Port 5
Configuration I/Os
LCD/LED Driver COM1~8
SEG1~28
Port 1
Configuration I/Os
P4.0~ P4.7
Port 0
Configuration I/Os
P5.0~P5.5
Oscillator X
XTALX2
XTALX1
SPI
Frequency Detect
2 X COMPARATOR
CRC

SH79F3283
3
4. Pin Configuration
4.1 TQFP48
P4.1/INT41/AN1
PWM01A/SEG19/P0.2
P4.4/AN8/AVREF
P4.0/INT40/AN0
P3.6/COM7/LED_C7/SGE26/AN6
P4.2/INT42/AN2
P4.3/INT43/AN3
P3.3/COM4/LED_C4
Vss
25
24
23
32 31 30 29 28 27 26
1 2 3 4 5 6 7 8 9 10 11
33
12
13
14
15
16
17
18
19
22
21
20
44
43
42
41
40
39
38
37
45
3536
P3.2/COM3/LED_C3
P3.7/COM8/LED_C8/SGE25/AN7
P3.4/COM5/LED_C5/SGE28/AN4 P3.0/COM1/LED_C1 P3.1/COM2/LED_C2
P1.0/SEG1/LED_S1/INT44/TDO/SWE
P1.4/SEG5/LED_S5
P1.3/SEG4/LED_S4/INT47/TCK P1.2/SEG3/LED_S3/INT46/TDI
P1.1/SEG2/LED_S2/INT45/TMS
P1.5/SEG6/LED_S6
LED_S7/SEG7/P1.6
MOSI/RXD1/SEG11/P2.2
TXD0/SEG10/P2.1
RXD0/SEG9/P2.0
MISO/TXD1/SEG12/P2.3
PWM01C/SEG15/P2.6
FLT/SS/SEG14/P2.5
SCK/SEG13/P2.4
PWM0C/SEG16/P2.7
PWM01B/SEG17/P0.0
PWM0B/SEG18/P0.1
PWM0A/T4/P0.3
T2EX/INT0/P0.4
XTALX1/INT3/P0.7
XTAL2/P5.1
T2/INT1/P0.5
XTALX2/INT2/P0.6
RST/P5.2
XTAL1/P5.0
P3.5/COM6/LED_C6/SGE27/AN5
SH79F3283U
P4.5/SEG24/PWM1
34
46
47
48
P4.7/SEG22
LED_S8/SEG8/P1.7
P4.6/SEG23
BUZ/T3/P5.3
VDD
P5.4/SEG20
P5.5/SEG21
Pin Configuration Diagram TQFP48
Note:
The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin
Configuration Diagram. This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the
lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by
software, can the corresponding pin be released for the lower priority function to use.

SH79F3283
4
4.2 LQFP44
P4.1/INT41/AN1
PWM01A/SEG19/P0.2
BUZ/T3/P5.3
P4.4/AN8/AVREF
P4.0/INT40/AN0
P3.6/COM7/LED_C7/SGE26/AN6
P4.2/INT42/AN2
P4.3/INT43/AN3
P3.3/COM4/LED_C4
LED_S8/SEG8/P1.7
Vss
25 24 2332 31 30 29 28 27 26
1 2 3 4 5 6 7 8 9 10 11
33
12
13
14
15
16
17
18
19
22
21
20
44
43
42
41
40
39
38
37
34
35
36
VDD
P3.2/COM3/LED_C3
P3.7/COM8/LED_C8/SGE25/AN7
P3.4/COM5/LED_C5/SEG28/AN4
P3.0/COM1/LED_C1
P3.1/COM2/LED_C2
P1.0/SEG1/LED_S1/INT44/TDO/SWE
P1.4/SEG5/LED_S5
P1.3/SEG4/LED_S4/INT47/TCK
P1.2/SEG3/LED_S3/INT46/TDI P1.1/SEG2/LED_S2/INT45/TMS
P1.5/SEG6/LED_S6 P1.6/SEG7/LED_S7
MOSI/RXD1/SEG11/P2.2
TXD0/SEG10/P2.1
RXD0/SEG9/P2.0
MISO/TXD1/SEG12/P2.3
PWM01C/SEG15/P2.6
FLT/SS/SEG14/P2.5
SCK/SEG13/P2.4
PWM0C/SEG16/P2.7
PWM01B/SEG17/P0.0
PWM0B/SEG18/P0.1
PWM0A/T4/P0.3
T2EX/INT0/P0.4
XTALX1/INT3/P0.7
XTAL2/P5.1
T2/INT1/P0.5
XTALX2/INT2/P0.6
RST/P5.2
XTAL1/P5.0
P3.5/COM6/LED_C6/SGE27/AN5
SH79F3283P
P4.5/SEG24/PWM1
Pin Configuration Diagram LQFP44
Note:
The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin
Configuration Diagram. This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the
lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by
software, can the corresponding pin be released for the lower priority function to use.

SH79F3283
5
4.3 LQFP32
P4.1/INT41/AN1
BUZ/T3/P5.3
P4.4/AN8/AVREF
P4.0/INT40/AN0
P4.2/INT42/AN2
P4.3/INT43/AN3
VSS
VDD
XTALX1/INT3/P0.7
XTAL2/P5.1
XTALX2/INT2/P0.6
XTAL1/P5.0
SH79F3283P
24 23 17181922 21 20
1 2 3 4 5 6 7 8
12
13
14
15
16
9
10
11
25
32
31
30
29
28
27
26
RST/P5.2
P3.7/COM8/LED_C8/SGE25/AN7
P3.6/COM7/LED_C7/SGE26/AN6
P3.5/COM6/LED_C6/SGE27/AN5
P3.4/COM5/LED_C5/SGE28/AN4
P3.0/COM1/LED_C1
P3.1/COM2/LED_C2
P3.2/COM3/LED_C3 P3.3/COM4/LED_C4
P1.0/SEG1/LED_S1/INT44/TDO/SWE
P1.1/SEG2/LED_S2/INT45/TMS
P1.2/SEG3/LED_S3/INT46/TDI
TCK/INT47/LED_S4/SEG4/P1.3
LED_S5/SEG5/P1.4
RXD0/SEG9/P2.0
TXD0/SEG10/P2.1
FLT/SEG14/P2.5
PWM01C/SEG15/P2.6
PWM01A/SEG19/P0.2
PWM0A/T4/P0.3
Pin Configuration Diagram LQFP32
Note:
The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin
Configuration Diagram. This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the
lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by
software, can the corresponding pin be released for the lower priority function to use.

SH79F3283
6
Table 4.1 Pin Function
Pin No.
(TQFP48) Pin No. (LQFP44) Pin No. (LQFP32) Pin Name Default Function
1 1 31 PWM01A/SEG19/P0.2 P0.2
2 2 32 PWM0A/T4/P0.3 P0.3
*3 *3 - T2EX/INT0/P0.4 P0.4
*4 *4 - T2/INT1/P0.5 P0.5
5 5 1 XTALX2/INT2/P0.6 P0.6
6 6 2 XTALX1/INT3/P0.7 P0.7
7 7 3 VSS ----
8 8 4 XTAL1/P5.0 ----
9 9 5 XTAL2/P5.1 ----
10 10 6 RST
————/P5.2 RST ————
11 11 7 BUZ/T3/P5.3 P5.3
12 12 8 VDD ----
13 - - SEG20/P5.4 P5.4
14 - - SEG21/P5.5 P5.5
15 - - SEG22/P4.7 P4.7
16 - - SEG23/P4.6 P4.6
17 13 - PWM1/SEG24/P4.5 P4.5
18 14 9 AVREF/AN8/P4.4 P4.4
19 15 10 AN3/INT43/P4.3 P4.3
20 16 11 AN2/INT42/P4.2 P4.2
21 17 12 AN1/INT41/P4.1 P4.1
22 18 13 AN0/INT40/P4.0 P4.0
23 19 14 AN7/SEG25/LED_C8/COM8/P3.7 P3.7
24 20 15 AN6/SEG26/LED_C7/COM7/P3.6 P3.6
25 21 16 AN5/SEG27/LED_C6/COM6/P3.5 P3.5
26 22 17 AN4/SEG28/LED_C5/COM5/P3.4 P3.4
27 23 18 LED_C4/COM4/P3.3 P3.3
28 24 19 LED_C3/COM3/P3.2 P3.2
29 25 20 LED_C2/COM2/P3.1 P3.1
30 26 21 LED_C1/COM1/P3.0 P3.0
31 27 22 INT44/LED_S1/SEG1/P1.0 P1.0
32 28 23 INT45/LED_S2/SEG2/P1.1 P1.1
33 29 24 INT46/LED_S3/SEG3/P1.2 P1.2
34 30 25 INT47/LED_S4/SEG4/P1.3 P1.3
35 31 26 LED_S5/SEG5/P1.4 P1.4
36 32 - LED_S6/SEG6/P1.5 P1.5
(to be continued)

SH79F3283
7
(continue)
Pin No.
(TQFP48) Pin No. (LQFP44) Pin No. (LQFP32) Pin Name Default Function
37 33 - LED_S7/SEG7/P1.6 P1.6
38 34 - LED_S8/SEG8/P1.7 P1.7
39 35 27 RXD0/SEG9/P2.0 P2.0
40 36 28 TXD0/SEG10/P2.1 P2.1
41 37 - MOSI/RXD1/SEG11/P2.2 P2.2
42 38 - MISO/TXD1/SEG12/P2.3 P2.3
43 39 - SCK/SEG13/P2.4 P2.4
44 40 29 FLT/SS/SEG14/P2.5 P2.5
45 41 30 PWM01C/SEG15/P2.6 P2.6
46 42 - PWM0C/SEG16/ P2.7 P2.7
47 43 - PWM01B/SEG17/P0.0 P0.0
48 44 - PWM0B/SEG18/P0.1 P0.1
* Note: P0.4, P0.5 are configured as N-channel open drain IO.

SH79F3283
8
5. Pin Description
Pin No. Type Description
I/O PORT
P0.0 - P0.7 I/O 8 bit General purpose CMOS I/O
P1.0 - P1.7 I/O 8 bit General purpose CMOS I/O
P2.0 - P2.7 I/O 8 bit General purpose CMOS I/O
P3.0 - P3.7 I/O 8 bit General purpose CMOS I/O
P4.0 - P4.7 I/O 8 bit General purpose CMOS I/O
P5.0 - P5.5 I/O 6 bit General purpose CMOS I/O
Timer
T2 I/O Timer2 external input/baud rate clock output
T3 I Timer3 external input
T4 I/O Timer4 external input/output
T2EX I Timer2 Reload/Capture/Direction Control
PWM
PWM0A/0B/0C O Output pin for 12-bit PWM0 timer
PWM01A/01B/01C O Output pin for 12-bit PWM0 timer with fixed phase relationship of PWM0
FLT I PWM0 Fault Detect input
PWM1 O Output pin for 8-bit PWM1 timer
EUART
RXD0/1 I EUART0/1 data input
TXD0/1 O EUART0/1 data output
SPI
MOSI I/O SPI Master output Slave input
MISO I/O SPI Master input Slave output
SCK I/O SPI serial clock
SS
——— I SPI Slave Select
ADC
AN0 - AN7 I ADC input channel
AVREF I External ADC reference voltage input
LCD
COM1 - COM8 O Common signal output for LCD display
SEG1 - SEG28 O Segment signal output for LCD display
LED
LED_C1 - LED_C8 O Common signal output for LCD display
LED_S1 - LED_S8 O Segment signal output for LCD display
(to be continued)

SH79F3283
9
(continue)
Interrupt & Reset & Clock & Power
INT0 - INT3 I External interrupt 0-3 input source
INT40 - INT47 I External interrupt 40-47 input source
RST
———— I The device will be reset by a low voltage on this pin longer than 10us, an internal
resistor about 30kΩ to VDD, So using only an external capacitor to GND can cause a
power-on reset.
XTAL1 I Oscillator input
XTAL2 O Oscillator output
XTALX1 I Oscillator X input
XTALX2 O Oscillator X output
VSS P Ground
VDD P Power supply (2.0 - 5.5V)
Buzzer
BUZ O Buzzer output pin
Programmer
TDO (P1.0) O Debug interface: Test data out
TMS (P1.1) I Debug interface: Test mode select
TDI (P1.2) I Debug interface: Test data in
TCK (P1.3) I Debug interface: Test clock in
SWE (P1.0) I/O Single simulation interface. If the power on or down slope of VDD is greater than
500ms/V, it is recommended to connect 47k-1m resistor to GND or VDD to increase
the stability of the chip
Note: When P1.0-1.3 used as debug interface, functions of P1.0-1.3 are blocked.

SH79F3283
10
6. SFR Mapping
The SH79F3283 provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function Register
(SFR). The SFR of the SH79F3283 fall into the following categories:
CPU Core Registers: ACC, B, PSW, SP, DPL, DPH
Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE
Power and Clock Control Registers: PCON, SUSLO
Flash Registers: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4, IB_CON5
Data Memory Register: XPAGE
Hardware Watchdog Timer Registers: RSTSTAT
System Clock Control Register: CLKCON, SCMCON
Interrupt System Registers: IEN0, IEN1, IENC, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1, EXCON
I/O Port Registers: P0, P1, P2, P3, P4, P5, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P0PCR,
P1PCR, P2PCR, P3PCR, P4PCR, P5PCR, P0OS
Timer Registers: TCON, T2CON, T2MOD, TH2, TL2, RCAP2L, RCAP2H, T3CON, TH3, TL3,
T4CON, TH4, TL4, SWTHL, T5CON, TH5, TL5
EUART Registers: SCON, SBUF, SADEN, SADDR, PCON, SCON1, SBUF1, SADEN1,
SADDR1, SBRTL, SBRTH, BFINE
SPI Registers: SPCON, SPSTA, SPDAT
ADC Registers: ADCON, ADT, ADCH, ADDL, ADDH, ADCON1
LCD Registers: DISPCON, DISPCON1, DISPCLK0, P0SS, P1SS, P2SS, P3SS
LED Registers: DISPCON, DISPCLK0, P1SS, P3SS
BUZZER Registers: BUZCON
PWM Registers: PWMEN, PWMEN1, PWM0C, PWM0PL, PWM0PH, PWM0DL, PWM0DH,
PWM1C, PWM1P, PWM1D
LPD Registers: LPDCON
CRC Registers: CRCCON, CRCDL, CRCDH

SH79F3283
11
Table 6.1 CPU Core SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ACC E0H Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
B F0H B Register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
AUXC F1H C Register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0
PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P
SP 81H Stack Pointer 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
DPL 82H Data Pointer Low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0
DPH 83H Data Pointer High byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0
DPL1 84H Data Pointer 1 Low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPH1 85H Data Pointer 1 High byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
INSCON 86H Data pointer select -0--00-0 - BKS0 - - DIV MUL - DPS
Table 6.2 Power and Clock control SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON 87H Power Control 000-0000 SMOD SSTAT SSTAT1 - GF1 GF0 PD IDL
SUSLO 8EH Suspend Mode Control 00000000 SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0

SH79F3283
12
Table 6.3 Flash control SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_OFF
SET FBH
Bank0
Low byte offset of flash memory
for programming 00000000 IB_OFF SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0
IB_DATA FCH
Bank0
Data Register for programming
flash memory 00000000 IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
IB_CON1 F2H
Bank0
Flash Memory Control Register 1 00000000 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0
IB_CON2 F3H
Bank0
Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0
IB_CON3 F4H
Bank0
Flash Memory Control Register 3 ----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0
IB_CON4 F5H
Bank0
Flash Memory Control Register 4 ----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0
IB_CON5 F6H
Bank0
Flash Memory Control Register 5 ----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
XPAGE F7H
Bank0
Memory Page -0000000 - XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
FLASHCON
A7H
Bank0
Flash access control -------0 - - - - - - - FAC
Table 6.4 WDT SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTSTAT B1H
Bank0
Watchdog Timer Control 0-000000* WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
*Note: RSTSTAT initial value is determined by different RESET.
Table 6.5 CLKCON SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKCON B2H
Bank0
System Clock Control Register 111000-- 32k_
SPDUP CLKS1 CLKS0 SCMIF HFON FS - -
SCMCON A1H
Bank0
SCM Clock Control Register -----011 - - - - - SCK2 SCK1 SCK0

SH79F3283
13
Table 6.6 Interrupt SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN0 A8H
Bank0
Interrupt Enable Control 0 00000000 EA EADC ET2 ES ECMP EX1 ET5 EX0
IEN1 A9H
Bank0
Interrupt Enable Control 1 00000000 ESCM_LPD
_CRC ET4 EPWM ET3_ES1 EX4 EX3 EX2 ESPI
IENC BAH
Bank0
Interrupt 4channel enable control 00000000 EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40
IENC1 BBH
Bank0
Interrupt channel enable control 1 -0000000 - ECRC ES1 ET3 ECMP1 ECMP2 ESCM ELPD
IPH0 B4H
Bank0
Interrupt Priority Control High 0 -0000000 - PADCH PT2H PSH PCMPH PX1H PT5H PX0H
IPL0 B8H
Bank0
Interrupt Priority Control Low 0 -0000000 - PADCL PT2L PSL PCMPL PX1L PT5L PX0L
IPH1 B5H
Bank0
Interrupt Priority Control High 1 00000000 PSCMH PT4H PPWMH PT3S1H PX4H PX3H PX2H PSPIH
IPL1 B9H
Bank0
Interrupt Priority Control Low 1 00000000 PSCML PT4L PPWML PT3S1L PX4L PX3L PX2L PSPIL
EXF0 E8H
Bank0
External interrupt Control 0 00000000 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 IE3 IE2
EXF1 D8H
Bank0
External interrupt Control 1 00000000 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40
EXCON 8BH
Bank0
External interrupt Sample Control 00000000 I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0

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Table 6.7 Port SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0 80H
Bank0
8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1
90H
Bank0
8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2
A0H
Bank0
8-bit Port 2 00000000 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P3 B0H
Bank0
8-bit Port 3 00000000 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P4 C0H
Bank0
8-bit Port 4 00000000 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
P5 80H
Bank1
6-bit Port 5 --000000 - - P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
P0CR E1H
Bank0
Port0 input/output direction control 00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR E2H
Bank0
Port1 input/output direction control 00000000 P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
P2CR
E3H
Bank0
Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR
E4H
Bank0
Port3 input/output direction control 00000000 P3CR.7 P3CR.6 P3CR.5 P3CR.4 P3CR.3 P3CR.2 P3CR.1 P3CR.0
P4CR E5H
Bank0
Port4 input/output direction control 00000000 P4CR.7 P4CR.6 P4CR.5 P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0
P5CR E1H
Bank1
Port5 input/output direction control --000000 - - P5CR.5 P5CR.4 P5CR.3 P5CR.2 P5CR.1 P5CR.0
P0PCR E9H
Bank0
Internal pull-high enable for Port0 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR EAH
Bank0
Internal pull-high enable for Port1 00000000 P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR EBH
Bank0
Internal pull-high enable for Port2 00000000 P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR
ECH
Bank0
Internal pull-high enable for Port3 00000000 P3PCR.7 P3PCR.6 P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 P3PCR.1 P3PCR.0
P4PCR
EDH
Bank0
Internal pull-high enable for Port4 00000000 P4PCR.7 P4PCR.6 P4PCR.5 P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0
P5PCR E9H
Bank1
Internal pull-high enable for Port5 --000000 - - P5PCR.5 P5PCR.4 P5PCR.3 P5PCR.2 P5PCR.1 P5PCR.0
P0OS EFH
Bank0
Output mode control --00---- - - P0OS.5 P0OS.4 - - - -

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Table 6.8 Timer SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON 88H
Bank0
Timer/Counter Control ----0000 - - - - IE1 IT1 IE0 IT0
T2CON C8H
Bank0
Timer/Counter 2 Control 00000000 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T
----2 ---- CP/R ----L ----2 ----
T2MOD C9H
Bank0
Timer/Counter 2 Mode 0-----00 TCLKP2 - - - - - T2OE DCEN
RCAP2L CAH
Bank0
Timer/Counter 2 Reload
/Capture Low Byte 00000000 RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
RCAP2H CBH
Bank0
Timer/Counter 2 Reload
/Capture High Byte 00000000 RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
TL2 CCH
Bank0
Timer/Counter 2 Low Byte 00000000 TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
TH2 CDH
Bank0
Timer/Counter 2 High Byte 00000000 TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
T3CON 88H
Bank1
Timer/Counter 3 Control 0-00-000 TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0
SWTHL 89H
Bank1
Timer/Counter data switch ------00 - - - - - - T5HLCON T3HLCON
TL3 8CH
Bank1
Timer/Counter 3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0
TH3 8DH
Bank1
Timer/Counter 3 High Byte 00000000 TH3.7 TH3.6 TH3.5 TH3.4 TH3.3 TH3.2 TH3.1 TH3.0
T4CON C8H
Bank1
Timer/Counter 4 Control 00000000 TF4 TC4 T4PS1 T4PS0 T4M1 T4M0 TR4 T4CLKS
TL4 CCH
Bank1
Timer/Counter 4 Low Byte 00000000 TL4.7 TL4.6 TL4.5 TL4.4 TL4.3 TL4.2 TL4.1 TL4.0
TH4 CDH
Bank1
Timer/Counter 4 High Byte 00000000 TH4.7 TH4.6 TH4.5 TH4.4 TH4.3 TH4.2 TH4.1 TH4.0
T5CON C0H
Bank1
Timer/Counter 5 Control 0-00--0- TF5 - T5PS1 T5PS0 - - TR5 -
TL5 CEH
Bank1
Timer/Counter 5 Low Byte 00000000 TL5.7 TL5.6 TL5.5 TL5.4 TL5.3 TL5.2 TL5.1 TL5.0
TH5 CFH
Bank1
Timer/Counter 5 High Byte 00000000 TH5.7 TH5.6 TH5.5 TH5.4 TH5.3 TH5.2 TH5.1 TH5.0

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Table 6.9 EUART SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCON 98H
Bank0
EUART0 Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL REN TB8 RB8 TI RI
SBUF 99H
Bank0
EUART0 Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
SADEN 9BH
Bank0
EUART0 Slave Address Mask 00000000 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
SADDR 9AH
Bank0
EUART0 Slave Addres 00000000 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
PCON 87H
Bank0
Power & serial Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
SCON1 98H
Bank1
EUART1 Serial Control 00000000 SM10/FE1 SM11/
RXOV1 SM12/ TXCOL1 REN1 TB18 RB18 TI1 RI1
SBUF1 99H
Bank1
EUART1 Serial Data Buffer 00000000 SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
SADEN1 9AH
Bank1
EUART1 Slave Address Mask 00000000 SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
SADDR1 9BH
Bank1
EUART1 Slave Addres 00000000 SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0
SBRTH 9DH
Bank1
EUART1 Baudrate Generator 00000000 SBRTEN SBRT.14 SBRT.13 SBRT.12 SBRT.11 SBRT.10 SBRT.9 SBRT.8
SBRTL 9CH
Bank1
EUART1 Baudrate Generator 00000000 SBRT.7 SBRT.6 SBRT.5 SBRT.4 SBRT.3 SBRT.2 SBRT.1 SBRT.0
BFINE 9EH
Bank1
EUART1 Baudrate Generator 0000---- BFINE.7 BFINE.6 BFINE.5 BFINE.4 - - - -
Table 6.10 SPI SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPCON A2H
Bank0
SPI Control 00000000 DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0
SPSTA F8H
Bank0
SPI Status 00000--- SPEN SPIF MODF WCOL RXOV - - -
SPDAT A3H
Bank0
SPI Data 00000000 SPDAT7 SPDAT6 SPDAT5 SPDAT4 SPDAT3 SPDAT2 SPDAT1 SPDAT0

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Table 6.11 ADC SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADCON 93H
Bank0
ADC Control 00000000 ADON ADCIF EC REFC SCH2 SCH1 SCH0 GO/D
----O ----N ----E ----
ADT 94H
Bank0
ADC Time Configuration 00000000 TADC2 TADC1 TADC0 CDIR TS3 TS2 TS1 TS0
ADCH 95H
Bank0
ADC Channel Configuration 00000000 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADDL 96H
Bank0
ADC Data Low Byte ----0000 - - - - A3 A2 A1 A0
ADDH 97H
Bank0
ADC Data High Byte 00000000 A11 A10 A9 A8 A7 A6 A5 A4
ADCON1 92H
Bank0
ADC Control 1 -----000 - - - - - RESO CH8 SCH3
Table 6.12 Buzzer SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
BUZCON BDH
Bank0
Buzzer output control ----0000 - - - - BCA2 BCA1 BCA0 BZEN
Table 6.13 LCD SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DISPCON ABH
Bank0
LCD Control 00000000 DISPSEL LCDON ELCC DUTY0 VOL3 VOL2 VOL1 VOL0
DISPCON1
ADH
Bank0
LCD Control 1 00000000 MODSW DUTY2 DUTY1 RLCD FCCTL1 FCCTL0 MOD1 MOD0
DISPCLK0
ACH
Bank0
LCD clock 0 ------00 - - - - - - DCK1 DCK0
P0SS B6H
Bank0
P0 mode select 00000000 P4S7 P4S6 P4S5 P5S5 P5S4 P0S2 P0S1 P0S0
P1SS 9CH
Bank0
P1 mode select 00000000 P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0
P2SS 9DH
Bank0
P2 mode select 00000000 P2S7 P2S6 P2S5 P2S4 P2S3 P2S2 P2S1 P2S0
P3SS 9EH
Bank0
P3 mode select 00000000 P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0

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Table 6.14LED SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DISPCON ABH
Bank0
LED Control 00-0---- DISPSEL LEDON - DUTY0 - - - -
DISPCON1
ADH
Bank0
LED Control 1 000----- MODSW DUTY2 DUTY1 - - - - -
DISPCLK0
ACH
Bank0
LED clock 0 ------00 - - - - - - DCK1 DCK0
P1SS 9CH
Bank0
P1 mode select 00000000 P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0
P3SS 9EH
Bank0
P3 mode select 00000000 P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0
Table 6.15 PWM SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMEN CFH
Bank0
PWM0 timer enable 00000000 EPWM0 EFLT PWM01COE PWM01BOE PWM01AOE PWM0COE PWM0BOE PWM0AOE
PWMLO E7H
Bank0
PWM0 register Lock 00000000 PWMLO.7 PWMLO.6 PWMLO.5 PWMLO.4 PWMLO.3 PWMLO.2 PWMLO.1 PWMLO.0
PWM0C D2H
Bank0
12-bit PWM0 Control 00000000 PWM0IE PWM0IF TnCK02 FLTS FLTC PWM0S TnCK01 TnCK00
PWM0PL D3H
Bank0
12-bit PWM0 Period Control low
byte 00000000 PP0.7 PP0.6 PP0.5 PP.4 PP0.3 PP0.2 PP0.1 PP0.0
PWM0PH D4H
Bank0
12-bit PWM0 Period Control high
byte ----0000 - - - - PP0.11 PP0.10 PP0.9 PP0.8
PWM0DL D5H
Bank0
12-bit PWM0 Duty Control low byte 00000000 PD0.7 PD0.6 PD0.5 PD0.4 PD0.3 PD0.2 PD0.1 PD0.0
PWM0DH D6H
Bank0
12-bit PWM0 Duty Control high byte ----0000 - - - - PD0.11 PD0.10 PD0.9 PD0.8
PWM0DT D1H
Bank0
12-bit PWM0 Dead time control 00000000 DT0.7 DT0.6 DT0.5 DT0.4 DT0.3 DT0.2 DT0.1 DT0.0
PWM1C D9H
Bank0
8-bit PWM1 Control 0000-000 PWM1EN PWM1S TnCK11 TnCK10 - PWM1IE PWM1IF PWM1OE
PWM1P DAH
Bank0
8-bit PWM1 Period Control 00000000 PP1.7 PP1.6 PP1.5 PP1.4 PP1.3 PP1.2 PP1.1 PP1.0
PWM1D DBH
Bank0
8-bit PWM1 Duty Control 00000000 PD1.7 PD1.6 PD1.5 PD1.4 PD1.3 PD1.2 PD1.1 PD1.0

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Table 6.16 LPD SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LPDCON B3H
Bank0
LPD Control 00000000 LPDEN LPDF LPDMD LPDIF LPDS3 LPDS2 LPDS1 LPDS0
Table 6.17 CRC SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CRCCON FDH
Bank0
CRC verify control 00--0000 CRC_GO CRCIF - - CRCADR3 CRCADR2 CRCADR1 CRCADR0
CRCDL F9H
Bank0
CRC verify result low byte 00000000 CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0
CRCDH FAH
Bank0
CRC verify result high byte 00000000 CRCD15 CRCD14 CRCD13 CRCD12 CRCD11 CRCD10 CRCD9 CRCD8
Note: - :Unimplemented

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SFR Map
Bank0
Bit
addressable
Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8H SPSTA CRCDL CRCDH IB_OFFSET IB_DATA CRCCON FFH
F0H B AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE F7H
E8H EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR P0OS EFH
E0H ACC P0CR P1CR P2CR P3CR P4CR PWMLO E7H
D8H EXF1 PWM1C PWM1P PWM1D DFH
D0H PSW PWM0DT PWM0C PWM0PL PWM0PH PWM0DL PWM0DH D7H
C8H T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PWMEN CFH
C0H P4 CMP1CON CMP2CON CMPCON0 CMPCON1 INVCON INVCTL INVCTH C7H
B8H IPL0 IPL1 IENC IENC1 BUZCON BFH
B0H P3 RSTSTAT CLKCON LPDCON IPH0 IPH1 P0SS B7H
A8H IEN0 IEN1 DISPCLK1 DISPCON DISPCLK0 DISPCON1 AFH
A0H P2 SCMCON SPCON SPDAT ISPLO ISPCON FLASHCON A7H
98H SCON SBUF SADDR SADEN P1SS P2SS P3SS 9FH
90H P1 ADCON1 ADCON ADT ADCH ADDL ADDH 97H
88H TCON EXCON SUSLO 8FH
80H P0 SP DPL DPH DPL1 DPH1 INSCON PCON 87H
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Bank1
Bit
addressable
Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8H FFH
F0H B AUXC XPAGE F7H
E8H P5PCR EFH
E0H ACC P5CR E7H
D8H DFH
D0H PSW D7H
C8H T4CON TL4 TH4 TL5 TH5 CFH
C0H T5CON C7H
B8H IPL0 IPL1 BFH
B0H IPH0 IPH1 B7H
A8H IEN0 IEN1 AFH
A0H A7H
98H SCON1 SBUF1 SADDR1 SADEN1 SBRTL SBRTH BFINE 9FH
90H 97H
88H T3CON SWTHL TL3 TH3 SUSLO 8FH
80H P5 SP DPL DPH DPL1 DPH1 INSCON PCON 87H
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Note: The unused addresses of SFR are not available.