Sino Wealth SH69P55A User manual

SH69P55A/K55A
OTP/MASK 8K 4-Bit Micro-controller
With LCD Driver & 10-bit SAR ADC
1 V2.2
Features
SH6610D-Based Single-Chip 4-bit Micro-Controller With
LCD Driver & 10-bit SAR ADC
OTP ROM: 8K X 16 bits (SH69P55A)
MASK ROM: 8K X 16 bits (SH69K55A)
RAM: 515X 4 bits
- 99 System Control Register
- 376 Data Memory
- 40 LCD RAM
Operation Voltage: 2.4V - 5.5V
- fOSC = 30k- 4MHz, VDD = 2.4V - 5.5V
- fOSC = 30k - 8MHz, VDD = 4.5V - 5.5V
42 CMOS Bi-directional I/O Pins (Including one
open-drain output PortC.3)
Built-in Pull-high Resistor For PORTA - PORTK
8-Level Stack (Including Interrupts)
Two 8-bit and One 16-bit Auto Re-loaded Timer/Counter
LCD Driver:
- 16 SEG X 8 COM (1/8 Duty, 1/4 Bias)
- 18 SEG X 6 COM (1/6 Duty, 1/3 Bias)
- 20 SEG X 4 COM (1/4 Duty, 1/3 Bias)
LED Driver:
- 8 SEG X 6 COM (1/6 Duty)
- 8 SEG X 5 COM (1/5 Duty)
- 8 SEG X 4 COM (1/4 Duty)
Powerful Interrupt Sources:
- Timer0 Interrupt
- Timer1 Interrupt
- Timer2 Interrupt
- External Interrupts (PORTB & PORTC Falling Edge
Interrupts, A/D Interrupt, Key Scan Interrupt)
Oscillator (Code Option)
- Crystal Oscillator: 32.768kHz, 400kHz - 8MHz
- Ceramic Resonator: 400kHz - 8MHz
- External RC Oscillator: 400kHz - 8MHz
- Internal RC Oscillator: 4MHz ±5%
One Built-in PLL Oscillator (1, 2, 4, 8MHz)
Instruction Cycle Time (4/fOSC)
10 Channels 10-Bit Resolution Analog/Digital Converter
(ADC)
2 Channel Tone Generators
Built-in Automatic Key Scanner
Zero Cross Detect Function for AC Power Line
Read ROM Data Table Function (RDT)
One Channel 8+2Bit PWM Output
Reset
- Built-in Watchdog Timer (WDT) [(Code Option)]
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) [(Code Option)]
Two-Level Low Voltage Reset (LVR) (Code Option)
Two Low Power Operation Modes: HALT and STOP
OTP Type/Code Protection (SH69P55A)
MASK Type (SH69K55A)
28-pin SOP package; 44-pin QFP package; 32-pin DIP
package
General Description
SH69P55A/69K55A is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer,
LCD/LED driver, I/O ports, watchdog timer, 10 channels 10-bit resolution ADC, low voltage reset, automatic key scan, PLL
and Zero Cross Detect function. The SH69P55A/69K55A is suitable for washing machine and micro-wave oven etc.
application.

SH69P55A/K55A
2
Pin Configuration (44 Pin)
GND
VDD
PORTA.0/SEG1/LED_S1/KEY_I1
PORTA.2/SEG3/LED_S3/KEY_I3
PORTA.3/SEG4/LED_S4/KEY_I4
PORTF.0/SEG5/LED_S5/KEY_I5
PORTF.1/SEG6/LED_S6
PORTF.3/SEG8/LED_S8
PORTI.0/SEG9
25 24 2332 31 30 29 28 27 26
1234567891011
33
12
13
14
15
16
17
18
19
22
21
20
SH69P55A/69K55A
/44 Pin
PORTC.0/PLL_C
OSCO/PORTC.1
OSCI/PORTC.2
PORTE.3/COM5/LED_C5/SEG20 PORTE.2/COM6/LED_C6/SEG19 PORTE.1/COM7/SEG18 PORTE.0/COM8/SEG17 PORTH.3/SEG16 PORTH.2/SEG15 PORTH.1/SEG14 PORTH.0/SEG13 PORTI.3/SEG12 PORTI.2/SEG11
PORTI.1/SEG10
44
43
42
41
40
39
38
37
34
35
36
PORTK.1 PORTK.0
PORTF.2/SEG7/LED_S7
PORTA.1/SEG2/LED_S2/KEY_I2
RESET/PORTC.3
PORTD.0/COM4/LED_C4/KEY_04
PORTD.1/COM3/LED_C3/KEY_03
PORTD.2/COM2/LED_C2/KEY_02
PORTD.3/COM1/LED_C1/KEY_01
PORTB.1/AN1
PORTB.2/AN2
PORTB.3/AN3
PORTG.0/PWM
PORTG.1/TONE/AN9
PORTG.2/VREF/T0
PORTG.3/T2/AN8
PORTJ.0/AN4 PORTJ.1/AN5 PORTJ.2/AN6 PORTJ.3/AN7
PORTB.0/AN0

SH69P55A/K55A
3
Pin Configuration (32 Pin & 28 Pin)
SH69P55A/69K55A
/32Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
GND
PORTF.0/SEG5/KEY_I5/LED_S5
PORTH.2/SEG15
PORTF.3/SEG8/LED_S8
PORTF.2/SEG7/LED_S7
PORTF.1/SEG6/LED_S6
PORTD.0/COM4/LED_C4/KEY_O4
PORTE.3/COM5/SEG20/LED_C5
PORTE.2/COM6/SEG19/LED_C6
PORTH.3/SEG16
PORTD.3/COM1/LED_C1/KEY_O1
PORTD.2/COM2/LED_C2/KEY_O2
PORTD.1/COM3/LED_C3/KEY_O3
PORTA.2/SEG3/KEY_I3/LED_S3
PORTA.3/SEG4/KEY_I4/LED_S4
PORTE.1/COM7/SEG18
PORTE.0/COM8/SEG17
PORTB.1/AN1
PORTB.2/AN2
PORTB.3/AN3
PORTG.0/PWM
PORTG.1/TONE/AN9
PORTG.2/VREF/T0
PORTB.0/AN0
PORTC.0/PLL_C
OSCO/PORTC.1
OSCI/PORTC.2
PORTG.3/T2/AN8
RESET/PORTC.3
PORTA.0/SEG1/LED_S1/KEY_I1
PORTA.1/SEG2/LED_S2/KEY_I2
SH69P55A/69K55A
/28Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PORTA.3/SEG4/LED_S4
PORTI.0/SEG9
PORTB.2/AN2
PORTB.1/AN1
PORTB.0/AN0
PORTA.1/SEG2/LED_S2
PORTA.2/SEG3/LED_S3
PORTI.1/SEG10
PORTA.0/SEG1/LED_S1
VDD
PORTC.0/PLL_C
PORTG.3/T2/AN8
GND
PORTJ.1/AN5
PORTJ.2/AN6
PORTJ.3/AN7
PORTJ.0/AN4
PORTE.3/COM5/LED_C5
PORTE.2/COM6/LED_C6
PORTE.1/COM7
PORTE.0/COM8
RESET/PORTC.3
OSCO/PORTC.1
OSCI/PORTC.2
PORTB.3/AN3
PORTG.0/PWM
PORTG.1/TONE/AN9
PORTG.2/VREF/T0

SH69P55A/K55A
4
Block Diagram
PORTJ.3 - 0/AN7 - AN4
Oscillator
CPU
WDT RC
PORTB (4-bit)
PORTF (4-bit)
ROM
8196 X 16 Bits
RAM
99 X 4 Bits
System Register
Watch Dog
Timer
PORTE (4-bit)
Reset Circuit
OSCI/PORTC.2
OSCO/PORTC.1
VDD
GND
RESET/PORTC.3
PORTA (4-bit)
PORTD (4-bit) PORTD.3 - 0/COM1 - COM4/
LED_C1 - LED_C4/
KEY_O1 - KEY_O4
376 X 4 Bits
Data Memory
10ch X 10bits
ADC
1 X ( 8+2) Bits
PWM
Power Circuit
PORTB.3 - 0/AN3 - AN0
PORTF.3 - 0/SEG8 - SEG5/
LED_S8 - LED_S5/KEY_I5
PORTE.3 - 0/COM5 - COM8/
LED_C5 - LED_C6/
SEG20 - SEG17
PORTA.3 - 0/SEG4 - SEG1/
LED_S4 - LED_S1/
KEY_I4 - KEY_I1
PORTH (4-bit)
PORTC.3
PORTH.3 - 0/SEG16 - SEG13
Tone generator 1
PORTC.2 - 0
Tone generator 2
PORTG.3 - 0/T2, T0, VREF/
TONE/PWM/AN8 - AN9
PORTG (4-bit)
PORTI.3 - 0/SEG12 - SEG9
PORTI (4-bit)
PORTJ (4-bit)
PORTK (2-bit)
PORTK.1 - 0
PORTC.0/PLL_C
TIMER 0
(8 Bits)
TIMER1
(8 Bits)
TIMER2
(16 Bits)
40X 4 Bits
LCD RAM

SH69P55A/K55A
5
Pin Descriptions
Pin No.
44 pin 28 pin 32 pin Pad No. Pin Name I/O Description
44 4 7 1
PORTG.2
/T0
/VREF
I/O
I
I
Bit programmable I/O
Timer0 Clock/Counter input pin. (Schmitt trigger input)
External ADC VREF input
1 5 8 2
PORTG.3
/T2
/AN8
I/O
I
I
Bit programmable I/O
Timer2 Clock/Counter input pin. (Schmitt trigger input)
ADC input channel 8
3 - 2 - - 4 - 3 PORTK.1 - 0 I/O Bit programmable I/O
7 - 4 9 - 6 - 8 - 5 PORTJ.3 - 0
/AN7 - AN4
I/O
I
Bit programmable I/O
ADC input channel 7 - 4
8 10 9 10
PORTC.0
/PLL_C
I/O
I
P
Bit programmable I/O (code option)
Vector Interrupt (Active falling edge by system register setup)
Built-in PLL Connect with external capacitor
9 11 10 11
PORTC.1
/OSCO
I/O
I
I/O
Bit programmable I/O (code option)
Vector Interrupt (Active falling edge by system register setup)
OSC output pin. No output in RC mode
10 12 11 12
PORTC.2
/OSCI
I/O
I
I
Bit programmable I/O (code option)
Vector Interrupt (Active falling edge by system register setup)
OSC input pin, connected to a crystal, ceramic or external
resistor
11 13 12 13
RESET
/PORTC.3
I
I
I/O
Reset pin input (active low, Schmitt trigger input)
Vector Interrupt (Active falling edge by system register setup)
Bit programmable I/O, open-drain
12 14 13
9, 14, 35,
36, 43 GND P Ground pin
13 15 14 15,16 VDD P Power supply pin
17 - 14 19 - 16 18 - 15 20 - 17
PORTA.3 - 0
/SEG4 - SEG1
/LED_S4 - LED_S1
/KEY_I4 - KEY_I1
I/O
O
O
I
Bit programmable I/O
SEG4 - SEG1 signal output for LCD display
SEG4 - SEG1 signal output for LED display
Input for automatic key scan
18 - 19 21
PORTF.0
/SEG5
/LED_S5
/KEY_I5
I/O
O
O
I
Bit programmable I/O
SEG5 signal output for LCD display
SEG5 signal output for LED display
Input for automatic key scan
21 - 19 - 22 - 20 24 - 22
PORTF.3 - 1
/SEG8 - SEG6
/LED_S8 - LED_S6
I/O
O
O
Bit programmable I/O
SEG8 - SEG6 signal output for LCD display
SEG8 - SEG6 signal output for LED display
23 - 22 21 - 20 - 26- 25 PORTI.1 - 0
/SEG10 - SEG9
I/O
O
Bit programmable I/O
SEG10 - SEG9 signal output for LCD display
25 - 24 - - 28 - 27 PORTI.3 - 2
/SEG12 - SEG11
I/O
O
Bit programmable I/O
SEG12 - SEG11 signal output for LCD display
27 - 26 - - 30 - 29 PORTH.1 - 0
/SEG14 - SEG13
I/O
O
Bit programmable I/O
SEG14 - SEG13 signal output for LCD display
29 - 28 - 24 - 23 32 - 31 PORTH.3 - 2
/SEG16 - SEG15
I/O
O
Bit programmable I/O
SEG16 - SEG15 signal output for LCD display
31 - 30 23 - 22 26 - 25 34 - 33
PORTE.1 - 0
/COM7 - COM8
/SEG18 - SEG17
I/O
O
O
Bit programmable I/O
COM7 - COM8 signal output for LCD display
SEG18 - SEG17 signal output for LCD display

SH69P55A/K55A
6
Pin Descriptions (continued)
Pin No.
44 pin 28 pin 32 pin Pad No. Pin Name I/O Description
33 - 32 25 - 24 28 - 27 38 - 37
PORTE.3 - 2
/COM5 - COM6
/SEG20 - SEG19
/LED_C5 - LED_C6
I/O
O
O
O
Bit programmable I/O
COM5 - COM6 signal output for LCD display
SEG20 - SEG19 signal output for LCD display
COM5 - COM6 signal output for LED display
37 - 34 - 32 - 29 42 - 39
PORTD.3 - 0
/COM1 - COM4
/LED_C1 - LED_C4
/KEY_O1 - KEY_O4
I/O
O
O
O
Bit programmable I/O
COM1 - COM4 signal output for LCD display
COM1 - COM4 signal output for LED display
Output for automatic key scan
40 - 38 28 - 26 3 - 1 46 - 44
PORTB.2 - 0
/AN2 - AN0
I/O
I
I
Bit programmable I/O
Vector Interrupt (Active falling edge by system register setup)
ADC input channel 2 - 0
41 1 4 47
PORTB.3
/AN3
I/O
I
I
Bit programmable I/O
Vector Interrupt (Active falling edge by system register setup)
ADC input channel 3
42 2 5 48 PORTG.0
/PWM
I/O
O
Bit programmable I/O
PWM output
43 3 6 49
PORTG.1
/TONE
/AN9
I/O
O
I
Bit programmable I/O
TONE Generator output
ADC input channel 9
Which, I: Input; O: Output; P: Power; Z: High impedance
OTP Programming Pin Description* (OTP Program Mode)
Pin No.
44 pin 28 pin 32 pin Pad No. Symbol I/O Sharing Pin Description
13 15 14 14, 15 VDD PVDD Programming Power supply (+5.5V)
11 13 12 12 VPP P RESET Programming high voltage Power supply (+11V)
12 14 13 13 GND P GND Ground
10 12 11 11 SCK I OSCI Programming Clock input pin
14 16 15 16 SDA I/O PORTA.0 Programming Data pin
*: Only SH69P55A has the OTP Program Mode, SH69K55A has not the OTP Program Mode.

SH69P55A/K55A
7
Functional Descriptions
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM
address. (Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service
or call instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register,
or data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value
into (TBR, AC). ROM code bit7-bit4 is placed into TBR and
bit3-bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bits), DPM
(3-bits) and DPL (4-bits). The addressing range is
000H--3FFH. Pseudo index address (INX) is used to read
or write Data memory, then RAM address bit9 - bit0 which
comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents
of CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into
13 bits X 8 levels. The stack is operated on a first-in,
last-out basis and returned sequentially to the PC by the
return instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will
be shifted out, that program execution may enter an
abnormal state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep
data after the CPU entering STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register: $000 - $02F, $380 - $3AF, $3C0 - $3C2
Data memory: $030 - $1A7
LCD RAM space: $300 - $313, $320 - $333
RAM Bank Table:
Bank 0
B = 0 Bank 1 B = 1 Bank 2 B = 2 Bank 3 B = 3 Bank 4 B = 4 Bank 5
B = 5 Bank 6
B = 6 Bank 7 B = 7
$000 - $07F $080 - $0FF $100 - $17F $180 - $1FF $200 - $27F $280 - $2FF $300 - $37F $380 - $3AF,
$3C0 - $3C2
Where, B: RAM bank bit use in instructions

SH69P55A/K55A
8
2.2. Configuration of System Register:
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$00 IET0 IET1 IET2 IEEX R/W Interrupt enable flags register
$01 IRQT0 IRQT1 IRQT2 IRQEX R/W Interrupt request flags register
$02 T0S T0M.2 T0M.1 T0M.0 R/W Bit2-0: Timer0 Mode register
Bit3: T0 signal source select register
$03 T0E T1M.2 T1M.1 T1M.0 R/W Bit2-0: Timer1 Mode register
Bit3: T0 signal edge select register
$04 T0L.3 T0L.2 T0L.1 T0L.0 R/W Timer0 load/counter low nibble register
$05 T0H.3 T0H.2 T0H.1 T0H.0 R/W Timer0 load/counter high nibble register
$06 T1L.3 T1L.2 T1L.1 T1L.0 R/W Timer1 load/counter low nibble register
$07 T1H.3 T1H.2 T1H.1 T1H.0 R/W Timer1 load/counter high nibble register
$08 PA.3 PA.2 PA.1 PA.0 R/W PORTA data register
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB data register
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC data register
$0B PD.3 PD.2 PD.1 PD.0 R/W PORTD data register
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE data register
$0D PF.3 PF.2 PF.1 PF.0 R/W PORTF data register
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch Register
$0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register
$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble register
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble register
$12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble register
$13 VREF ACR2 ACR1 ACR0 R/W Bit2-0: A/D port configuration control register
Bit3: Select Internal/External reference voltage register
$14 ADCON CH2 CH1 CH0 R/W Bit2-0: ADC channel control register
Bit3: ADC module operate control register
$15 T2E T2SC.2 T2SC.1 T2SC.0 R/W Bit2-0: Timer2 pre-scaler register
Bit3: T2 external signal edge select register
$16 FS1 FS0 OXS OXON R/W
Bit0: Turn on PLL register
Bit1: clock source select (1: PLL, 0: 32.768kHz) register
Bit3-2: PLL Frequency select register
$17 LVR - - - R/W Bit3: Low Voltage Reset flag register (Read and Write 0 only)
$18 PACR.3 PACR.2 PACR.1 PACR.0 R/W PORTA input/output control register
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 R/W PORTB input/output control register
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 R/W PORTC input/output control register
$1B PDCR.3 PDCR.2 PDCR.1 PDCR.0 R/W PORTD input/output control register
$1C PECR.3 PECR.2 PECR.1 PECR.0 R/W PORTE input/output control register
$1D PFCR.3 PFCR.2 PFCR.1 PFCR.0 R/W PORTF input/output control register
$1E
WDT
WDT.2 WDT.1 WDT.0 R/W
R
Bit2-0: Watch dog timer control register
Bit3: Watchdog timer overflow flag register (Read only)
$1F - - BNK1 BNK0 R/W Bit1-0: ROM Bank register

SH69P55A/K55A
9
Configuration of System Register (continued1):
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$20 PWMS TCK1 TCK0 PWM_EN R/W
Bit0: PWM output enable control register
Bit2-1: PWM clock control register
Bit3: PWM output mode of duty cycle control register
$21 PP.3 PP.2 PP.1 PP.0 R/W PWM period low nibble register
$22 PP.7 PP.6 PP.5 PP.4 R/W PWM period high nibble register
$23 - FSTP - - R/W Bit2: 32.768kHz oscillator is closed in the stop
$24 - - PDF.1 PDF.0 R/W PWM duty fine-tune bits register (2 bits)
$25 PD.3 PD.2 PD.1 PD.0 R/W PWM duty low nibble register (4 bits)
$26 PD.7 PD.6 PD.5 PD.4 R/W PWM duty high nibble register (4bits)
$27 T2GO DEC TM2S1 TM2S0 R/W
Bit1-0: Timer2 mode select register
Bit2: Select directive edge active enable register
Bit3: Set Timer2 function start register
$28
KEYNUM1 KEYNUM0 KEYEND
KEYEN R/W
R
Bit0: key scan enable register
Bit1: key scan end/processing register
Bit3-2: key scan result register
$29 LCDON DUTY2 DUTY1 DUTY0 R/W Bit2-0: Set duty and com register
Bit3: LCD display on control register
$2A - - - - R/W Reserved
$2B LEDEN LEDON EDUTY1 EDUTY0 R/W
Bit1-0: Set duty register
Bit2: Turn on LED driver register
Bit3: Enable LED driver register
$2C KEYC3 KEYC2 KEYC1 KEYC0 R Bit3-0: the result of key scan on KEY_O4 - 1 register
$2D KEYL3 KEYL2 KEYL1 KEYL0 R Bit3-0: the result of key scan on KEY_I5 - 1 register
$2E RLCD PS2 PS1 PS0 R/W Bit2-0: Configuration the segment register
Bit3: LCD bias resistor set register
$2F GO/ DONE TADC1 TADC0 - R/W Bit2-1: A/D Conversion Time control register
Bit3: ADC startup/status flag register
$380 RDT.3 RDT.2 RDT.1 RDT.0 R/W ROM Data table address/data register
$381 RDT.7 RDT.6 RDT.5 RDT.4 R/W ROM Data table address/data register
$382 RDT.11 RDT.10 RDT.9 RDT.8 R/W ROM Data table address/data register
$383 RDT.15 RDT.14 RDT.13 RDT.12 R/W ROM Data table address/data register
$384 T2D.3 T2D.2 T2D.1 T2D.0 R/W Timer2 load/counter low nibble register
$385 T2D.7 T2D.6 T2D.5 T2D.4 R/W Timer2 load/counter middle_L nibble register
$386 T2D.11 T2D.10 T2D.9 T2D.8 R/W Timer2 load/counter middle_H nibble register
$387 T2D.15 T2D.14 T2D.13 T2D.12 R/W Timer2 load/counter high nibble register
$388 PBIEN.3 PBIEN.2 PBIEN.1 PBIEN.0 R/W PORTB interrupt enable flags register
$389 PBIF.3 PBIF.2 PBGIF.1 PBIF.0 R/W PORTB interrupt request flags register
$38A PCIEN.3 PCIEN.2 PCIEN.1 PCIEN.0 R/W PORTC interrupt enable flags register
$38B PCIF.3 PCIF.2 PCIF.1 PCIF.0 R/W PORTC interrupt request flags register
$38C - - KEYIE ADIE R/W Bit0: AD interrupt enable flag register
Bit1: Key scan interrupt enable flag register
$38D - - KEYIF ADIF R/W Bit0: AD interrupt request flag register
Bit1: Key scan interrupt request flag register
$38E PG.3 PG.2 PG.1 PG.0 R/W PORTG data register
$38F PH.3 PH.2 PH.1 PH.0 R/W PORTH data register

SH69P55A/K55A
10
Configuration of System Register (continued2):
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$390 PI.3 PI.2 PI.1 PI.0 R/W PORTI data register
$391 PJ.3 PJ.2 PJ.1 PJ.0 R/W PORTJ data register
$392 - - PK.1 PK.0 R/W PORTK data register
$393 PGCR.3 PGCR.2 PGCR.1 PGCR.0 R/W PORTG input/output control register
$394 PHCR.3 PHCR.2 PHCR.1 PHCR.0 R/W PORTH input/output control register
$395 PICR.3 PICR.2 PICR.1 PICR.0 R/W PORTI input/output control register
$396 PJCR.3 PJCR.2 PJCR.1 PJCR.0 R/W PORTJ input/output control register
$397 - - PKCR.1 PKCR.0 R/W PORTK input/output control register
$398 PPACR.3 PPACR.2 PPACR.1 PPACR.0 R/W PORTA pull high control register
$399 PPBCR.3 PPBCR.2 PPBCR.1 PPBCR.0 R/W PORTB pull high control register
$39A - PPCCR.2 PPCCR.1 PPCCR.0 R/W PORTC pull high control register
$39B PPDCR.3 PPDCR.2 PPDCR.1 PPDCR.0 R/W PORTD pull high control register
$39C PPECR.3 PPECR.2 PPECR.1 PPECR.0 R/W PORTE pull high control register
$39D PPFCR.3 PPFCR.2 PPFCR.1 PPFCR.0 R/W PORTF pull high control register
$39E PPGCR.3 PPGCR.2 PPGCR.1 PPGCR.0 R/W PORTG pull high control register
$39F PPHCR.3 PPHCR.2 PPHCR.1 PPHCR.0 R/W PORTH pull high control register
$3A0 PPICR.3 PPICR.2 PPICR.1 PPICR.0 R/W PORTI pull high control register
$3A1 PPJCR.3 PPJCR.2 PPJCR.1 PPJCR.0 R/W PORTJ pull high control register
$3A2 - - PPKCR.1 PPKCR.0 R/W PORTK pull high control register
$3A3 TG1.3 TG1.2 TG1.1 TG1.0 R/W Tone generator 1 low nibble register
$3A4 TG1.7 TG1.6 TG1.5 TG1.4 R/W Tone generator 1 middle nibble register
$3A5 TG1.11 TG1.10 TG1.9 TG1.8 R/W Tone generator 1 high nibble register
$3A6 TG2.3 TG2.2 TG2.1 TG2.0 R/W Tone generator 2 low nibble register
$3A7 TG2.7 TG2.6 TG2.5 TG2.4 R/W Tone generator 2 middle nibble register
$3A8 TG2.11 TG2.10 TG2.9 TG2.8 R/W Tone generator 2 high nibble register
$3A9 TV1.3 TV1.2 TV1.1 TV1.0 R/W Tone generator 1 volume low nibble register
$3AA TG1EN TV1.6 TV1.5 TV1.4 R/W Bit2-0: Tone generator 1 volume high nibble register
Bit3: Tone generator 1 enable register
$3AB TV2.3 TV2.2 TV2.1 TV2.0 R/W Tone generator 2 volume low nibble register
$3AC TG2EN TV2.6 TV2.5 TV2.4 R/W Bit2-0: Tone generator 2 volume high nibble register
Bit3: Tone generator 2 enable register
$3AD - - A1 A0 R ADC data low nibble register
$3AE A5 A4 A3 A2 R ADC data middle nibble register
$3AF A9 A8 A7 A6 R ADC data high nibble register
$3C0 T1S - - - R/W T1 signal source select register
$3C1 LPS3 LPS2 LPS1 LPS0 R/W Bit3-0: LCD frame frequency control register
$3C2 ACR3 CH3 - - R/W Bit3: A/D port configuration control register
Bit2: ADC channel control register

SH69P55A/K55A
11
3. ROM
The ROM can address 8192 X 16 bits of program area from $000 to $1FFF.
3.1. Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
Address Instruction Remarks
$000 JMP* Jump to RESET service routine
$001 JMP* Jump to TIMER0 interrupt service routine
$002 JMP* Jump to TIMER1 interrupt service routine
$003 JMP* Jump to TIMER2 interrupt service routine
$004 JMP* Jump to External interrupts service routine
* JMP instruction can be replaced by any instruction.
3.2. Bank Switch Mapping
Program Counter (PC11 - PC0) can only address 4K ROM Space. The bank switch technique is used to extend the CPU
address space. The lower 2K of the CPU address space maps to the lower 2K of ROM space (BANK0). The upper 2K of the
CPU address space maps to one of the three banks (BNK3-0 = 0, 1, 2) of the upper 6K of ROM.
The bank switch mapping is as follows:
ROM Space
CPU Address BNK = $00 BNK = $01 BNK = $02
Low 2K address 0000 - 07FF
(BANK 0)
0000 - 07FF
(BANK 0)
0000 - 07FF
(BANK 0)
Upper 2K address 0800 - 0FFF
(BANK 1)
1000 - 17FF
(BANK 2)
1800 - 1FFF
(BANK 3)

SH69P55A/K55A
12
4. Initial State
4.1. System Register State:
Address Bit 3 Bit 2 Bit 1 Bit 0 Power On Reset
/Pin Reset WDT Reset /Low Voltage Reset
$00 IET0 IET1 IET2 IEEX 0000 0000
$01 IRQT0 IRQT1 IRQT2 IRQEX 0000 0000
$02 T0S T0M.2 T0M.1 T0M.0 0000 uuuu
$03 T0E T1M.2 T1M.1 T1M.0 0000 uuuu
$04 T0L.3 T0L.2 T0L.1 T0L.0 xxxx xxxx
$05 T0H.3 T0H.2 T0H.1 T0H.0 xxxx xxxx
$06 T1L.3 T1L.2 T1L.1 T1L.0 xxxx xxxx
$07 T1H.3 T1H.2 T1H.1 T1H.0 xxxx xxxx
$08 PA.3 PA.2 PA.1 PA.0 0000 0000
$09 PB.3 PB.2 PB.1 PB.0 0000 0000
$0A PC.3 PC.2 PC.1 PC.0 0000 0000
$0B PD.3 PD.2 PD.1 PD.0 0000 0000
$0C PE.3 PE.2 PE.1 PE.0 0000 0000
$0D PF.3 PF.2 PF.1 PF.0 0000 0000
$0E TBR.3 TBR.2 TBR.1 TBR.0 xxxx uuuu
$0F INX.3 INX.2 INX.1 INX.0 xxxx uuuu
$10 DPL.3 DPL.2 DPL.1 DPL.0 xxxx uuuu
$11 - DPM.2 DPM.1 DPM.0 -xxx -uuu
$12 - DPH.2 DPH.1 DPH.0 -xxx -uuu
$13 VREF ACR2 ACR1 ACR0 0000 uuuu
$14 ADCON CH2 CH1 CH0 0000 0uuu
$15 T2E T2SC.2 T2SC.1 T2SC.0 0000 uuuu
$16 FS1 FS0 OXS OXON 0000 uuuu
$17 LVR - - - 0--- *---
$18 PACR.3 PACR.2 PACR.1 PACR.0 0000 0000
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 0000 0000
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 0000 0000
$1B PDCR.3 PDCR.2 PDCR.1 PDCR.0 0000 0000
$1C PECR.3 PECR.2 PECR.1 PECR.0 0000 0000
$1D PFCR.3 PFCR.2 PFCR.1 PFCR.0 0000 0000
$1E
WDT
WDT.2 WDT.1 WDT.0
0000 #000
$1F - - BNK1 BNK0 --00 --00
$20 PWMS TCK1 TCK0 PWM_EN 0000 uuu0
$21 PP.3 PP.2 PP.1 PP.0 xxxx uuuu
$22 PP.7 PP.6 PP.5 PP.4 xxxx uuuu
$23 - FSTP -0-- -0--

SH69P55A/K55A
13
System Register State (Continued1):
Address Bit 3 Bit 2 Bit 1 Bit 0 Power On Reset
/Pin Reset WDT Reset /Low Voltage Reset
$24 PDF.1 PDF.0 --xx --uu
$25 PD.3 PD.2 PD.1 PD.0 xxxx uuuu
$26 PD.7 PD.6 PD.5 PD.4 xxxx uuuu
$27 T2GO DEC TM2S1 TM2S0 0000 0uuu
$28 KEYNUM1 KEYNUM0 KEYEND KEYEN 0000 000u
$29 LCDON DUTY2 DUTY1 DUTY0 0000 uuuu
$2A - - - - ---- ----
$2B LEDEN LEDON EDUTY1 EDUTY0 0000 uuuu
$2C KEYC3 KEYC2 KEYC1 KEYC0 0000 uuuu
$2D KEYL3 KEYL2 KEYL1 KEYL0 0000 uuuu
$2E RLCD PS2 PS1 PS0 0000 uuuu
$2F GO/ DONE TADC1 TADC0 - 000- 0uu-
$380 RDT.3 RDT.2 RDT.1 RDT.0 xxxx uuuu
$381 RDT.7 RDT.6 RDT.5 RDT.4 xxxx uuuu
$382 RDT.11 RDT.10 RDT.9 RDT.8 xxxx uuuu
$383 RDT.15 RDT.14 RDT.13 RDT.12 xxxx uuuu
$384 T2D.3 T2D.2 T2D.1 T2D.0 xxxx xxxx
$385 T2D.7 T2D.6 T2D.5 T2D.4 xxxx xxxx
$386 T2D.11 T2D.10 T2D.9 T2D.8 xxxx xxxx
$387 T2D.15 T2D.14 T2D.13 T2D.12 xxxx xxxx
$388 PBIEN.3 PBIEN.2 PBIEN.1 PBIEN.0 0000 0000
$389 PBIF.3 PBIF.2 PBIF.1 PBIF.0 0000 0000
$38A PCIEN.3 PCIEN.2 PCIEN.1 PCIEN.0 0000 0000
$38B PCIF.3 PCIF.2 PCIF.1 PCIF.0 0000 0000
$38C - KEYIE ADIE --00 --00
$38D - - KEYIF ADIF --00 --00
$38E PG.3 PG.2 PG.1 PG.0 0000 0000
$38F PH.3 PH.2 PH.1 PH.0 0000 0000
$390 PI.3 PI.2 PI.1 PI.0 0000 0000
$391 PJ.3 PJ.2 PJ.1 PJ.0 0000 0000
$392 - - PK.1 PK.0 --00 --00
$393 PGCR.3 PGCR.2 PGCR.1 PGCR.0 0000 0000
$394 PHCR.3 PHCR.2 PHCR.1 PHCR.0 0000 0000
$395 PICR.3 PICR.2 PICR.1 PICR.0 0000 0000
$396 PJCR.3 PJCR.2 PJCR.1 PJCR.0 0000 0000
$397 - - PKCR.1 PKCR.0 --00 --00
$398 PPACR.3 PPACR.2 PPACR.1 PPACR.0 0000 0000

SH69P55A/K55A
14
System Register State (Continued2):
Address Bit 3 Bit 2 Bit 1 Bit 0 Power On Reset
/Pin Reset WDT Reset /Low Voltage Reset
$399 PPBCR.3 PPBCR.2 PPBCR.1 PPBCR.0 0000 0000
$39A - PPCCR.2 PPCCR.1 PPCCR.0 -000 -000
$39B PPDCR.3 PPDCR.2 PPDCR.1 PPDCR.0 0000 0000
$39C PPECR.3 PPECR.2 PPECR.1 PPECR.0 0000 0000
$39D PPFCR.3 PPFCR.2 PPFCR.1 PPFCR.0 0000 0000
$39E PPGCR.3 PPGCR.2 PPGCR.1 PPGCR.0 0000 0000
$39F PPHCR.3 PPHCR.2 PPHCR.1 PPHCR.0 0000 0000
$3A0 PPICR.3 PPICR.2 PPICR.1 PPICR.0 0000 0000
$3A1 PPJCR.3 PPJCR.2 PPJCR.1 PPJCR.0 0000 0000
$3A2 - - PPKCR.1 PPKCR.0 --00 --00
$3A3 TG1.3 TG1.2 TG1.1 TG1.0 xxxx uuuu
$3A4 TG1.7 TG1.6 TG1.5 TG1.4 xxxx uuuu
$3A5 TG1.11 TG1.10 TG1.9 TG1.8 xxxx uuuu
$3A6 TG2.3 TG2.2 TG2.1 TG2.0 xxxx uuuu
$3A7 TG2.7 TG2.6 TG2.5 TG2.4 xxxx uuuu
$3A8 TG2.11 TG2.10 TG2.9 TG2.8 xxxx uuuu
$3A9 TV1.3 TV1.2 TV1.1 TV1.0 xxxx uuuu
$3AA TG1EN TV1.6 TV1.5 TV1.4 xxxx uuuu
$3AB TV2.3 TV2.2 TV2.1 TV2.0 xxxx uuuu
$3AC TG2EN TV2.6 TV2.5 TV2.4 xxxx uuuu
$3AD - - A1 A0 --xx --uu
$3AE A5 A4 A3 A2 xxxx uuuu
$3AF A9 A8 A7 A6 xxxx uuuu
$3C0 T1S - - - 0--- u---
$3C1 LPS3 LPS2 LPS1 LPS0 0000 uuuu
$3C2 ACR3 CH3 - - 00-- uu--
Legend: x = unknown; u = unchanged; - = unimplemented read as '0'.
*, #: For the detail information, refer to the following table:
WDT Reset LVR Reset WDT Reset & LVR Reset Power on Reset/Pin Reset
* 0 1 1 0
# 1 0 1 0
4.2. Others Initial State:
Others After any Reset
Program Counter (PC) $000
CY Undefined
Accumulator (AC) Undefined
Data Memory Undefined

SH69P55A/K55A
15
5. System Clock and Oscillator
SH69P55A/69K55A has one clock source, which is determined in Code options. The oscillator generates the basic clock
pulses that provide the system clock to supply CPU and on-chip peripherals.
System clock fSYS = fOSC/4.
5.1. Instruction Cycle Time:
(1) 4/32.768kHz (≈122µs) for 32.768kHz oscillator.
(2) 4/8MHz (= 0.5µs) for 8 MHz oscillator.
5.2. Oscillator Type
(1) Crystal Oscillator: 32.768kHz or 400kHz - 8MHz
OSCI
OSCO
C1
C2
Crystal
PLL_C
(2) Ceramic Resonator: 400kHz - 8MHz
OSCI
OSCO
C1
C2
Ceramic
PLL_C
(3) RC Oscillator: 400kHz - 8MHz
OSCI
ROSC VDD
OSCO
PLL_C
External RC
(4) RC Oscillator: 4MHz
OSCI
OSCO
PLL_C
Internal RC
(5) PLL Oscillator (1, 2, 4, 8MHz)
OSCI
OSCO
C1
C2
32.768
kHz
PLL_C
C3 = 2200p
RPLL = 100K
Note:
- If the external RC oscillator is selected, OSCO pin is used as the I/O port (PORTC.1).
- If the internal RC oscillator is selected, OSCO pin is used as the I/O port (PORTC.1) and OSCI pin is used as the I/O port
(PORTC.2).
- If the PLL is disabled, PLL_C is used as the I/O port (PORTC.0).

SH69P55A/K55A
16
5.3. Control of Phase Locked Loop Clock Source (PLL)
A phase locked loop (PLL) is built in SH69P55A/69K55A, which can provide up to 8MHz clock source when the 32.768kHz
oscillator is selected. PLL control register can decide whether PLL enable or disable. When PLL is enabled, PORTC.0 is
shared as PLL capacitor connecting port, which is connected with a RC network. When PLL is disabled, PORTC.0 is shared
as a normal I/O.
PLL Control Register $16
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$16 FS1 FS0 OXS OXON R/W
Bit0: Turn on PLL register
Bit1: clock source select (1: PLL, 0: 32.768kHz) register
Bit3 - 2: PLL Frequency select register
X X X 0 R/W Turn off PLL
X X X 1 R/W Turn on PLL, when 32.768kHz oscillator is selected in code option
X X 0 X R/W Clock source is selected as 32.768kHz oscillator
X X 1 1 R/W Clock source is selected as PLL
0 0 1 1 R/W PLL provides 8.126MHz clock signal for clock source
(LVR voltage range must be selected as 4V in the code option)
0 1 1 1 R/W PLL provides 4.063MHz clock signal for clock source
1 0 1 1 R/W PLL provides 2.031MHz clock signal for clock source
1 1 1 1 R/W PLL provides 1.016MHz clock signal for clock source
Note:
1. Usage of PLL:
First, configure the FS1 and FS0 in PLL control register.
Second, set OXON = 1 and turn on the PLL.
Third, wait at least 2ms.
Last, set OXS = 1 and select PLL as the system clock source.
2. If LVR voltage range is selected as 2.5V in the code option, the PLL only provides 1, 2, 4MHz clock signal for clock source.
System Register $23
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$23 - FSTP - - R/W Bit2: 32.768kHz oscillator is closed in the stop
X 1 X X R/W 32.768kHz oscillator is closed in the stop, if 32.768kHz is selected
in the code option
X 0 X X R/W 32.768kHz oscillator is not closed in the stop, if 32.768kHz
oscillator is selected in the code option

SH69P55A/K55A
17
5.4. Capacitor Selection for Oscillator
Ceramic Resonators
Frequency C1 C2 Recommend Type Manufacturer
ZTB 455KHz Vectron International
455kHz 47 - 100pF 47 - 100pF ZT 455E Shenzhen DGJB Electronic Co.,Ltd.
ZTT 3.580M Vectron International
3.58MHz - - ZT 3.58M* Shenzhen DGJB Electronic Co.,Ltd.
ZTT 4.000M Vectron International
4MHz - - ZT 4M* Shenzhen DGJB Electronic Co.,Ltd.
*- The specified ceramic resonator has internal built-in load capacity
Crystal Oscillator
Frequency C1 C2 Recommend Type Manufacturer
DT 38 (φ3x8) KDS
32.768kHz 5 - 12.5pF 5 - 12.5pF φ3x8 - 32.768KHz Vectron International
HC-49U/S 4.000MHz Vectron International
4MHz 8 - 15pF 8 - 15pF 49S-4.000M-F16E Shenzhen DGJB Electronic Co.,Ltd.
HC-49U/S 8.000MHz Vectron International
8MHz 8 - 15pF 8 - 15pF 49S-8.000M-F16E Shenzhen DGJB Electronic Co.,Ltd.
Notes:
1. Capacitor values are used for design guidance only!
2. These capacitors were tested with the crystals listed above for basic start-up and operation. They are not optimized.
3. Be careful for the stray capacitance on PCB board, the user should test the performance of the oscillator over the expected
VDD and the temperature range for the application.
Before selecting crystal/ceramic, the user should consult the crystal/ceramic manufacturer for appropriate value of external
component to get best performance, visit http://www.sinowealth.com for more recommended manufactures

SH69P55A/K55A
18
6. I/O Port
The SH69P55A/69K55A provides 42 bi-directional I/O ports including one open-drain output. The PORT data is put in register
$08 - $0D and $38E - $392. The PORT control register ($18 - $1D and $393 - $397) controls the PORT as input or output.
Each I/O port (excluding those open drain output ports) contains pull-high resistor, which is controlled by the value of the
corresponding bit in the port pull-high control register ($398 - $3A2), independently.
When the port is selected as an input port, write “1” to the relevant bit in the port pull-high control register ($398 - $3A2)
could turn on the pull high resistor and write “0” could turn off the pull high resistor.
When the port is selected as output port, the pull high resistor will be turned off automatically, regardless the value of the
corresponding bit in the port pull high control register ($398 - $3A2).
When PORTB and PORTC are selected as the digital input direction, they can active port interrupt by falling edge (if port
interrupt is enabled).
System Register $08 - $0D, $38E - $392: Port Data Register (PDR)
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks
$08 PA.3 PA.2 PA.1 PA.0 R/W PORTA data register
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB data register
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC data register
$0B PD.3 PD.2 PD.1 PD.0 R/W PORTD data register
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE data register
$0D PF.3 PF.2 PF.1 PF.0 R/W PORTF data register
$38E PG.3 PG.2 PG.1 PG.0 R/W PORTG data register
$38F PH.3 PH.2 PH.1 PH.0 R/W PORTH data register
$390 PI.3 PI.2 PI.1 PI.0 R/W PORTI data register
$391 PJ.3 PJ.2 PJ.1 PJ.0 R/W PORTJ data register
$392 - - PK.1 PK.0 R/W PORTK data register
System Register $18 - $1D, $393 - $397: Port Control Register (PCR)
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks
$18 PACR.3 PACR.2 PACR.1 PACR.0 R/W PORTA input/output control register
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 R/W PORTB input/output control register
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 R/W PORTC input/output control register
$1B PDCR.3 PDCR.2 PDCR.1 PDCR.0 R/W PORTD input/output control register
$1C PECR.3 PECR.2 PECR.1 PECR.0 R/W PORTE input/output control register
$1D PFCR.3 PFCR.2 PFCR.1 PFCR.0 R/W PORTF input/output control register
$393 PGCR.3 PGCR.2 PGCR.1 PGCR.0 R/W PORTG input/output control register
$394 PHCR.3 PHCR.2 PHCR.1 PHCR.0 R/W PORTH input/output control register
$395 PICR.3 PICR.2 PICR.1 PICR.0 R/W PORTI input/output control register
$396 PJCR.3 PJCR.2 PJCR.1 PJCR.0 R/W PORTJ input/output control register
$397 - - PKCR.1 PKCR.0 R/W PORTK input/output control register
PA (/B/C/D/E/F/G/H/I/J) PCR.n, (n = 0, 1, 2, 3), PKPCR.n (n = 0, 1)
0: Set I/O as an input direction. (Power on initial)
1: Set I/O as an output direction.

SH69P55A/K55A
19
System Register $398 - $3A2: Port Pull-high Control Register (PPCR)
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks
$398 PPACR.3 PPACR.2 PPACR.1 PPACR.0 R/W PORTA pull high control register
$399 PPBCR.3 PPBCR.2 PPBCR.1 PPBCR.0 R/W PORTB pull high control register
$39A - PPCCR.2 PPCCR.1 PPCCR.0 R/W PORTC pull high control register
$39B PPDCR.3 PPDCR.2 PPDCR.1 PPDCR.0 R/W PORTD pull high control register
$39C PPECR.3 PPECR.2 PPECR.1 PPECR.0 R/W PORTE pull high control register
$39D PPFCR.3 PPFCR.2 PPFCR.1 PPFCR.0 R/W PORTF pull high control register
$39E PPGCR.3 PPGCR.2 PPGCR.1 PPGCR.0 R/W PORTG pull high control register
$39F PPHCR.3 PPHCR.2 PPHCR.1 PPHCR.0 R/W PORTH pull high control register
$3A0 PPICR.3 PPICR.2 PPICR.1 PPICR.0 R/W PORTI pull high control register
$3A1 PPJCR.3 PPJCR.2 PPJCR.1 PPJCR.0 R/W PORTJ pull high control register
$3A2 - - PPKCR.1 PPKCR.0 R/W PORTK pull high control register
PA (/B/D/E/F/G/H/I/J) CR.n, (n = 0, 1, 2, 3), PKCR.n (n = 0, 1), PCCR.n (n = 0, 1, 2)
0: Disable internal pull-high resistor. (Power on initial)
1: Enable internal pull-high resistor.
Equivalent Circuit for a Single I/O Pin
I/O Control
Register
DATA
Register
Pull high
Register
M2T1
0
1
s
READ DATA IN
DATA
READ
I/O Pad
Pull high
VDD
GND
VDD

SH69P55A/K55A
20
PORTA.3 - 0 can be shared with SEG4 - SEG1 signal output for LCD or LED display, KEY_I4 - KEY_I1 input for automatic
key scan.
PORTB.3 - 0 can be shared with ADC AN3 - 0 input channel.
PORTC.0 can be shared with PLL_C (code option), if PLL is enabled, a RC network must be connected with this port.
The OSCO pin can be shared with PORTC.1 if the SH69P55A/69K55A uses the external clock or the RC oscillator as the
system oscillation.
The OSCI pin can be shared with PORTC.2, if the SH69P55A/69K55A uses the internal RC oscillator as the system
oscillation.
The RESET pin can be shared with PORTC.3 controlled by the code option. PORTC.3 is open-drain output.
PORTD.3 - 0 can be shared with COM1 - COM4 signal output for LCD or LED display, KEY_O1 - KEY_O4 output for
automatic key scan.
PORTE.3 - 0 can be shared with COM5 - COM8 or SEG20 - SEG17 signal output for LCD display, and PORTE.3 - 2 can be
shared with COM5 - 6 signal output for LED display.
PORTF.3 - 0 can be shared with SEG8 - SEG5 signal output for LCD or LED display, and PORTF0 can be shared with
KEY_I5 input for automatic key scan.
PORTG.0 can be shared with PWM output.
PORTG.1 can be shared with TONE output or ADC AN9.
PORTG.2 can be shared with T0 input or external ADC VREF input.
PORTG.3 can be shared with T2 input or ADC AN8.
PORTH.3 - 0 can be shared with SEG16 - SEG13 signal output for LCD display.
PORTI.3 - 0 can be shared with SEG12 - SEG9 signal output for LCD display.
PORTJ.3 - 0 can be shared with ADC AN7 - 4 input channels.
IMPORTANT:
In 32pin package, PORTH.0, PORTH.1 and PORTI - K must be selected to be output ‘0’ (Port Control Register (PCR):
$394 = xx11B, $395 - $396 = 1111B, $397 = 0011B and Port Data Register (PDR): $38F = xx00B and $390 - $391 = 0000B,
$392 = 0000B).
In 28pin package, PORTD, PORTF, PORTH, PORTI.3 - 2 and PORTK must be selected to be output ‘0’ (Port Control
Register (PCR): $1B $1D, $394 = 1111B, $395 = 11xxB, $397 = 0011B and Port Data Register (PDR): $0B $0D, $38F =
0000B, $390 = 00xxB, $392 = 0000B).
In SH69P55A/69K55A, each output port contains a latch, which can hold the output data. Writing the port data register
(PDR) under the output mode can directly transfers data to the corresponding pin. All input ports do not have latches, so
the external input data should be held externally until the input data is get from outside. The contents of the port control
register (PCR) determines each bi-directional I/O port to be an input or output port, where writing ‘0’ to port control register
(PCR) represents the input mode and ‘1’ for the output mode. When a digital I/O port is selected to be an output port, the
value of the associated port bit actually represents the value of the output data latch, not the voltage on the pin. When a
digital I/O port is selected to be input, the value of the associated port bit represents the status on the corresponding pin.
The output data latch can be written all the while, regardless of the state of the port control register (PCR). Therefore, when
using ports in a mixture of input and output modes, the contents of the output latches for those ports that are selected as
inputs may be rewritten by execution of logical instructions. So it is strongly recommended that writing proper data to the
port data register (PDR) before changing the corresponding bits in the port control register (PCR) from the input mode to
the output mode can avoid glitches on the relevant pins.