Sino Wealth SH79F7416 User manual

SH79F7416
Enhanced 8051 Microcontroller with 4 channels UART and 3 channels PWM
1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 64K Bytes
RAM: internal 256 Bytes, external 4096 Bytes,LCD ram
40 Bytes
EEPROM-Like:bulid-in 4096 Bytes(code option)
Operation Voltage:
fOSC = 32.768kHz - 24MHz, VDD=2.0V -5.5V
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator:2MHZ-16MHz
- Ceramic oscillator:2MHZ-16MHz
- Internal RC oscillator: 24MHz(±1%)/128K
61 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Three 16-bit timer/counters T3 ,T4,T5
8 large current driver I/O(code option optional enhanced
or standardized or weakened)
Four 16-bit PCA0, PCA1,PCA2 and PCA3 each contain
two comparison/capture units
3channels 12-bits PWM timer
Interrupt sources:
-Timer 3/4/5
-INT0/1/2
- INT3: 8input
- INT4: 8input
-,CRC,ADC, LPD,SCM
- SPI, TWI, CRC, EUART0/1/2/3
- PEM0/1/2, PCA0/1/2/3
SPI (Master/slave Mode)
TWI (Master/slave Mode)
4 Enhanced UART (CMOS/TTL)(own baudrate
generator)
LCD driver
- 8 X 40dots (1/8 duty 1/4 bias)
- 6 X 40dots (1/6 duty 1/4 bias or 1/3 bias)
- 5 X 40dots (1/5 duty 1/3 bias)
- 4 X 40dots (1/4 duty 1/3 bias)
16 analog inputs 12-bit Analog Digital Converter
Internal Logic Configuration Module(LCM)
Low Power Detect (LPD) Module with 16 level
optional
Built-in CRC verification module, the verify size
can be selected
Support single line simulation and download
Built-in low voltage Reset (LVR) function (code
option)
- LVR voltage1: 4.1v
- LVR voltage2: 3.7v
- LVR voltage3: 2.8v
- LVR voltage3: 2.1v
CPU Machine period:
- 1 oscillator clock
Built-in Watch Dog Timer (WDT)
Built-in oscillator Warm-up timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package:
-LQFP64 7*7
2. General Description
The SH79F7416 is a high performance 8051 compatible micro-controller.The SH79F7416 can perform more fast
operation speed and higher calculation performance, if compare SH79F7416 with standard 8051 at same clock speed.
The SH79F7416 retains most features of the standard 8051. These features include internal 256 bytes RAM, INT0-INT4.
In addition,SH79F7416 provides external4096 bytes RAM.It also contains 64Kbytes Flash memory block for program storage.
The SH79F7416 not only include many standard communication modules, such as EUART/TWI/SPI and so on, but also
include LCD diver, ADC,PCA, PWM timer, ect.
In addition, the SH79F7416 also have CRC module, built in it.
1 V1.0

SH79F7416
3. Block Diagram
64K Bytes
Flash ROM
Internal 256 Bytes
External 4096Bytes
(Exclude System
Register)
Oscillator
Pipelined 8051 architecture
Timer3 (16bit)
Timer4 (16bit)
Timer5 (16bit)
Reset circuit RST
XTAL2
XTAL1
V
DD
External Interrupt
Power
Watch Dog
oscillator fail
detector
PWM 0, 1, 2
Internal
Oscillator
Port 3
Configuration I/Os
Port 4
Configuration I/Os
P1.0 - P1.7
P2.0 - P2.7
P0.0 - P0.7
Port 2
Configuration I/Os
P3.0 - P3.7
EUART0/1/2/3
12-bit ADC
Jtag ports
(for debug)
Port 5
Configuration I/Os
LCD Driver COM1 - 8
SEG1 - 40
Port 1
Configuration I/Os
P4.0 - P4.7
Port 0
Configuration I/Os
P5.0 - P5.7
SPI
SCM
PCA 0, 1, 2, 3
CRC
Port 6
Configuration I/Os
Port 7
Configuration I/Os
P6.0 - P6.7
P7.0 - P7.4
TWI
LPD
2

SH79F7416
4. Pin Configration
4.1 LQFP64ackage
SH79F7416
30
31
32
17
29
28
27
26
25
24
23
22
21
20
19
18
52
53
54
55
56
57
58
59
60
61
62
63
64
49
50
51
38 37 36 35 34 3339404142434445464748
12345678910 11 12 13 14 15 16
COM4/P4.5
COM5/P4.4
P1.7/INT41/AN4/XTAL1 P1.3/SEG11
P1.4/SEG10
VDD
GND
COM3/P4.6
P7.3/INT33/SEG24/P3CEX0/AN0
P7.2/SEG25/ECI3/TDO
P7.1/SEG26/P1CEX1/TMS
P7.0/SEG27/P1CEX0/TDI
P6.7/SEG28/ECI1/TCK
P6.6/SEG29
P6.5/INT34/SEG30
P6.4/INT35/SEG31
P6.3/SEG32/T4
P6.2/INT47/SEG33
P6.1/SEG34/ECI2
P6.0/SEG35/P2CEX1/AN14
INT46/P3.3
P3.2
P3.1
P3.0
AN6/INT40/P3.5
SWE/INT1/P5.2
VIN/AN10/INT0/P5.1
RXD3/INT43/SEG39/P5.4
TXD3/SEG40/P5.3
COM8/P4.1
COM7/P4.2
P0.6/SEG16
SEG7/P2.1
P1.6/SEG8
XTAL2/AN5/INT42/P2.0
P0.5/INT30/SEG17/PWM2
P0.4/INT31/SEG18/AN3
P0.3/SEG19/SCK P1.2/SEG12 P1.1/SEG13 P1.0/SEG14
SEG5/P2.3
COM1/P5.0
COM2/P4.7
SEG4/P2.4
SEG3/P2.5
SEG2/P2.6
SEG1/P2.7
SEG6/P2.2
COM6/P4.3
AN9/INT45/P4.0
P5.5/INT37/SEG38/AN11
P5.6/INT36/SEG37/AN12
P5.7/SEG36/P2CEX0/AN13
P0.7/SEG15
P0.2/SEG20/SS P0.1/SEG21/MISO P0.0/SEG22/AN2/MOSI
P7.4/INT32/SEG23/T3/P3CEX1AN1
P1.5/SEG9
AVREF/INT44/P3.4
RESET
AN8/P3.7
AN7/P3.6
Note:
In pin designation, the pin function written on the outermostside has the highest priority and the innermost pin function has
the lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a
pin of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority
function of the pin can the corresponding pin be released as a low-priority port.
3

SH79F7416
LCM (logical function configuration module) pin allocation table
Function
UART0
UART1
UART2
TWI
PWM0
PWM1
INT2
PCA0
Pin
RXD0
TXD0
RXD1
TXD1
RXD2
TXD2
SCL
SDA
PWM0
PWM1
INT2
P0CEX0
P0CEX1
ECI0
P0.0
P0.1
P0.2
P0.3
P0.4
● ●

●●
P0.5 ●●●
P0.6 ●
P0.7
●● ●
P1.0 ●●●
P1.1
●●
P1.2
●●
P1.3
P1.4
P1.5 ●
P1.6 ●
P1.7
●
P2.0 ●
P2.1
P2.2
P2.3
P2.4 ●
P2.5
● ●
P2.6 ●●●●
P2.7 ●●●●
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6 
P3.7 ●
P4.0
P4.1
● ● ●●

●
●
P4.2 ●●●●●●●
P4.3
●

●

P4.4 ●●●
P4.5 ●●●
P4.6
●● ●
P4.7 ●
4

SH79F7416
(continue)
Function
UART0
UART1
UART2
TWI
PWM0
PWM1
INT2
PCA0
Pin
RXD0
TXD0
RXD1
TXD1
RXD2
TXD2
SCL
SDA
PWM0
PWM1
INT2
P0CEX0
P0CEX1
ECI0
P5.0
●
P5.1
P5.2
P5.3
P5.4
P5.5
● ● ● ● ● ●
P5.6
● ● ● ● ● ●●
P5.7
● ● ●
P6.0
●● ●
P6.1
●● ● ● ●
P6.2
●● ● ●●
P6.3
●
P6.4
P6.5
P6.6
●
P6.7

●

P7.0
●

●
P7.1
P7.2
P7.3
● ●
P7.4
● ●
*Note: In Table, the black dots(
● ) respected the functions which can be configurated for the pin; The black square(  )
respected the default function pin of logic configuration module after reset. The black square (
 ) can be configurated to
corresponding black dots(
● ) pin through LCM.
The priority of LCM is lower than all the other function of the pin(except IO function
5

SH79F7416
引脚功能
Pin No.
Type Default
(LQFP64)
1 AN6/INT40/P3.5 P3.5
2 AN7/P3.6 P3.6
3 AN8/P3.7 P3.7
4 AN9/INT45/P4.0 P4.0
5 COM8/P4.1 P4.1
6 COM7/P4.2 P4.2
7 COM6/P4.3 P4.3
8 COM5/P4.4 P4.4
9 COM4/P4.5 P4.5
10 COM3/P4.6 P4.6
11 COM2/P4.7 P4.7
12 COM1/P5.0 P5.0
13 VIN/AN10/INT40/P5.1 P5.1
14 SWE/INT1/P5.2 P5.2
15 TXD3/SEG40/P5.3 P5.3
16 RXD3/INT43/SEG39/P5.4 P5.4
17 AN11/SEG38/INT37/P5.5 P5.5
18 AN12/SEG37/INT36/P5.6 P5.6
19 AN13/P2CEX0/SEG36/P5.7 P5.7
20 AN14/P2CEX1/SEG35/P6.0 P6.0
21 ECI2/SEG34/P6.1 P6.1
22 SEG33/INT47/P6.2 P6.2
23 T4/SEG32/P6.3 P6.3
24 SEG31/INT35/P6.4 P6.4
25 SEG30/INT34/P6.5 P6.5
26 SEG29/P6.6 P6.6
27 TCK/ECI1/SEG28/P6.7 P6.7
28 TDI/P1CEX0/SEG27/P7.0 P7.0
29 TMS/P1CEX1/SEG26/P7.1 P7.1
30 TDO/ECI3/SEG25/P7.2 P7.2
31 AN0/P3CEX0/SEG24/INT33/P7.3 P7.3
32 AN1/P3CEX1/T3/SEG23/INT32/P7.4 P7.4
33 MOSI/AN2/SEG22/P0.0 P0.0
34 MISO/SEG21/P0.1 P0.1
35 SS/SEG20/P0.2 P0.2
36 SCK/SEG19/P0.3 P0.3
6

SH79F7416
续上表
Pin No.
Type Default
(LQFP64)
37 AN3/SEG18/INT31/P0.4 P0.4
38 PWM2/SEG17/INT30/P0.5 P0.5
39 SEG16/P0.6 P0.6
40 SEG15/P0.7 P0.7
41 SEG14/P1.0 P1.0
42 SEG13/P1.1 P1.1
43 SEG12/P1.2 P1.2
44 SEG11/P1.3 P1.3
45 SEG10/P1.4 P1.4
46 SEG9/P1.5 P1.5
47 SEG8/P1.6 P1.6
48 XTAL1/AN4/INT41/P1.7 P1.7 port or oscillator input pin (code option
control)
49 XTAL2/AN5/INT42/P2.0 P2.0 mouth or the oscillator output pin (code
option control)
50 SEG7/P2.1 P2.1
51 SEG6/P2.2 P2.2
52 SEG5/P2.3 P2.3
53 SEG4/P2.4 P2.4
54 SEG3/P2.5 P2.5
55 SEG2/P2.6 P2.6
56 SEG1/P2.7 P2.7
57
RST
————
RST
————
58 GND GND
59 VDD VDD
60 P3.0 P3.0
61 P3.1 P3.1
62 P3.2 P3.2
63 INT46/P3.3 P3.3
64 AVREF/INT44/P3.4 P3.4
7

SH79F7416
5. Pin Function and Pin Description
5.1 Pin Function
Pin No. Type Description
I/O PORT
P0.0 - P0.7
I/O
8-bit bi-directional I/O port
P1.0 - P1.7 I/O 8-bit bi-directional I/O port
P2.0 - P2.7 I/O 8-bit bi-directional I/O port
P3.0 - P3.7
I/O
8-bit bi-directional I/O port
P4.0 - P4.7
I/O
8-bit bi-directional I/O port
P5.0 – P5.7
I/O
8-bit bi-directional I/O port
P6.0 – P6.7 I/O 8-bit bi-directional I/O port
P7.0 – P7.4 I/O 5-bit bi-directional I/O port
Timer
/Counter
T3
I
Timer3
T4
I/O
The external input/compare pin for timer 4
P
WM Controller
PWM0
O
12-bit output pin for PWM0
PWM1 O
12-bit output pin for PWM1
PWM2 O
12-bit output pin for PWM1
EUART
RXD0/1/2/3
I
EUART0/1/2/3 data input
TXD0/1/2/3
O
EUART0/1/2/3 data output
TWI
SCL
I/O
TWI CLK pin
SDA
I/O
TWI data input / output pin
SPI
MOSI I/O SPI master output slave input
MISO I/O SPI master input slave output
SCK I/O SPI serial clock
SS
——
I SPI slave select
ADC
AN0- AN14
I
No.12 ADC input pin
AVREF
I
ADC/DAC external analog reference voltage pin
LCD
Controller
COM1 – COM8
O
Common signal output for LCDdisplay
SEG1-SEG40 O LCD Segment signal output
8

SH79F7416
(continue)
Interrupt & Reset & Clock & Power
INT0 – INT2
I
External interrupt 0-2 input source
INT30 – INT37 I External interrupt 30-37 input source
INT40 - INT47
I
External interrupt 40-47 input source
RST
———— I
The device will be reset byA low voltage on this pin longer than 10us, an internal resistor
about 30kΩ to VDD, So using only an external capacitor to GND can cause a PIN reset.
XTAL1 I external oscillator/clock input
XTAL2 O
external oscillator output/bi-directional I/O port
GND
P
Ground
VDD
P
Power source(2.0 - 5.5V)
PCA
Controller
P0CEX0 I/O Input /output pin for PCA0 module 0
P0CEX1 I/O Input /output pin for PCA0 module 1
ECI0 I The external clock input for PCA0
P1CEX0 I/O Input /output pin for PCA1 module 0
P1CEX1 I/O Input /output pin for PCA1 module 1
ECI1 I The external clock input for PCA1
P2CEX0 I/O Input /output pin for PCA2 module 0
P2CEX1 I/O Input /output pin for PCA2 module 1
ECI2 I The external clock input for PCA2
P3CEX0 I/O Input /output pin for PCA3 module 0
P3CEX1 I/O Input /output pin for PCA3 module 1
ECI3 I The external clock input for PCA3
LPD
VIN I LPD detection voltage input port
Single line simulation interface
SWE(P5.2) I/O Single-line simulation interface. If the chip VDDpower-on or power-
down slope is greater
than 500ms/V, it is recommended to connect 47K~1M resistors to GND or VDD to
increase the stability ofthe chip .
Programming interface
TDO(P6.7)
O
Debug interface: Test data out
TMS(P7.0) I Debug interface: Test mode select
TDI(P7.1)
I
Debug interface: Test data in
TCK(P7.2)
I
Debug interface: Test clock in
Note:
When P6.7 – P7.2, P5.2 used as debug interface, functions of P6.7 – P7.2, P5.2 are blocked.
9

SH79F7416
6. SFR Mapping
The SFR of the SH79F7416 fall into the following categories:
CPU Core Registers:ACC,B,PSW,SP,DPL,DPH
Enhanced CPU Core Registers: AUXC,DPL1,DPH1,INSCON,XPAGE
Power and Clock Control Registers: PCON,SUSLO
Flash Registers:IB_OFFSET,IB_DATA,IB_CON1,IB_CON2,IB_CON3,IB_CON4,IB_CON5,FLASHCON
Data Memory Register:XPAGE
Hardware Watchdog Timer Registers:RSTSTAT
System Clock Control Registers: CLKCON
Interrupt System Registers:: IEN0, IEN1, IEN2, IEN3, IENC, IENC1, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1, EXCON, TCON,
EXF2, EXCON1
I/O Port Registers: P0, P1, P2, P3, P4, P5, P6, P7, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P6CR, P7CR,P0PCR,
P1PCR, P2PCR, P3PCR, P4PCR, P5PCR, P6PCR, P7PCR, PIMS0，PIMS1，PIMS2，PIMS3
Timer Registers: T3CON, TH3, TL3, T4CON, TH4, TL4, T5CON, TH5, TL5
PCA0,1,2,3 Registers:PCACON，P0TOPL，P0TOPH，P0CMD，P0CF，P0CPM0，P0CPM1，P0CPL0，P0CPH0，P0CPL1，
P0CPH1，P0FORCE
P1TOPL，P1TOPH，P1CMD，P1CF，P1CPM0，P1CPM1，P1CPL0，P1CPH0，P1CPL1，
P1CPH1，
P1FORCE
P2TOPL，P2TOPH，P2CMD，P2CF，P2CPM0，P2CPM1，P2CPL0，P2CPH0，P2CPL1，P2CPH1，
P2FORCE
P3TOPL，P3TOPH，P3CMD，P3CF，P3CPM0，P3CPM1，P3CPL0，P3CPH0，P3CPL1，P3CPH1，
P3FORCE
EUART Registers: PCON，SCON，SBUF，SADEN，SADDR，SBRTL，SBRTH，SFINE，SCON1，SBUF1，SADEN1，
SADDR1，SBRTL1，SBRTH1，SFINE1，SCON2，SBUF2，SADEN2，SADDR2，SBRTL2，SBRTH2，SFINE2，SCON3，
SBUF3，SADEN3，SADDR3，SBRTL3，SBRTH3，SFINE3
SPI Register:SPCON,SPSTA,SPDAT
TWI Register: TWICON, TWIPCR, TWITOUT, TWISTA, TWTFREE, TWIBR, TWIADR, TWIDAT, TWIAMR
ADC Register: ADCON1, ADCON2, ADT, ADCH1, ADCH2, ADDxL, ADDxH, SEQCON, SEQCHX
LCD Registers:LCDCON，DISPCON1，LCDSEG0，LCDSEG1，LCDSEG2，LCDSEG3，LCDSEG4，COMSEL
LCM Register: UART0CR，UART1CR，UART2CR，TWICR，PWMCR，CEXCR，ECICR
PWM Register: PWM0CON，PWM1CON，PWM2CON，PWM0PL，PWM0PH，PWM0DL，PWM0DH，PWM1PL，
PWM1PH，PWM1DL，PWM1DH，PWM2PL，PWM2PH，PWM2DL，PWM2DH
LPD Register: LPDCON, LPDSEL
CRC Register: CRCCON，CRCDL，CRCDH，CRCSTAL，CRCSTAH，CRCSTOL，CRCSTOH
WDT Register: RSTSTAT
10

SH79F7416
Table 6.1 C51 Core SFRs
symbol
Address
Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ACC E0H Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
B F0H B Register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
AUXC F1H C Register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0
PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P
SP 81H Stack Pointer 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
DPL 82H Data Pointer Low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0
DPH 83H Data Pointer High byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0
DPL1 84H Data Pointer 1 Low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPH1 85H Data Pointer 1 High byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
INSCON 86H Data pointer select 00--00-0 BKS1 BKS0 - - DIV MUL - DPS
Table 6.2 Power and Clock control SFRs
symbol Address Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON 87H Power Control 00-0000 SMOD SSTAT - - GF1 GF0 PD IDL
SUSLO 8EH Suspend Mode Control 00000000
SUSLO.7
SUSLO.6
SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0
11

SH79F7416
Table 6.3 Flash control SFRs
symbol
Address
Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_OFF
SET
FBH
Bank0
Offset Register for Programming 00000000
IB_OFF
SET.7
IB_OFF
SET.6
IB_OFF
SET.5
IB_OFF
SET.4
IB_OFF
SET.3
IB_OFF
SET.2
IB_OFF
SET.1
IB_OFF
SET.0
IB_DATA
FCH
Bank0
Data Register for Programming 00000000
IB_DATA.
7
IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
IB_CON1
F2H
Bank0
Flash Memory Control Register 1 00000000
IB_CON1.
7
IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0
IB_CON2
F3H
Bank0
Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0
IB_CON3 F4H
Bank0 Flash Memory Control Register 3
----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0
IB_CON4 F5H
Bank0 Flash Memory Control Register 4
----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0
IB_CON5 F6H
Bank0 Flash Memory Control Register 5
----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
XPAGE
F7H
Bank0
Programming address selection
register
00000000 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
FLASHCON
A7H
Bank0
Flash access control ------00 - - - - - - CRC_FAC FAC
Table 6.4 WDT SFR
symbol
Address
Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTSTAT
B1H
Bank0 Watchdog Timer Control 0-000000* WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
Note: * : RSTSTAT initial value is determined by different RESET.
Table 6. 5 CLKCON SFR
symbol
Address
Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKCON B2H
Bank0 System Clock Control Register 111000-- 32k_ SPDUP CLKS1 CLKS0 SCMIF HFON FS - -
12

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Table 6.6 Interrupt SFRs
symbol Address Name
POR/WDT/LVR
/PIN Reset
Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN0
A8H
Bank0
Interrupt Enable Control 0 00000000 EA EADC ET3 ES0 EPCA1 EX1 EPCA0 EX0
IEN1
A9H
Bank0
Interrupt Enable Control 1 00000000 EX3 ESPI EX2 EPCA0 EX4 ES3 ETWI
IEN2 AAH
Bank0 Interrupt Enable Control 2 --000000 - EPWM1- EPCA1 EPWM0 ECRC ET5 ET3 ET4
IEN3 A1H
Bank0 Interrupt Enable Control 3 -----000 EPCA2 EPWM2 ESCM ELPD
IENC BAH
Bank0 Interrupt channel enable control 00000000 EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40
IENC1 C2H
Bank0 Interrupt channel enable control 1
00000000 EXS37 EXS36 EXS35 EXS34 EXS33 EXS32 EXS31 EXS30
IPH0 B4H
Bank0
Interrupt Priority Control High 0 00000000 PINTH PADCH PT3H PSH PT5H PX1H PT2H PX0H
IPL0
B8H
Bank0
Interrupt Priority Control Low 0 00000000 PINTL PADCL PT3L PSL PT5L PX1L PT2L PX0L
IPH1 B5H
Bank0 Interrupt Priority Control High 1 00000000 PINTH PLPDH PEX2H PPCA1H PX4H PT4H PTWIH
IPL1
B9H
Bank0
Interrupt Priority Control Low 1 00000000 PSCML PLPDL PEX2L PPCA1L PX4L PT4L PTWIL
EXF0 D1H
Bank0 External interrupt Control 0 000000-0 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 - IE2
EXF1 D8H
Bank0 External interrupt Control 1 00000000 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40
EXF2
E8H
Bank0
External interrupt Control 2 00000000 IF37 IF36 IF35 IF34 IF33 IF32 IF31 IF30
EXCON 8BH
Bank0
External interrupt sampling control
00000000 I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0
EXCON1 A6H
Bank0
External interrupt sampling control
1
----0000 - - - - I2PS1 I2PS0 I2SN1 I2SN0
TCON 88H
Bank0
External Interrupt 0/1 Control Mode
Register
----0000 - - - - IE1 IT1 IE0 IT0
13

SH79F7416
Table 6.7 TWI SFRs
symbol Add
ress
Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TWICON C8H
Bank0 TWI Control register 00000000 TOUT ENTWI STA STO TWINT AA TFREE EFREE
TWISTA DFH
Bank0 TWII status register 11111000 TWISTA.7 TWISTA.6 TWISTA.5 TWISTA.4 TWISTA.3 CR.1 CR.0 ETOT
TWIBR 8AH
Bank0 TWI bit rate register 00000000 TWIBR.7 TWIBR.6 TWIBR.5 TWIBR.4 TWIBR.3 TWIBR.2 TWIBR.1 TWIBR.0
TWITOUT
C9H
Bank0
Timeout For Bus Low level
Count Register
00----0- CNT1 CNT0 - - - - TWIPCR -
TWIDAT
8DH
Bank0
TWI data register 00000000 TWIDAT.7 TWIDAT.6 TWIDAT.5 TWIDAT.4 TWIDAT.3 TWIDAT.2 TWIDAT.1 TWIDAT.0
TWIADR 8CH
Bank0 TWI address register 00000000 TWA.6 TWA.5 CTRTWA.4 TWA.3 TWA.2 TWA.1 TWA.0 GC
TWIAMR 8FH
Bank0 TWI address mask register 0000000- TWIAMR.7 TWIAMR.6 TWIAMR.5 TWIAMR.4 TWIAMR.3 TWIAMR.2 TWIAMR.1 CTRTOUT-
TWTFREE
89H
Bank0
Timeout For Bus High level
Count Register
00000000 TWTFREE.7 TWTFREE.6 TWTFREE.5 TWTFREE.4 TWTFREE.3 TWTFREE.2 TWTFREE.1 TWTFREE.0
Table 6.8 Port SFRs
symbol Address Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3Bit2 Bit1 Bit0
P0 80H
Bank0
8-bit Port0
00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1 90H
Bank0 8-bit Port1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2 A0H
Bank0 8-bit Port2 00000000 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P3 B0H
Bank0 8-bit Port3 00000000 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P4 C0H
Bank0 8-bit Port4 00000000 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
P5 80H
Bank1 8-bit Port5 00000000 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
P6 90H
Bank1 8-bit Port6 00000000 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
P7 A0H
Bank1 5-bit Port7 ---00000 - - - P7.4 P7.3 P7.2 P7.1 P7.0
P0CR E1H
Bank0 Port0 input/output direction control
00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR E2H
Bank0 Port1 input/output direction control
00000000 P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
14

SH79F7416
P2CR E3H
Bank0 Port2 input/output direction control
00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
(continue)
P2CR
E3H
Bank0
Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR
E4H
Bank0
Port3 input/output direction control 00000000 P3CR.7 P3CR.6 P3CR.5 P3CR.4 P3CR.3 P3CR.2 P3CR.1 P3CR.0
P4CR
E5H
Bank0
Port4 input/output direction control 00000000 P4CR.7 P4CR.6 P4CR.5 P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0
P5CR
E1H
Bank1
Port5 input/output direction control 00000000 P5CR.7 P5CR.6 P5CR.5 P5CR.4 P5CR.3 P5CR.2 P5CR.1 P5CR.0
P6CR
E2H
Bank1
Port6 input/output direction control 00000000 P6CR.7 P6CR.6 P6CR.5 P6CR.4 P6CR.3 P6CR.2 P6CR.1 P6CR.0
P7CR
E3H
Bank1
Port7 input/output direction control ---00000 - - - P7CR.4 P7CR.3 P7CR.2 P7CR.1 P7CR.0
P0PCR
E9H
Bank0
Internal pull-high enable for Port0 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR
EAH
Bank0
Internal pull-high enable for Port1 00000000 P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR
EBH
Bank0
Internal pull-high enable for Port2 00000000 P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR
ECH
Bank0
Internal pull-high enable for Por3 00000000 P3PCR.7 P3PCR.6 P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 P3PCR.1 P3PCR.0
P4PCR
EDH
Bank0
Internal pull-high enable for Port4 00000000 P4PCR.7 P4PCR.6 P4PCR.5 P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0
P5PCR
E9H
Bank1
Internal pull-high enable for Port5 00000000 P5PCR.7 P5PCR.6 P5PCR.5 P5PCR.4 P5PCR.3 P5PCR.2 P5PCR.1 P5PCR.0
P6PCR
EAH
Bank1
Internal pull-high enable for Port6 00000000 P6PCR.7 P6PCR.6 P6PCR.5 P6PCR.4 P6PCR.3 P6PCR.2 P6PCR.1 P6PCR.0
P7PCR
EBH
Bank1
Internal pull-high enable for Port7 ---00000 - - - P7PCR.4 P7PCR.3 P7PCR.2 P7PCR.1 P7PCR.0
PIMS0
BAH
Bank1
Port input mode selection 00000000 P04S P05S P07S P10S P11S P12S P17S P20S
PIMS1
BBH
Bank1
Port input mode selection 00000000 P26S P27S P41S P42S P43S P44S P45S P46S
PIMS2
BCH
Bank1
Port input mode selection 00000000 P55S P56S P63S P64S P67S P70S P71S P72S
PIMS3
BDH
Bank1
Port input mode selection ------00 - - - - - - P54S P53S
15

SH79F7416
Table 6.9 Timer SFRs
Mnem Add Name
POR/WDT/LVR
/PIN Reset
Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
T3CON 88H
Bank1 Timer/Counter3 Control 0-00-000 TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0
TL3 8CH
Bank1 Timer/Counter3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0
TH3 8DH
Bank1 Timer/Counter3 High Byte 00000000 TH3.7 TH3.6 TH3.5 TH3.4 TH3.3 TH3.2 TH3.1 TH3.0
T4CON C8H
Bank1 Timer/Counter4 Control 00000000 TF4 TC4 T4PS1 T4PS0 T4M1 T4M0 TR4 T4CLKS
TL4 CCH
Bank1 Timer/Counter4 Low Byte 00000000 TL4.7 TL4.6 TL4.5 TL4.4 TL4.3 TL4.2 TL4.1 TL4.0
TH4 CDH
Bank1 Timer/Counter4 High Byte 00000000 TH4.7 TH4.6 TH4.5 TH4.4 TH4.3 TH4.2 TH4.1 TH4.0
T5CON C0H
Bank1 Timer/Counter5 Control 0-00--0- TF5 - T5PS1 T5PS0 - - TR5 -
TL5 CEH
Bank1 Timer/Counter5 Low Byte 00000000 TL5.7 TL5.6 TL5.5 TL5.4 TL5.3 TL5.2 TL5.1 TL5.0
TH5 CFH
Bank1 Timer/Counter5 High Byte 00000000 TH5.7 TH5.6 TH5.5 TH5.4 TH5.3 TH5.2 TH5.1 TH5.0
Table 6.10 PCA SFRs
Mnem Add Name
POR/WDT/LVR
/PIN Reset
Val e
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0CF 98H
Bank2
PCA0 Flag register 0-----00 CF0 - - - - - P0CCF1 P0CCF0
P1CF 88H
Bank2 PCA1 Flag register 0-----00 CF1 - - - - - P1CCF1 P1CCF0
P2CF D8H
Bank2 PCA2 Flag register 0-----00 CF2 - - - - - P2CCF1 P2CCF0
P3CF C0H
Bank2 PCA3 Flag register 0-----00 CF3 - - - - - P3CCF1 P3CCF0
P0CMD 99H
Bank2 PCA0 Mode register 00---000 ECF0 P0SDEN - - - P0CPS2 P0CPS1 P0CPS0
P1CMD 89H
Bank2 PCA1 Mode register 00---000 ECF1 P1SDEN - - - P1CPS2 P1CPS1 P1CPS0
16

SH79F7416
P2CMD 8AH
Bank2 PCA2 Mode register 00---000 ECF2 P2SDEN - - - P2CPS2 P2CPS1 P2CPS0
17

SH79F7416
(continue)
P3CMD 8BH
Bank2
PCA3 Mode register 00---000 ECF3 P3SDEN - - - P3CPS2 P3CPS1 P3CPS0
P0CPM0 9AH
Bank2
PCA0 Capture /Compare Module 0
register 00000000 P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0
P0CPM1 9BH
Bank2 PCA0 Capture /Compare Module1 register 00000000 P0SMP1 P0SMN1 P0FSP1 P0FSN1 P0ECOM1 P0TCP1 P0MAT1 P0ECCF1
P1CPM0 B3H
Bank2 PCA1
Capture /Compare Module 0
register 00000000 P1SMP0 P1SMN0 P1FSP0 P1FSN0 P1ECOM0 P1TCP0 P1MAT0 P1ECCF0
P1CPM1 ABH
Bank2 PCA1 Capture /Compare Module1 register 00000000 P1SMP1 P1SMN1 P1FSP1 P1FSN1 P1ECOM1 P1TCP1 P1MAT1 P1ECCF1
P2CPM0 C9H
Bank2 PCA2
Capture /Compare Module 0
register 00000000 P2SMP0 P2SMN0 P2FSP0 P2FSN0 P2ECOM0 P2TCP0 P2MAT0 P2ECCF0
P2CPM1
CAH
Bank2
PCA2 Capture /Compare Module1
register 00000000 P2SMP1 P2SMN1 P2FSP1 P2FSN1 P2ECOM1 P2TCP1 P2MAT1 P2ECCF1
P3CPM0 CBH
Bank2 PCA3
Capture /Compare Module 0
register 00000000 P3SMP0 P3SMN0 P3FSP0 P3FSN0 P3ECOM0 P3TCP0 P3MAT0 P3ECCF0
P3CPM1 CCH
Bank2 PCA3 Capture /Compare Module1 register 00000000 P3SMP1 P3SMN1 P3FSP1 P3FSN1 P3ECOM1 P3TCP1 P3MAT1 P3ECCF1
P0TOPL 9EH
Bank2
PCA0 Count Maximum Low Byte 11111111 P0TOPL.7 P0TOPL.6 P0TOPL.5 P0TOPL.4 P0TOPL.3 P0TOPL.2 P0TOPL.1 P0TOPL.0
P1TOPL AEH
Bank2 PCA1 Count Maximum Low Byte 11111111 P1TOPL.7 P1TOPL.6 P1TOPL.5 P1TOPL.4 P1TOPL.3 P1TOPL.2 P1TOPL.1 P1TOPL.0
P2TOPL B6H
Bank2 PCA2 Count Maximum Low Byte 11111111 P2TOPL.7 P2TOPL.6 P2TOPL.5 P2TOPL.4 P2TOPL.3 P2TOPL.2 P2TOPL.1 P2TOPL.0
P3TOPL A6H
Bank2 PCA3 Count Maximum Low Byte 11111111 P3TOPL.7 P3TOPL.6 P3TOPL.5 P3TOPL.4 P3TOPL.3 P3TOPL.2 P3TOPL.1 P3TOPL.0
P0TOPH 9FH
Bank2 PCA0 Count Maximum High Byte 11111111 P0TOPH.7 P0TOPH.6 P0TOPH.5 P0TOPH.4 P0TOPH.3 P0TOPH.2 P0TOPH.1 P0TOPH.0
P1TOPH AFH
Bank2 PCA1 Count Maximum High Byte 11111111 P1TOPH.7 P1TOPH.6 P1TOPH.5 P1TOPH.4 P1TOPH.3 P1TOPH.2 P1TOPH.1 P1TOPH.0
P2TOPH B7H
Bank2 PCA2 Count Maximum High Byte 11111111 P2TOPH.7 P2TOPH.6 P2TOPH.5 P2TOPH.4 P2TOPH.3 P2TOPH.2 P2TOPH.1 P2TOPH.0
P3TOPH A7H
Bank2 PCA3 Count Maximum High Byte 11111111 P3TOPH.7 P3TOPH.6 P3TOPH.5 P3TOPH.4 P3TOPH.3 P3TOPH.2 P3TOPH.1 P3TOPH.0
P0CPL0 9CH
Bank2 PCA0 capture/compare module 0 low byte 00000000 P0CPL0.7 P0CPL0.6 P0CPL0.5 P0CPL0.4 P0CPL0.3 P0CPL0.2 P0CPL0.1 P0CPL0.0
P0CPH0 9DH
Bank2 PCA0 capture/compare module 0 high byte 00000000 P0CPH0.7 P0CPH0.6 P0CPH0.5 P0CPH0.4 P0CPH0.3 P0CPH0.2 P0CPH0.1 P0CPH0.0
18

SH79F7416
(continue)
P0CPL1 ACH
Bank2
PCA0 capture/compare module 1
low byte
00000000 P0CPL1.7 P0CPL1.6 P0CPL1.5 P0CPL1.4 P0CPL1.3 P0CPL1.2 P0CPL1.1 P0CPL1.0
P0CPH1 ADH
Bank2 PCA0 capture/compare module 1 high byte 00000000 P0CPH1.7 P0CPH1.6 P0CPH1.5 P0CPH1.4 P0CPH1.3 P0CPH1.2 P0CPH1.1 P0CPH1.0
P1CPL0 F2H
Bank2 PCA1 capture/compare module 0 low byte 00000000 P1CPL0.7 P1CPL0.6 P1CPL0.5 P1CPL0.4 P1CPL0.3 P1CPL0.2 P1CPL0.1 P1CPL0.0
P1CPH0 F3H
Bank2 PCA1 capture/compare module 0 high byte 00000000 P1CPH0.7 P1CPH0.6 P1CPH0.5 P1CPH0.4 P1CPH0.3 P1CPH0.2 P1CPH0.1 P1CPH0.0
P1CPL1 F4H
Bank2 PCA1 capture/compare module 1 low byte 00000000 P1CPL1.7 P1CPL1.6 P1CPL1.5 P1CPL1.4 P1CPL1.3 P1CPL1.2 P1CPL1.1 P1CPL1.0
P1CPH1 F5H
Bank2 PCA1 capture/compare module 1 high byte 00000000 P1CPH1.7 P1CPH1.6 P1CPH1.5 P1CPH1.4 P1CPH1.3 P1CPH1.2 P1CPH1.1 P1CPH1.0
P2CPL0
ECH
Bank2
PCA2 capture/compare module 0
low byte 00000000 P2CPL0.7 P2CPL0.6 P2CPL0.5 P2CPL0.4 P2CPL0.3 P2CPL0.2 P2CPL0.1 P2CPL0.0
P2CPH0 EDH
Bank2 PCA2 capture/compare module 0 high byte 00000000 P2CPH0.7 P2CPH0.6 P2CPH0.5 P2CPH0.4 P2CPH0.3 P2CPH0.2 P2CPH0.1 P2CPH0.0
P2CPL1 EEH
Bank2 PCA2 capture/compare module 1 low byte 00000000 P2CPL1.7 P2CPL1.6 P2CPL1.5 P2CPL1.4 P2CPL1.3 P2CPL1.2 P2CPL1.1 P2CPL1.0
P2CPH1 EFH
Bank2
PCA2 capture/compare module 1
high byte
00000000 P2CPH1.7 P2CPH1.6 P2CPH1.5 P2CPH1.4 P2CPH1.3 P2CPH1.2 P2CPH1.1 P2CPH1.0
P3CPL0 E4H
Bank2 PCA3 capture/compare module 0 low byte 00000000 P3CPL0.7 P3CPL0.6 P3CPL0.5 P3CPL0.4 P3CPL0.3 P3CPL0.2 P3CPL0.1 P3CPL0.0
P3CPH0 E5H
Bank2 PCA3 capture/compare module 0 high byte 00000000 P3CPH0.7 P3CPH0.6 P3CPH0.5 P3CPH0.4 P3CPH0.3 P3CPH0.2 P3CPH0.1 P3CPH0.0
P3CPL1 E6H
Bank2 PCA3 capture/compare module 1 low byte 00000000 P3CPL1.7 P3CPL1.6 P3CPL1.5 P3CPL1.4 P3CPL1.3 P3CPL1.2 P3CPL1.1 P3CPL1.0
P3CPH1 E7H
Bank2 PCA3 capture/compare module 1 high byte 00000000 P3CPH1.7 P3CPH1.6 P3CPH1.5 P3CPH1.4 P3CPH1.3 P3CPH1.2 P3CPH1.1 P3CPH1.0
PCACON B0H
Bank2 PCA Enable Register ----0000 - - - - PR3 PR2 PR1 PR0
P0FORCE
DCH
Bank2 PCA0 Force Output Control Register --00--00 - - P0OSC1 P0OSC0 - - P0FCO1 P0FCO0
P1
FORCE
BDH
Bank2 PCA1 Force Output Control Register --00--00 - - P1OSC1 P1OSC0 - - P1FCO1 P1FCO0
P2FOR
CE
BEH
Bank2 PCA2 Force Output Control Register --00--00 - - P2OSC1 P2OSC0 - - P2FCO1 P2FCO0
P3
FORCE
BFH
Bank2 PCA3 Force Output Control Register --00--00 - - P3OSC1 P3OSC0 - - P3FCO1 P3FCO0
19

SH79F7416
20