Sino Wealth SH79F166A User manual

SH79F166A
Enhanced 8051 Microcontroller with 10bit ADC
1 V2.2
1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 16K Bytes
RAM: internal 256 Bytes, external 256 Bytes, LCD RAM
19Bytes
EEPROM-like: 1K Bytes
Operation Voltage:
fOSC = 32.768kHz - 12MHz, VDD = 2V - 5.5V
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 12MHz
- Ceramic oscillator: 2MHz - 12MHz
- Internal RC: 12MHz (±2%)/128K
41 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Four 16-bit timer/counters T2, T3,T4 and T5
One 12-bit PWM
Powerful interrupt sources:
- Timer2, 3, 4, 5
- INT0, 1, 2, 3
- INT40, INT41, INT42, INT43
- ADC，EUART，SCM
- PWM
EUART
8channels 10-bits Analog Digital Converter (ADC),
with comparator function built-in
Buzzer
LED driver:
- 8 X 8 dots (1/8 duty)
- 4 X 8 dots (1/4 duty)
LCD driver:
- 8 X 19 dots (1/8 duty 1/4 bias)
- 4 X 19 dots (1/4 duty 1/3 bias)
Low Voltage Reset (LVR) function (enabled by
code option)
- LVR voltage level 1: 4.3V
- LVR voltage level 2: 2.1V
CPU Machine cycle:
1 oscillator clock
Watch Dog Timer (WDT)
Warm-up Timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package: QFP44/LQFP44
2. General Description
The SH79F166A is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch
structure, that helps the SH79F166A can perform more fast operation speed and higher calculation performance, if compare
SH79F166A with standard 8051 at same clock speed.
The SH79F166A retains most features of the standard 8051. These features include internal 256 bytes RAM, UART and
Int0-3.In addition, the SH79F166A provides external 256 bytes RAM, It also contains 16K bytes Flash memory block both for
program and data. Also the ADC and PWM timer functions are incorporated in SH79F166A.
For high reliability and low cost issues, the SH79F166A builds in Watchdog Timer, Low Voltage Reset function. And
SH79F166A also supports two power saving modes to reduce power consumption.

SH79F166A
2
3. Block Diagram
16K Bytes
Flash ROM
Internal 256 Bytes
External 256 Bytes
(Exclude System
Register)
Oscillator
Pipelined 8051 architecture
Timer2 (16bit)
Timer3 (16bit)
Timer4 (16bit)
Timer5(16bit)
Reset circuit RST
XTAL2
XTAL1
V
DD
External Interrupt
buzzer
Power
Watch Dog
oscillator fail
detector
12-bit PWM
Internal
Oscillator
Port 3
Configuration I/Os
Port 4
Configuration I/Os
P1.0 - P1.7
P2.0 - P2.7
P0.0 - P0.7
Port 2
Configuration I/Os
P3.0 - P3.7
EUART0
10-bit ADC
Jtag ports
(for debug)
Port 5
Configuration I/Os
LCD/LED Driver
COM1 - 8
SEG1 - 19
Port 1
Configuration I/Os
P4.0 - P4.4
Port 0
Configuration I/Os
P5.0 - P5.3
Oscillator X
XTALX2
XTALX1

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4. Pin Configuration
QFP44:
P4.1/INT41/AN1
PWM01/SEG19/P0.2
BUZ/T3/P5.3
P4.4/AVREF
P4.0/INT40/AN0
P3.6/COM7/LED_C7/AN6
P4.2/INT42/AN2
P4.3/INT43/AN3
P3.3/COM4/LED_C4
LED_S8/SEG8/P1.7
Vss
25 24 2332 31 30 29 28 27 26
1 2 3 4 5 6 7 8 9 10 11
33
12
13
14
15
16
17
18
19
22
21
20
44
43
42
41
40
39
38
37
34
35
36
SH79F166AF
VDD
P3.2/COM3/LED_C3
P3.7/COM8/LED_C8/AN7
NC
P3.4/COM5/LED_C5/AN4
P3.0/COM1/LED_C1 P3.1/COM2/LED_C2
P1.0/SEG1/LED_S1/TDO P1.4/SEG5/LED_S5
P1.3/SEG4/LED_S4/TCK
P1.2/SEG3/LED_S3/TDI
P1.1/SEG2/LED_S2/TMS
P1.5/SEG6/LED_S6 P1.6/SEG7/LED_S7
SEG11/P2.2
TXD/SEG10/P2.1
RXD/SEG9/P2.0
SEG12/P2.3
SEG15/P2.6
FLT/SEG14/P2.5
SEG13/P2.4
SEG16/P2.7
SEG17/P0.0
SEG18/P0.1
PWM0/T4/P0.3
T2EX/INT0/P0.4
XTALX1/INT3/P0.7
XTAL2/P5.1
T2/INT1/P0.5
XTALX2/INT2/P0.6
RST/P5.2
XTAL1/P5.0
P3.5/COM6/LED_C6/AN5
QFP44 Pin Configuration Diagram

SH79F166A
4
LQFP44:
P4.1/INT41/AN1
PWM01/SEG19/P0.2
BUZ/T3/P5.3
P4.4/AVREF
P4.0/INT40/AN0
P3.6/COM7/LED_C7/AN6
P4.2/INT42/AN2
P4.3/INT43/AN3
P3.3/COM4/LED_C4
LED_S8/SEG8/P1.7
Vss
25 24 2332 31 30 29 28 27 26
1 2 3 4 5 6 7 8 9 10 11
33
12
13
14
15
16
17
18
19
22
21
20
44
43
42
41
40
39
38
37
34
35
36
SH79F166AP
VDD
P3.2/COM3/LED_C3
P3.7/COM8/LED_C8/AN7
NC
P3.4/COM5/LED_C5/AN4
P3.0/COM1/LED_C1 P3.1/COM2/LED_C2
P1.0/SEG1/LED_S1/TDO P1.4/SEG5/LED_S5
P1.3/SEG4/LED_S4/TCK
P1.2/SEG3/LED_S3/TDI
P1.1/SEG2/LED_S2/TMS
P1.5/SEG6/LED_S6 P1.6/SEG7/LED_S7
SEG11/P2.2
TXD/SEG10/P2.1
RXD/SEG9/P2.0
SEG12/P2.3
SEG15/P2.6
FLT/SEG14/P2.5
SEG13/P2.4
SEG16/P2.7
SEG17/P0.0
SEG18/P0.1
PWM0/T4/P0.3
T2EX/INT0/P0.4
XTALX1/INT3/P0.7
XTAL2/P5.1
T2/INT1/P0.5
XTALX2/INT2/P0.6
RST/P5.2
XTAL1/P5.0
P3.5/COM6/LED_C6/AN5
LQFP44 Pin Configuration Diagram
Note:
The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin
Configuration Diagram. This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the
lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by
software, can the corresponding pin be released for the lower priority function use.

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Table 4.1 Pin Function
Pin No. Pin Name Default function Pin No. Pin Name Default function
1 PWM01/SEG19/P0.2 P0.2 23 LED_C4/COM4/P3.3 P3.3
2 PWM0/T4/P0.3 P0.3 24 LED_C3/COM3/P3.2 P3.2
*3 T2EX/INT0/P0.4 P0.4 25 LED_C2/COM2/P3.1 P3.1
*4 T2/INT1/P0.5 P0.5 26 LED_C1/COM1/P3.0 P3.0
5 XTALX2/INT2/P0.6 P0.6 27 LED_S1/SEG1/P1.0 P1.0
6 XTALX1/INT3/P0.7 P0.7 28 LED_S2/SEG2/P1.1 P1.1
7 VSS ---- 29 LED_S3/SEG3/P1.2 P1.2
8 XTAL1/P5.0 ---- 30 LED_S4/SEG4/P1.3 P1.3
9 XTAL2/P5.1 ---- 31 LED_S5/SEG5/P1.4 P1.4
10 RST
————/P5.2 RST ———— 32 LED_S6/SEG6/P1.5 P1.5
11 BUZ/T3/P5.3 P5.3 33 LED_S7/SEG7/P1.6 P1.6
12 VDD ---- 34 LED_S8/SEG8/P1.7 P1.7
13 NC ---- 35 RXD/SEG9/P2.0 P2.0
14 AVREF/P4.4 P4.4 36 TXD/SEG10/P2.1 P2.1
15 AN3/INT43/P4.3 P4.3 37 SEG11/P2.2 P2.2
16 AN2/INT42/P4.2 P4.2 38 SEG12/P2.3 P2.3
17 AN1/INT41/P4.1 P4.1 39 SEG13/P2.4 P2.4
18 AN0/INT40/P4.0 P4.0 40 FLT/SEG14/P2.5 P2.5
19 AN7/LED_C8/COM8/P3.7 P3.7 41 SEG15/P2.6 P2.6
20 AN6/LED_C7/COM7/P3.6 P3.6 42 SEG16/P2.7 P2.7
21 AN5/LED_C6/COM6/P3.5 P3.5 43 SEG17/P0.0 P0.0
22 AN4/LED_C5/COM5/P3.4 P3.4 44 SEG18/P0.1 P0.1
* Note: P0.4, P0.5 are configured as N-channel open drain I/O

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5. Pin Description
Pin No. Type Description
I/O PORT
P0.0 - P0.7 I/O 8 bit General purpose CMOS I/O
P1.0 - P1.7 I/O 8 bit General purpose CMOS I/O
P2.0 - P2.7 I/O 8 bit General purpose CMOS I/O
P3.0 - P3.7 I/O 8 bit General purpose CMOS I/O
P4.0 - P4.4 I/O 5 bit General purpose CMOS I/O
P5.0 - P5.3 I/O 4 bit General purpose CMOS I/O
Timer T2 I/O Timer2 external input
T3 I Timer3 external input
T4 I/O Timer4 external input/Comparator output
T2EX I Timer2 Reload/Capture/Direction Control
PWM
PWM0 O Output pin for 12-bit PWM timer
PWM01 O Output pin for 12-bit PWM timer with fixed phase relationship of PWM0
FLT I PWM Fault Detect input
EUART RXD I EUART data input
TXD O EUART data output
ADC AN0 - AN7 I ADC input channel
AVREF I External ADC reference voltage input
LCDCOM1 - COM8 O Common signal output for LCD display
SEG1 - SEG19 O Segment signal output for LCD display
LED
LED_C1 - LED_C8 O Common signal output for LED display
LED_S1 - LED_S8 O Segment signal output for LED display
Interrupt & Reset & Clock & Power
INT0 - INT3 I External interrupt 0-3 input source
INT40 - INT43 I External interrupt 40-43 input source
RST
———— I The device will be reset by A low voltage on this pin longer than 10us, an internal
resistor about 30kΩto VDD, So using only an external capacitor to GND can cause
a power-on reset.
XTAL1 I Oscillator input
XTAL2 O Oscillator output
XTALX1 I OscillatorX input
XTALX2 O OscillatorX output
VSS P Ground
VDD P Power supply (2.0 - 5.5V)
(to be continued)

SH79F166A
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(continue)
Pin No. Type Description
Buzzer
BUZ O Buzzer output pin
Programmer
TDO (P1.0) O Debug interface: Test data out
TMS (P1.1) I Debug interface: Test mode select
TDI (P1.2) I Debug interface: Test data in
TCK (P1.3) I Debug interface: Test clock in
Note
：
When P1.0-1.3 used as debug interface, functions of P1.0-1.3 are blocked.

SH79F166A
8
6. SFR Mapping
The SH79F166A provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function Register
(SFR). The SFR of the SH79F166A fall into the following categories:
CPU Core Registers: ACC, B, PSW, SP, DPL, DPH
Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE
Power and Clock Control Registers: PCON, SUSLO
Flash Registers: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4, IB_CON5,
FLASHCON
Data Memory Register: XPAGE
Hardware Watchdog Timer Registers: RSTSTAT
System Clock Control Register: CLKCON
Interrupt System Registers: IEN0, IEN1, IENC, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1
I/O Port Registers: P0, P1, P2, P3, P4, P5, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P0PCR, P1PCR,
P2PCR, P3PCR, P4PCR, P5PCR, P0OS
Timer Registers: TCON, T2CON, T2MOD, TH2, TL2, RCAP2L, RCAP2H, T3CON, TH3, TL3,
T4CON, TH4, TL4, SWTHL, T5CON, TH5, TL5
EUART Registers: SCON, SBUF, SADEN, SADDR, PCON, RxCON
ADC Registers: ADCON, ADT, ADCH, ADDL, ADDH
LCD Registers: DISPCON, DISPCLK0, DISPCLK1, P0SS, P1SS, P2SS, P3SS
LED Registers: DISPCON, DISPCLK0, DISPCLK1, P1SS, P3SS
Buzzer Registers: BUZCON
PWM Registers: PWMEN, PWMEN1, PWMLO, PWM0C, PWM0PL, PWM0PH, PWM0DL, PWM0DH
LPD Registers: LPDCON

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Table 6.1 CPU Core SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ACC E0H Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
B F0H B Register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
AUXC F1H C Register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0
PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P
SP 81H Stack Pointer 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
DPL 82H Data Pointer Low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0
DPH 83H Data Pointer High byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0
DPL1 84H Data Pointer 1 Low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPH1 85H Data Pointer 1 High byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
INSCON 86H Data pointer select -0--00-0 - BKS0 - - DIV MUL - DPS
Table 6.2 Power and Clock control SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON 87H Power Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
SUSLO 8EH Suspend Mode Control 00000000 SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0

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Table 6.3 Flash control SFRs
Mnem Add Name POR/WDT/LVR
/PIN R
eset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_OFF
SET FBH Bank0 Low byte offset of flash memory for programming 00000000 IB_OFF SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0
IB_DATA FCH
Bank0 Data Register for programming flash memory 00000000 IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
IB_CON1 F2H
Bank0 Flash Memory Control Register 1 00000000 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0
IB_CON2 F3H
Bank0 Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0
IB_CON3 F4H
Bank0 Flash Memory Control Register 3 ----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0
IB_CON4 F5H
Bank0 Flash Memory Control Register 4 ----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0
IB_CON5 F6H
Bank0 Flash Memory Control Register 5 ----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
XPAGE F7H
Bank0 Memory Page --000000 - - XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
FLASHCON
A7H
Bank0 Flash access control -------0 - - - - - - - FAC
Table 6.4 WDT SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTSTAT B1H
Bank0 Watchdog Timer Control *-***000 WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
*Note: RSTSTAT initial value is determined by different RESET.
Table 6.5 CLKCON SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKCON B2H
Bank0 System Clock Control Register 111000-- 32k_ SPDUP CLKS1 CLKS0 SCMIF HFON FS - -

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Table 6.6 Interrupt SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN0 A8H
Bank0 Interrupt Enable Control 0 0000-000 EA EADC ET2 ES - EX1 ET5 EX0
IEN1 A9H
Bank0 Interrupt Enable Control 1 0000000- ESCM/ELPD
ET4 EPWM ET3 EX4 EX3 EX2 -
IENC BAH
Bank0 Interrupt 4channel enable control ----0000 - - - - EXS43 EXS42 EXS41 EXS40
IENC1 BBH
Bank0 Interrupt channel enable control 1 ------00 - - - - - - ESCM1 ELPD
IPH0 B4H
Bank0 Interrupt Priority Control High 0 -000-000 - PADCH PT2H PSH - PX1H PT5H PX0H
IPL0 B8H
Bank0 Interrupt Priority Control Low 0 -000-000 - PADCL PT2L PSL - PX1L PT5L PX0L
IPH1 B5H
Bank0 Interrupt Priority Control High 1 0000000- PSCMH PT4H PPWMH PT3H PX4H PX3H PX2H -
IPL1 B9H
Bank0 Interrupt Priority Control Low 1 0000000- PSCML PT4L PPWML PT3L PX4L PX3L PX2L -
EXF0 E8H
Bank0 External interrupt Control 0 00000000 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 IE3 IE2
EXF1 D8H
Bank0 External interrupt Control 1 ----0000 - - - - IF43 IF42 IF41 IF40

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Table 6.7 Port SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0 80H
Bank0 8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1
90H
Bank0 8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2
A0H
Bank0 8-bit Port 2 00000000 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P3 B0H
Bank0 8-bit Port 3 00000000 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P4 C0H
Bank0
5-bit Port 4 ---00000 - - - P4.4 P4.3 P4.2 P4.1 P4.0
P5 80H
Bank1
4-bit Port 5 ----0000 - - - - P5.3 P5.2 P5.1 P5.0
P0CR E1H
Bank0 Port0 input/output direction control 00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR E2H
Bank0 Port1 input/output direction control 00000000 P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
P2CR
E3H
Bank0 Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR
E4H
Bank0 Port3 input/output direction control 00000000 P3CR.7 P3CR.6 P3CR.5 P3CR.4 P3CR.3 P3CR.2 P3CR.1 P3CR.0
P4CR E5H
Bank0
Port4 input/output direction control ---00000 - - - P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0
P5CR E1H
Bank1
Port5 input/output direction control ----0000 - - - - P5CR.3 P5CR.2 P5CR.1 P5CR.0
P0PCR E9H
Bank0
Internal pull-high enable for Port0 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR EAH
Bank0 Internal pull-high enable for Port1 00000000 P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR EBH
Bank0 Internal pull-high enable for Port2 00000000 P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR
ECH
Bank0 Internal pull-high enable for Port3 00000000 P3PCR.7 P3PCR.6 P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 P3PCR.1 P3PCR.0
P4PCR
EDH
Bank0 Internal pull-high enable for Port4 ---00000 - - - P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0
P5PCR E9H
Bank1
Internal pull-high enable for Port5 ----0000 - - - - P5PCR.3 P5PCR.2 P5PCR.1 P5PCR.0
P0OS EFH
Bank0
Output mode control --00---- - - P0OS.5 P0OS.4 - - - -

SH79F166A
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Table 6.8 Timer SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON 88H
Bank0 Timer/Counter Control ----0000 - - - - IE1 IT1 IE0 IT0
T2CON C8H
Bank0 Timer/Counter 2 Control 00000000 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T
----2 ---- CP/R ----L ----2 ----
T2MOD C9H
Bank0 Timer/Counter 2 Mode ------00 - - - - - - T2OE DCEN
RCAP2L CAH
Bank0 Timer/Counter 2 Reload /Caprure Low Byte 00000000 RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
RCAP2H CBH
Bank0 Timer/Counter 2 Reload /Caprure High Byte 00000000 RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
TL2 CCH
Bank0 Timer/Counter 2 Low Byte 00000000 TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
TH2 CDH
Bank0 Timer/Counter 2 High Byte 00000000 TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
T3CON 88H
Bank1 Timer/Counter 3 Control 0-00-000 TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0
SWTHL 89H
Bank1 Timer/Counter data switch ------00 - - - - - - T5HLCON T3HLCON
TL3 8CH
Bank1 Timer/Counter 3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0
TH3 8DH
Bank1 Timer/Counter 3 High Byte 00000000 TH3.7 TH3.6 TH3.5 TH3.4 TH3.3 TH3.2 TH3.1 TH3.0
T4CON C8H
Bank1 Timer/Counter 4 Control 00000000 TF4 TC4 T4PS1 T4PS0 T4M1 T4M0 TR4 T4CLKS
TL4 CCH
Bank1 Timer/Counter 4 Low Byte 00000000 TL4.7 TL4.6 TL4.5 TL4.4 TL4.3 TL4.2 TL4.1 TL4.0
TH4 CDH
Bank1 Timer/Counter 4 High Byte 00000000 TH4.7 TH4.6 TH4.5 TH4.4 TH4.3 TH4.2 TH4.1 TH4.0
T5CON C0H
Bank1 Timer/Counter 5 Control 0-000-0- TF5 - T5PS1 T5PS0 - - TR5 -
TL5 CEH
Bank1 Timer/Counter 5 Low Byte 00000000 TL5.7 TL5.6 TL5.5 TL5.4 TL5.3 TL5.2 TL5.1 TL5.0
TH5 CFH
Bank1 Timer/Counter 5 High Byte 00000000 TH5.7 TH5.6 TH5.5 TH5.4 TH5.3 TH5.2 TH5.1 TH5.0

SH79F166A
14
Table 6.9 EUART SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCON 98H
Bank0 Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL
REN TB8 RB8 TI RI
SBUF 99H
Bank0 Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
SADEN 9BH
Bank0 Slave Address Mask 00000000 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
SADDR 9AH
Bank0 Slave Address 00000000 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
PCON 87H
Bank0 Power & serial Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
RxCON 9FH
Bank0 Rxd pin Schmidt voltage Control ------00 - - - - - - RxCON1 RxCON0
Table 6.10 ADC SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADCON 93H
Bank0 ADC Control 00000000 ADON ADCIF EC REFC SCH2 SCH1 SCH0 GO/D
----O ----N ----E ----
ADT 94H
Bank0 ADC Time Configuration 000-0000 TADC2 TADC1 TADC0 - TS3 TS2 TS1 TS0
ADCH 95H
Bank0 ADC Channel Configuration 00000000 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADDL 96H
Bank0 ADC Data Low Byte ------00 - - - - - - A1 A0
ADDH 97H
Bank0 ADC Data High Byte 00000000 A9 A8 A7 A6 A5 A4 A3 A2
Table 6.11 Buzzer SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
BUZCON BDH
Bank0 Buzzer output control ----0000 - - - - BCA2 BCA1 BCA0 BZEN

SH79F166A
15
Table 6.12 LCD SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DISPCON ABH
Bank0 LCD Control 00000000 DISPSEL LCDON ELCC DUTY VOL3 VOL2 VOL1 VOL0
DISPCON1
ADH
Bank0 LCD Control 1 ---00000 - - - RLCD FCCTL1 FCCTL0 MOD1 MOD0
DISPCLK0
ACH
Bank0 LCD clock 0 00000000 DCK0.7 DCK0.6 DCK0.5 DCK0.4 DCK0.3 DCK0.2 DCK0.1 DCK0.0
DISPCLK1
AAH
Bank0 LCD clock 1 -------0 - - - - - - - DCK1.0
P0SS B6H
Bank0 P0 mode Select -----000 - - - - - P0S2 P0S1 P0S0
P1SS 9CH
Bank0 P1 mode Select 00000000 P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0
P2SS 9DH
Bank0 P2 mode Select 00000000 P2S7 P2S6 P2S5 P2S4 P2S3 P2S2 P2S1 P2S0
P3SS 9EH
Bank0 P3 mode Select 00000000 P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0
Table 6.13 LED SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DISPCON ABH
Bank0 LED Control 00-0---- DISPSEL LEDON - DUTY - - - -
DISPCLK0
ACH
Bank0 LED clock 0 00000000 DCK0.7 DCK0.6 DCK0.5 DCK0.4 DCK0.3 DCK0.2 DCK0.1 DCK0.0
DISPCLK1
AAH
Bank0 LED clock 1 -------0 - - - - - - - DCK1.0
P1SS 9CH
Bank0 P1 mode Select 00000000 P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0
P3SS 9EH
Bank0 P3 mode Select 00000000 P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0

SH79F166A
16
Table 6.14 PWM SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMEN CFH
Bank0 PWM timer enable -0--0--0 - EFLT - - EPWM01 - - EPWM0
PWMEN1 B7H
Bank0 PWM output enable -------0 - - - - - - - PWM0
PWMLO E7H
Bank0 PWM register Lock 00000000 PWMLO.7 PWMLO.6 PWMLO.5 PWMLO.4 PWMLO.3 PWMLO.2 PWMLO.1 PWMLO.0
PWM0C D2H
Bank0 12-bit PWM Control 00-00000 PWM0IE PWM0IF - FLTS FLTC PWM0S TnCK01 TnCK00
PWM0PL D3H
Bank0 12-bit PWM Period Control low byte
00000000 PP0.7 PP0.6 PP0.5 PP.4 PP0.3 PP0.2 PP0.1 PP0.0
PWM0PH D4H
Bank0 12-bit PWM Period Control high byte ----0000 - - - - PP0.11 PP0.10 PP0.9 PP0.8
PWM0DL D5H
Bank0 12-bit PWM Duty Control low byte 00000000 PD0.7 PD0.6 PD0.5 PD0.4 PD0.3 PD0.2 PD0.1 PD0.0
PWM0DH D6H
Bank0 12-bit PWM Duty Control high byte
----0000 - - - - PD0.11 PD0.10 PD0.9 PD0.8
PWM0DT D1H
Bank0 PWM01 Dead time control 00000000 DT0.7 DT0.6 DT0.5 DT0.4 DT0.3 DT0.2 DT0.1 DT0.0
Table 6.15 LPD SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LPDCON B3H
Bank0 LPD control 00000000 LPDEN LPDF LPDMD LPDIF LPDS3 LPDS2 LPDS1 LPDS0
Note: - :Unimplemented

SH79F166A
17
SFR Map
Bank0
Bit
addressable
Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8H IB_OFFSET IB_DATA FFH
F0H B AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE F7H
E8H EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR P0OS EFH
E0H ACC P0CR P1CR P2CR P3CR P4CR PWMLO E7H
D8H EXF1 DFH
D0H PSW PWM0DT PWM0C PWM0PL PWM0PH PWM0DL PWM0DH D7H
C8H T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PWMEN CFH
C0H P4 C7H
B8H IPL0 IPL1 IENC IENC1 BUZCON BFH
B0H P3 RSTSTAT CLKCON LPDCON IPH0 IPH1 P0SS PWMEN1 B7H
A8H IEN0 IEN1 DISPCLK1 DISPCON DISPCLK0 DISPCON1 AFH
A0H P2 FLASHCON A7H
98H SCON SBUF SADDR SADEN P1SS P2SS P3SS RxCON 9FH
90H P1 ADCON ADT ADCH ADDL ADDH 97H
88H TCON SUSLO 8FH
80H P0 SP DPL DPH DPL1 DPH1 INSCON PCON 87H
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Bank1
Bit
addressable
Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8H FFH
F0H B AUXC XPAGE F7H
E8H P5PCR EFH
E0H ACC P5CR E7H
D8H DFH
D0H PSW D7H
C8H T4CON TL4 TH4 TL5 TH5 CFH
C0H T5CON C7H
B8H IPL0 IPL1 BFH
B0H IPH0 IPH1 B7H
A8H IEN0 IEN1 AFH
A0H A7H
98H 9FH
90H 97H
88H T3CON SWTHL TL3 TH3 SUSLO 8FH
80H P5 SP DPL DPH DPL1 DPH1 INSCON PCON 87H
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Note: The unused addresses of SFR are not available.

SH79F166A
18
7. Normal Function
7.1 CPU
7.1.1 CPU Core SFR
Feature
CPU core registers: ACC, B, PSW, SP, DPL, DPH
Accumulator
ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator
simply as A.
B Register
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad
register.
Stack Pointer (SP)
The Stack Pointer Register is 8 bits wide, It is incremented before data is stored during PUSH, CALL executions and it is
decremented after data is out of stack during POP, RET, RETI executions. The stack may reside anywhere in on-chip internal
RAM (00H-FFH). On reset, the Stack Pointer is initialized to 07H causing the stack to begin at location 08H.
Program Status Word Register (PSW)
The PSW register contains program status information.
Table 7.1 PSW Register
D0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PSW CY AC F0 RS1 RS0 OV F1 P
R/W R/W R/W R/W R/W R/W R/W R/W R
Reset Value
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0
Bit Number
Bit Mnemonic
Description
7 CY Carry flag bit
0: no carry or borrow in an arithmetic or logic operation
1: a carry or borrow in an arithmetic or logic operation
6 AC Auxiliary Carry flag bit
0: an auxiliary carry or borrow in an arithmetic or logic operation
1: an auxiliary carry or borrow in an arithmetic or logic operation
5 F0 F0 flag bit
Available to the user for general purposes
4-3 RS[1:0]
R0-R7 Register bank select bits
00: Bank0 (Address to 00H-07H)
01: Bank1 (Address to 08H-0FH)
10: Bank2 (Address to 10H-17H)
11: Bank3 (Address to 18H-1FH)
2 OV Overflow flag bit
0: no overflow happen
1: an overflow happen
1 F1 F1 flag bit
Available to the user for general purposes
0 P Parity flag bit
0: an even number of “one” bits in the Accumulator
1: an odd number of “one” bits in the Accumulator
Data Pointer Register (DPTR)
DPTR consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address, but it may be
manipulated as a 16-bit register or as two independent 8-bit registers.

SH79F166A
19
7.1.2 Enhanced CPU core SFRs
Extended 'MUL' and 'DIV' instructions: 16bit*8bit, 16bit/8bit
Dual Data Pointer
Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON
The SH79F166A has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the
register is applied to hold the upper part of the operand/result.
The AUXC register is used during 16 bit operand multiply and divide operations. For other instructions it can be treated as
another scratch pad register.
After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard
8051 instructions. To enable the 16 bit mode operation, the corresponding enable bit in the INSCON register must be set.
Operation Result
A B AUXC
MUL INSCON.2 = 0; 8 bit mode (A)*(B) Low Byte High Byte ---
INSCON.2 = 1; 16 bit mode (AUXC A)*(B) Low Byte Middle Byte High Byte
DIV INSCON.3 = 0; 8 bit mode (A)/(B) Quotient Low Byte Remainder ---
INSCON.3 = 1; 16 bit mode (AUXC A)/(B) Quotient Low Byte Remainder Quotient High Byte
Dual Data Pointer
Using two data pointers can accelerate data memory moves. The standard data pointer is called DPTR and the new data
pointer is called DPTR1.
DPTR1 is the same with DPTR, which consists of a high byte (DPH1) and a low byte (DPL1). Its intended function is to hold a
16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers.
The DPS bit in INSTCON register is used to choose the active pointer. The user can switch data pointers by toggling the DPS
bit. And all DPTR-related instructions will use the currently selected data pointer.
7.1.3 Register
Table 7.2 Data Pointer Select Register
86H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
INSCON - BKS0 - - DIV MUL - DPS
R/W - R/W - - R/W R/W - R/W
Reset Value
(POR/WDT/LVR/PIN)- 0 - - 0 0 - 0
Bit Number Bit Mnemonic Description
6 BKS0 SFR Bank Selection Bit
0: SFR Bank0 selected
1: SFR Bank1 selected
3 DIV 16 bit/8 bit Divide Selection Bit
0: 8 bit Divide
1: 16 bit Divide
2 MUL 16 bit/8 bit Multiply Selection Bit
0: 8 bit Multiply
1: 16 bit Multiply
0 DPS Data Pointer Selection Bit
0: Data pointer
1: Data pointer1

SH79F166A
20
7.2 RAM
7.2.1 Features
SH79F166A provides both internal RAM and external RAM for random data storage. The internal data memory is mapped into
four separated segments:
The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
The Special Function Registers (SFR, addresses 80H to FFH) are directly addressable only.
The 256 bytes of external RAM(addresses 00H to FFH) are indirectly accessed by MOVX instructions.
The Upper 128 bytes occupy the same address space as SFR, but they are physically separate from SFR space. When an
instruction accesses an internal location above address 7FH, the CPU can distinguish whether to access the upper 128 bytes
data RAM or to access SFR by different addressing mode of the instruction.
Note: the unused address is unavailable in SFR.
1F2H
7FH
80H
0FFH 0FFH
80H
00H 00H
Upper
128 bytes
Internal
Ram
indirect accesses
Lower
128 bytes
Internal
Ram
direct or indirect
accesses
RESERVED
Extenal
RAM
SFR
Bank0
direct accesses
1E0H
0FFH
LCD RAM
SFR
Bank1
direct accesses
80H
0FFH
The Internal and External RAM Configuration
The SH79F166A provides traditional method for accessing of external RAM. Use MOVXA, @Ri or MOVX @Ri, A; to access
external low 256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 256 bytes RAM.
In SH79F166A the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A
instructions. The user can use XPAGE to represent the high byte address of RAM above 256 Bytes.
But SH79F166A only has 256 bytes external RAM, XPAGE must be set as 0.
In Flash SSP mode, the XPAGE can also be used as sector selector (Refer to SSP Function).
7.2.2 Register
Table 7.3 Data Memory Page Register
F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XPAGE - - XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
R/W - - R/W R/W R/W R/W R/W R/W
Reset Value
(POR/WDT/LVR/PIN)- - 0 0 0 0 0 0
Bit Number Bit Mnemonic Description
5-0 XPAGE[5:0] RAM Page Selector