Sino Wealth SH79F6441 User manual

SH79F6441
Enhanced 8051 Microcontroller
1 V2.3
1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM:64K Bytes
RAM:Internal 256 Bytes, external 2816 Bytes
EEPROM-Like:bulid-in 4096 Bytes(code option)
Operation Voltage:
- fOSC = 32.768kHz - 24MHz, VDD = 2.7V - 5.5V
Oscillator (code option):
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 16MHz
- Ceramic oscillator: 2MHz - 16MHz
- Internal RC oscillator: 24MHz (±1%)/128K (±10%)
42/30/26 CMOS bi-directional I/O pins (44 pins/32
pins/28 pins)
Built-in pull-up resistor for input pin (30kΩ)
12 large current driver I/O (code option optional
enhanced or standardized or weakened)
P0 port can reduce the pull current capacity (code option
optional weakened or standardized)
One16-bit timer/counters T3
Three 16-bit PCA0, PCA1 and PCA2 each contain two
comparison/capture units
3 channels 12-bits PWM timer
Interrupt sources:
- Timer3, PCA0-2
- INT0-3
- INT4: 8 input
- ADC, EUART, SPI
- PWM, SCM, CRC, TWI, LPD
SPI (Master/Slave Mode)
TWI (Master/Slave Mode)
Internal Logic Configuration Module(LCM)
3 enhanced UART (3V/5V communication) (own
baudrate generator)
15 analog inputs 12-bit Analog Digital Converter
Built-in low voltage Reset (LVR) function (code option)
- LVR voltage1: 4.1V
- LVR voltage2: 3.7V
- LVR voltage3: 2.8V
Built-in CRC verification module, the verify size can be
selected
Low Power Detect (LPD) Module with 13 level optional
Support single line simulation and download
CPU Machine period: 1 oscillator clock
Built-in Watch Dog Timer (WDT)
Built-in oscillator Warm-up timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package:
- LQFP44
- LQFP32
- QFN32
- SOP28
2. General Description
The SH79F6441 is high performance 8051 compatible micro-controller. The SH79F6441 can perform more fast operation
speed and higher calculation performance, if compare SH79F6441 with standard 8051 at same clock speed.
The SH79F6441 retains most features of the standard 8051. These features include internal 256 bytes RAM, Three UART and
INT0, INT1, INT2, INT3, INT4. In addition, SH79F6441 provides external 2816 bytes RAM. It also contains 64K bytes Flash
memory block for program storage.
The SH79F6441 not only include many standard communication modules, such as EUART, TWI, SPI and so on, but also
include 12bit ADC, PWM timer, ect.
In addition, the SH79F6441 also have CRC module, Logic configurable module (LCM) built in it.
For high reliability and low cost issues, the SH79F6441 builds in Watchdog Timer, Low Voltage Reset function and system clock
monitor. And SH79F6441 also supports two power saving modes to reduce power consumption.

SH79F6441
2
3. Block Diagram
64K Bytes
Flash ROM
Internal 256 Bytes
External 2816Bytes
(Exclude System
Register)
Oscillator
Pipelined 8051 architecture
Timer3 (16bit)
Reset circuit RST
XTAL2
XTAL1
V
DD
External Interrupt
LPD
Power
Watch Dog
oscillator fail
detector
12-bit PWM0/1/2
Internal
Oscillator
Port 3
Configuration I/Os
Port 4
Configuration I/Os
P1.0 - P1.7
P2.0 - P2.7
P0.0 - P0.7
Port 2
Configuration I/Os
P3.0 - P3.7
EUART0/1/2
TWI
Jtag ports
(for debug)
Port 5
Configuration I/Os
Port 1
Configuration I/Os
P4.0 - P4.7
Port 0
Configuration I/Os
P5.0 - P5.1
SPI
SCM
CRC
PCA0
PCA1
PCA2
12-bit ADC

SH79F6441
3
4. Pin Configration
4.1 LQFP44 Package
1 2 3 4 5 6 7 8 9 10 11
12
13
14
15
16
17
18
19
22
21
20
25 24 2332 31 30 29 28 27 2633
44
43
42
41
40
39
38
37
34
35
36
P4.7
T3/AVREF/AN8/P1.6
AN11/P3.6
AN12/P3.7 AN13/P5.0
P5.1
RST/P1.7
XTAL2/P3.3
XTAL1/P3.4
VDD
VSS
P4.0
P4.1
P4.2
P4.3
P3.2/P1CEX0
P3.1/INT0/ECI1
P3.0/AN9/SS
P3.5/AN10
P2.0/SCK/P1CEX1
P2.1/MISO/TXD2
P2.2/MOSI/RXD2
P2.3/VIN
P2.4
P2.5/PWM2
P2.6/INT45
P2.7/INT46/P2CEX1
P4.4
P4.5
P4.6
P0.7/INT1/P2CEX0
P0.6/ECI2
P0.5/AN3
TCK/AN7/INT40/P1.5
TDI/AN6/INT41/P1.4
TMS/AN5/INT42/P1.3
SWE/TDO/AN4/INT43/P1.2
INT44/P1.1
INT47/P1.0
P0.0
INT3/P0.1
AN0/P0.2
AN1/P0.3
AN2/P0.4
SH79F6441
Note:
In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the
lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin
of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of
the pin can the corresponding pin be released as a low-priority port.

SH79F6441
4
4.2 LQFP32 Package
P3.1/INT0/ECI1
TCK/AN7/INT40/P1.5
SH79F6441
P2.5/PWM2
P0.6/ECI2
P0.7/INT1/P2CEX0
P2.7/INT46/P2CEX1
P2.6/INT45
P0.5/AN3
P0.4/AN2 P0.3/AN1
AN0/P0.2
INT3/P0.1
P0.0
INT47/P1.0
INT44/P1.1
SWE/TDO/AN4/INT43/P1.2
TMS/AN5/INT42/P1.3
TDI/AN6/INT41/P1.4
1 2 3 4 5 6 7 8
9
10
12
13
14
15
16
11
25
32
31
30
29
28
27
26
24 23 1718
1922 21 20
T3/AVREF/AN8/P1.6
RST/P1.7
XTAL2/P3.3
XTAL1/P3.4
VDD
VSS
P1CEX0/P3.2
P3.0/AN9/SS
P3.5/AN10
P2.0/SCK/P1CEX1
P2.1/MISO/TXD2
P2.2/MOSI/RXD2
P2.3/VIN
P2.4
Note:
In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the
lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin
of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of
the pin can the corresponding pin be released as a low-priority port.

SH79F6441
5
4.3 QFN32 Package
P3.1/INT0/ECI1
TCK/AN7/INT40/P1.5
SH79F6441
P2.5/PWM2
P0.6/ECI2
P0.7/INT1/P2CEX0
P2.7/INT46/P2CEX1
P2.6/INT45
P0.5/AN3
P0.4/AN2 P0.3/AN1
AN0/P0.2
INT3/P0.1
P0.0
INT47/P1.0
INT44/P1.1
SWE/TDO/AN4/INT43/P1.2
TMS/AN5/INT42/P1.3
TDI/AN6/INT41/P1.4
1 2 3 4 5 6 7 8
9
10
12
13
14
15
16
11
25
32
31
30
29
28
27
26
24 23 1718
1922 21 20
T3/AVREF/AN8/P1.6
RST/P1.7
XTAL2/P3.3
XTAL1/P3.4
VDD
VSS
P1CEX0/P3.2
P3.0/AN9/SS
P3.5/AN10
P2.0/SCK/P1CEX1
P2.1/MISO/TXD2
P2.2/MOSI/RXD2
P2.3/VIN
P2.4
Note:
In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the
lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin
of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of
the pin can the corresponding pin be released as a low-priority port.

SH79F6441
6
4.4 SOP28 Package
ECI1/INT0/P3.1
TCK/AN7/INT40/P1.5
SH79F6441
P2.5/PWM2
P0.6/ECI2
P0.7/INT1/P2CEX0
P2.7/INT46/P2CEX1
P2.6/INT45
P0.5/AN3
P0.4/AN2
P0.3/AN1
SWE/TDO/AN4/INT43/P1.2
TMS/AN5/INT42/P1.3
TDI/AN6/INT41/P1.4
T3/AVREF/AN8/P1.6
RST/P1.7
XTAL2/P3.3
XTAL1/P3.4
VDD
VSS
P1CEX0/P3.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SS/AN9/P3.0
AN10/P3.5 P2.0/SCK/P1CEX1
P2.1/MISO/TXD2
P2.2/MOSI/RXD2
P2.3/VIN
P2.4
P0.2/AN0
Note:
In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the
lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin
of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of
the pin can the corresponding pin be released as a low-priority port.

SH79F6441
7
LCM (Logical Function Configuration Module) Pin Allocation Table
Function
UART0
UART1
TWI
PWM0
PWM1
INT2
PCA0
Pin
RXD0 TXD0 RXD1 TXD1 SCL SDA PWM0 PWM1 INT2 P0CEX0 P0CEX1 ECI0
P0.0
●●■
P0.1 ●●
P0.2
●●●●
P0.3 ●●●
P0.4
●■●
P0.5 ■●●●
P0.6
■●●
P0.7 ●■
P1.0
■●
P1.1 ●■
P1.2
P1.3
P1.4
P1.5
P1.6 ●●
P1.7 ●●
P2.0 ●●
P2.1 ●●●
P2.2 ●●●
P2.3 ■●
P2.4 ●●■
P2.5
●●
P2.6 ●●■●
P2.7
●●
P3.0 ●●■
P3.1
●●
P3.2 ●●
P3.3
●●●●●
P3.4 ●●●●
P3.5
●■●
P3.6 ●
P3.7
●
P4.0 ●
P4.1
●
P4.2 ●●●
P4.3
●●●
P4.4 ●
P4.5 ●●●
P4.6 ●●●
P4.7 ●
P5.0 ●●●
P5.1 ●●●
Note:
In Table, the black dots (
● ) respected the functions which can be configurated for the pin; The black square (  ) respected the
default function pin of logic configuration module after reset. The black square (
 ) can be configurated to corresponding black
dots (
● ) pin through LCM.
The priority of LCM is lower than all the other function of the pin (except IO function).

SH79F6441
8
5. Pin Description
Pin No. Type Description
I/O PORT
P0.0-P0.7 I/O 8-bit bi-directional I/O port
P1.0-P1.7 I/O 8-bit bi-directional I/O port
P2.0-P2.7 I/O 8-bit bi-directional I/O port
P3.0-P3.7 I/O 8-bit bi-directional I/O port
P4.0-P4.7 I/O 8-bit bi-directional I/O port
P5.0-P5.1 I/O 2-bit bi-directional I/O port
Timer
T3 I Time3 external input
PWM Controller
PWM0 O 12-bit output pin for PWM0
PWM1 O 12-bit output pin for PWM1
PWM2 O 12-bit output pin for PWM2
EUART
RXD0/1/2 I EUART0/1/2 data input
TXD0/1/2 O EUART0/1/2 data output
TWI
SDA I/O TWI data input/output pin
SCL I/O TWICLK pin
SPI
MOSI I/O SPI master output slave input pin
MISO I/O SPI master input slave out pin
SCK I/O SPI serial clock pin
SS
——— I SPI slave device select pin
ADC
AN0 - AN13 I ADC input pin
AVREF I ADC external analog reference voltage pin
Interrupt & Reset & Clock & Power
INT0 - INT3 I External interrupt 0-3 input source
INT40 - INT47 I External interrupt 40-47 input source
RST
———— I The device will be reset by a low voltage on this pin longer than 10us, an internal
resistor about 100kΩ to VDD, So using only an external capacitor to GND can cause
a PIN reset.
XTAL1 I Resonator input
XTAL2 O Resonator output
VSS P Ground
VDD P Power source (2.7 - 5.5V)
(to be continued)

SH79F6441
9
(continue)
PCA Controller
P0CEX0 I/O Input/output pin for PCA0 module 0
P0CEX1 I/O Input/output pin for PCA0 module 1
ECI0 I The external clock input for PCA0
P1CEX0 I/O Input/output pin for PCA1 module 0
P1CEX1 I/O Input/output pin for PCA1 module 1
ECI1 I The external clock input for PCA1
P2CEX0 I/O Input/output pin for PCA2 module 0
P2CEX1 I/O Input/output pin for PCA2 module 1
ECI2 I The external clock input for PCA2
LPD
VIN I LPD detection voltage input port
Single line simulation interface
SWE (P1.2) I/O Single-line simulation interface. If the chip VDD power-on or power-down slope is
greater than 500ms/V, it is recommended to connect 47K - 1M resistors to GND or
VDD to increase the stability of the chip.
Programming interface
TDO (P1.2) O Debug interface: Test data out
TMS (P1.3) I Debug interface: Test mode select
TDI (P1.4) I Debug interface: Test data input
TCK (P1.5) I Debug interface: Test clock input
Note: When P1.2-1.5 is used as a debugging interface, the original function of P1.2-1.5 is forbidden.

SH79F6441
10
6. SFR Mapping
The SH79F6441 contains a 256-byte direct-addressed register, including general-purpose data memory and special function
registers (SFR). The SH79F6441 has the following SFR:
CPU Core Registers: ACC, B, PSW, SP, DPL, DPH
Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE
Power and Clock Control Registers: PCON,SUSLO
Flash Registers: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4, IB_CON5,
FLASHCON
Data Memory Register: XPAGE
Watchdog Timer Registers: RSTSTAT
System Clock Control Registers: CLKCON
Interrupt System Registers: IEN0, IEN1, IEN2, IENC, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1, EXCON, TCON
I/O RegistersPort: P0, P1, P2, P3, P4, P5, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P0PCR, P1PCR,
P2PCR, P3PCR, P4PCR, P5PCR, PIMS0, PIMS1, PIMS2
Timer Registers: T3CON, TH3, TL3
PCA Registers: PCACON, P0TOPL, P0TOPH, P0CMD, P0CF, P0CPM0, P0CPM1, P0CPL0, P0CPH0,
P0CPL1, P0CPH1, P0FORCE, P1TOPL, P1TOPH, P1CMD, P1CF, P1CPM0,
P1CPM1, P1CPL0, P1CPH0, P1CPL1, P1CPH1, P1FORCE, P2TOPL, P2TOPH,
P2CMD, P2CF, P2CPM0, P2CPM1, P2CPL0, P2CPH0, P2CPL1, P2CPH1, P2FORCE
EUART Registers: PCON, SCON, SBUF, SADEN, SADDR, SBRTL, SBRTH, SFINE, SCON1, SBUF1,
SADEN1, SADDR1, SBRTL1, SBRTH1, SFINE1, PCON2, SCON2, SBUF2, SADEN2,
SADDR2, SBRTL2, SBRTH2, SFINE2
SPI Register: SPCON, SPSTA, SPDAT
TWI Register: TWICON, TWIPCR, TWITOUT, TWISTA, TWTFREE, TWIBR, TWIADR, TWIDAT,
TWIAMR
ADC Register: ADCON1, ADCON2, ADT, ADCH1, ADCH2, ADDxL, ADDxH, SEQCON, SEQCHX
LCM Register: UART0CR, UART1CR, TWICR, PWMCR, CEXCR, ECICR
PWM Register: PWM0CON, PWM1CON, PWM2CON, PWM0PL, PWM0PH, PWM0DL, PWM0DH,
PWM1PL, PWM1PH, PWM1DL, PWM1DH, PWM2PL, PWM2PH, PWM2DL,
PWM2DH
LPD Register: LPDCON, LPDSEL
CRC Register: CRCCON, CRCDL, CRCDH, CRCSTAL, CRCSTAH, CRCSTOL, CRCSTOH

SH79F6441
11
Table 6.1 C51 Core SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ACC E0H Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
B F0H B Register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
AUXC F1H C Register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0
PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P
SP 81H Stack Pointer 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
DPL 82H Data Pointer Low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0
DPH 83H Data Pointer High byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0
DPL1 84H Data Pointer 1 Low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPH1 85H Data Pointer 1 High byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
INSCON 86H Data pointer select -0--00-0 - BKS0 - - DIV MUL - DPS
Table 6.2 Power and Clock control SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON 87H Power Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
SUSLO 8EH Suspend Mode Control 00000000 SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0

SH79F6441
12
Table 6.3 Flash Control SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_OFF
SET FBH
Bank0 Offset Register for Programming 00000000 IB_OFF
SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0
IB_DATA FCH
Bank0 Data Register for Programming 00000000 IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
IB_CON1 F2H
Bank0 Flash Memory Control Register 1 00000000 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0
IB_CON2 F3H
Bank0 Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0
IB_CON3 F4H
Bank0 Flash Memory Control Register 3 ----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0
IB_CON4 F5H
Bank0 Flash Memory Control Register 4 ----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0
IB_CON5 F6H
Bank0 Flash Memory Control Register 5 ----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
XPAGE F7H
Bank0 Programming address selection
register 00000000 XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
FLASHCON A7H
Bank0 Flash access control ------00 - - - - - - CRC_FAC FAC
Table 6.4 WDT SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTSTAT B1H
Bank0 Watchdog Timer Control 0-000000* WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
Note: * : RSTSTAT initial value is determined by different RESET.
Table 6.5 CLKCON SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKCON B2H
Bank0 System Clock Control Register 111000X- 32k_
SPDUP CLKS1 CLKS0 SCMIF HFON FS AHUM -
Note: X indicates that the reset value of AHUM is indefinite. It is given by OP_AHRV code option. See the code option chapter for details.

SH79F6441
13
Table 6.6 Interrupt SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN0 A8H
Bank0 Interrupt Enable Control 0 00000000 EA EADC ET3 ES0 EPCA1 EX1 EPCA0 EX0
IEN1 A9H
Bank0 Interrupt Enable Control 1 00000000 ESCM ELPD EX2 EX3 EX4 EPWM1 EPWM0 ETWI
IEN2 AAH
Bank0 Interrupt Enable Control 2 --000000 - - EPCA2 ESPI EPWM2 ECRC ES2 ES1
IENC BAH
Bank0 Interrupt channel enable control 00000000 EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40
IPH0 B4H
Bank0 Interrupt Priority Control High 0 00000000 PINTH PADCH PT3H PS0H PCF1H PX1H PCF0H PX0H
IPL0 B8H
Bank0 Interrupt Priority Control Low 0 00000000 PINTL PADCL PT3L PS0L PCF1L PX1L PCF0L PX0L
IPH1 B5H
Bank0 Interrupt Priority Control High 1 00000000 PSCMH PLPDH PX2H PX3H PX4H PPWM1H PPWM0H PTWIH
IPL1 B9H
Bank0 Interrupt Priority Control Low 1 00000000 PSCML PLPDL PX2L PX3L PX4L PPWM1L PPWM0L PTWIL
EXF0 E8H
Bank0 External interrupt Control 0 00000000 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 IE3 IE2
EXF1 D8H
Bank0 External interrupt Control 1 00000000 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40
EXCON 8BH
Bank0 External interrupt sampling control 00000000 I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0
TCON 88H
Bank0 External Interrupt 0/1 Control Mode Register ----0000 - - - - IE1 IT1 IE0 IT0
Table 6.7 TWI SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TWICON C8H
Bank0 TWI control register 00000000 TOUT ENTWI STA STO TWINT AA TFREE EFREE
TWISTA D1H
Bank0 TWII status register 11111000 TWISTA.7 TWISTA.6 TWISTA.5 TWISTA.4 TWISTA.3 CR.1 CR.0 ETOT
TWIBR 8AH
Bank0 TWI bit rate register 00000000 TWIBR.7 TWIBR.6 TWIBR.5 TWIBR.4 TWIBR.3 TWIBR.2 TWIBR.1 TWIBR.0
TWITOUT E6H
Bank0 Timeout for bus low level count register 00----0- CNT1 CNT0 - - - - TWIPCR -
TWIDAT 8DH
Bank0 TWI data register 00000000 TWIDAT.7 TWIDAT.6 TWIDAT.5 TWIDAT.4 TWIDAT.3 TWIDAT.2 TWIDAT.1 TWIDAT.0
TWIADR 8CH
Bank0 TWI address register 00000000 TWA.6 TWA.5 TWA.4 TWA.3 TWA.2 TWA.1 TWA.0 GC
TWIAMR 8FH
Bank0 TWI address mask register 0000000- TWIAMR.7 TWIAMR.6 TWIAMR.5 TWIAMR.4 TWIAMR.3 TWIAMR.2 TWIAMR.1 -
TWTFREE
89H
Bank0 Timeout for bus high level count register
00000000 TWTFREE.7 TWTFREE.6 TWTFREE.5 TWTFREE.4 TWTFREE.3 TWTFREE.2 TWTFREE.1 TWTFREE.0

SH79F6441
14
Table 6.8 Port SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0 80H
Bank0 8-bit Port0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1 90H
Bank0 8-bit Port1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2 A0H
Bank0 8-bit Port2 00000000 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1
P2.0
P3 B0H
Bank0 8-bit Port3 00000000 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P4 C0H
Bank0 8-bit Port4 00000000 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
P5 80H
Bank1 2-bit Port5 ------00 - - - - - - P5.1 P5.0
P0CR E1H
Bank0 Port0 input/output direction control
00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR E2H
Bank0 Port1 input/output direction control
00000000 P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
P2CR E3H
Bank0 Port2 input/output direction control
00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR E4H
Bank0 Port3 input/output direction control
00000000 P3CR.7 P3CR.6 P3CR.5 P3CR.4 P3CR.3 P3CR.2 P3CR.1 P3CR.0
P4CR E5H
Bank0 Port4 input/output direction control
00000000 P4CR.7 P4CR.6 P4CR.5 P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0
P5CR 8AH
Bank1 Port5 input/output direction control
------00 - - - - - - P5CR.1 P5CR.0
P0PCR E9H
Bank0 Internal pull-high enable for Port0 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR EAH
Bank0 Internal pull-high enable for Port1 00000000 P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR EBH
Bank0 Internal pull-high enable for Port2 00000000 P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR ECH
Bank0 Internal pull-high enable for Port3 00000000 P3PCR.7 P3PCR.6 P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 P3PCR.1 P3PCR.0
P4PCR EDH
Bank0 Internal pull-high enable for Port4 00000000 P4PCR.7 P4PCR.6 P4PCR.5 P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0
P5PCR 8BH
Bank1 Internal pull-high enable for Port5 ------00 - - - - - - P5PCR.1 P5PCR.0
PIMS0 D2H
Bank0 Port input mode selection 00000000 P07S P06S P01S P00S P22S P21S P11S P10S
PIMS1 D9H
Bank0 Port input mode selection 00000000 P27S P26S P25S P24S P43S P42S P34S P33S
PIMS2 DBH
Bank0 Port input mode selection ------00 - - - - - - P46S P45S

SH79F6441
15
Table 6.9 Timer SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
T3CON 88H
Bank1 Timer/Counter3 control 0-00-000 TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0
TL3 8CH
Bank1 Timer/Counter3 low byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0
TH3 8DH
Bank1 Timer/Counter3 high byte 00000000 TH3.7 TH3.6 TH3.5 TH3.4 TH3.3 TH3.2 TH3.1 TH3.0
Table 6.10 EUART SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON 87H
Bank0 Power & serial control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
SCON 98H
Bank0 EUART0 serial control 00000000 SM0/FE SM1/RXOV SM2/TXCOL
REN TB8 RB8 TI RI
SBUF 99H
Bank0 EUART0 serial data buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
SADEN 9BH
Bank0 EUART0 slave address mask 00000000 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
SADDR 9AH
Bank0 EUART0 slave address 00000000 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
SBRTH 9DH
Bank0 EUART0 baud rate generator high 00000000 SBRTEN SBRT.14 SBRT.13 SBRT.12 SBRT.11 SBRT.10 SBRT.9 SBRT.8
SBRTL 9CH
Bank0 EUART0 baud rate generator low 00000000 SBRT.7 SBRT.6 SBRT.5 SBRT.4 SBRT.3 SBRT.2 SBRT.1 SBRT.0
SFINE 9EH
Bank0 EUART0 baud rate generator
fine tuning ----0000 - - - - BFINE.3 BFINE.2 BFINE.1 BFINE.0
SCON1 A0H
Bank1 EUART1 serial control 00000000 SM10/FE1 SM11/
RXOV1 SM12/ TXCOL1 REN1 TB18 RB18 TI1 RI1
SBUF1 A1H
Bank1 EUART1 serial data buffer 00000000 SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
SADEN1 A3H
Bank1 EUART1 slave address mask 00000000 SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
SADDR1 A2H
Bank1 EUART1 slave address 00000000 SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0
SBRTH1 A5H
Bank1 EUART1 baud rate generator high 00000000 SBRTEN1 SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8
(to be continued)

SH79F6441
16
(continue)
SBRTL1 A4H
Bank1 EUART1 baud rate generator low 00000000 SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0
SFINE1 A6H
Bank1 EUART1 baud rate generator
fine tuning ----0000 - - - - BFINE1.3 BFINE1.2 BFINE1.1 BFINE1.0
PCON1 A7H
Bank1 Serial control register 1 00------ SMOD1 SSTAT1 - - - - - -
SCON2 90H
Bank1 EUART2 serial control 00000000 SM20/FE2 SM21/
RXOV2 SM22/ TXCOL2 REN2 TB28 RB28 TI2 RI2
SBUF2 91H
Bank1 EUART2 serial data buffer 00000000 SBUF2.7 SBUF2.6 SBUF2.5 SBUF2.4 SBUF2.3 SBUF2.2 SBUF2.1 SBUF2.0
SADEN2 93H
Bank1 EUART2 slave address mask 00000000 SADEN2.7 SADEN2.6 SADEN2.5 SADEN2.4 SADEN2.3 SADEN2.2 SADEN2.1 SADEN2.0
SADDR2 92H
Bank1 EUART2 slave address 00000000 SADDR2.7 SADDR2.6 SADDR2.5 SADDR2.4 SADDR2.3 SADDR2.2 SADDR2.1 SADDR2.0
SBRTH2 95H
Bank1 EUART2 baud rate generator high 00000000 SBRTEN2 SBRT2.14 SBRT2.13 SBRT2.12 SBRT2.11 SBRT2.10 SBRT2.9 SBRT2.8
SBRTL2 94H
Bank1 EUART2 baud rate generator low 00000000 SBRT2.7 SBRT2.6 SBRT2.5 SBRT2.4 SBRT2.3 SBRT2.2 SBRT2.1 SBRT2.0
SFINE2 96H
Bank1 EUART2 baud rate generator
fine tuning ----0000 - - - - BFINE2.3 BFINE2.2 BFINE2.1 BFINE2.0
PCON2 97H
Bank1 Serial control register 2 00------ SMOD2 SSTAT2 - - - - - -
Table 6.11 SPI SFRs
Mnem Add Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPCON A2H
Bank0 SPI control register 00000000 DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0
SPSTA F8H
Bank0 SPI status register 00000--- SPEN SPIF MODF WCOL RXOV - - -
SPDAT A3H
Bank0 SPI data register 00000000 SPDAT7 SPDAT6 SPDAT5 SPDAT4 SPDAT3 SPDAT2 SPDAT1 SPDAT0

SH79F6441
17
Table 6.12ADC SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADCON1 93H
Bank0 ADC control1 00000000 ADON ADCIF REFC XTRGEN PCA
TRGEN PWM TRGEN TIM TRGEN GO/DONE
—---—-----—
ADCON2 92H
Bank0 ADC control2 0000-000 VBG GRP2 GRP1 GRP0 - TGAP2 TGAP1 TGAP0
SEQCON 91H
Bank0 Mapping control register 0----000 ALR - - - - REG2 REG1 REG0
SEQCHX 9FH
Bank0 ADC channel register ----0000 - - - - SEQx3 SEQx2 SEQx1 SEQx0
ADCH1 95H
Bank0 ADC channel1 00000000 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADCH2 A6H
Bank0 ADC channel2 --000000 - - CH13 CH12 CH11 CH10 CH9 CH8
ADDXL 96H
Bank0 Low byte of the ADC results 0000---- A3 A2 A1 A0 - - - -
ADDXH 97H
Bank0 High byte of the ADC results 00000000 A11 A10 A9 A8 A7 A6 A5 A4
ADT 94H
Bank0 ADC time configuration 00000000 TADC3 TADC2 TADC1 TADC0 TS3 TS2 TS1 TS0
Table 6.13PWM SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWM0CON
C7H
Bank0 PWM0 control register 00000000 PWM0EN PWM0S PWM0CK2 PWM0CK1 PWM0CK0 PWM0IE PWM0IF PWM0SS
PWM1CON
B6H
Bank0 PWM1 control register 00000000 PWM1EN PWM1S PWM1CK2 PWM1CK1 PWM1CK0 PWM1IE PWM1IF PWM1SS
PWM2CON
B7H
Bank0 PWM2 control register 00000000 PWM2EN PWM2S PWM2CK2 PWM2CK1 PWM2CK0 PWM2IE PWM2IF PWM2SS
PWM0PH CDH
Bank0
Period control high byte of
12 byte PWM0 ----0000 - - - - PWM0P.11 PWM0P.10 PWM0P.9 PWM0P.8
PWM0PL CCH
Bank0
Period control low byte of
12 byte PWM0 00000000 PWM0P.7 PWM0P.6 PWM0P.5 PWM0P.4 PWM0P.3 PWM0P.2 PWM0P.1 PWM0P.0
PWM1PH AFH
Bank0 Period control high byte of
12 byte PWM1
----0000 - - - - PWM1P.11 PWM1P.10 PWM1P.9 PWM1P.8
PWM1PL AEH
Bank0 Period control low byte of
12 byte PWM1
00000000 PWM1P.7 PWM1P.6 PWM1P.5 PWM1P.4 PWM1P.3 PWM1P.2 PWM1P.1 PWM1P.0
PWM2PH BDH
Bank0 Period control high byte of
12 byte PWM2
----0000 - - - - PWM2P.11 PWM2P.10 PWM2P.9 PWM2P.8
PWM2PL BCH
Bank0 Period control low byte of
12 byte PWM2 00000000 PWM2P.7 PWM2P.6 PWM2P.5 PWM2P.4 PWM2P.3 PWM2P.2 PWM2P.1 PWM2P.0
(to be continued)

SH79F6441
18
(continue)
PWM0DH CFH
Bank0
Duty control high byte of
12 byte PWM0
----0000 - - - - PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8
PWM0DL CEH
Bank0
Duty control high byte of
12 byte PWM0 00000000 PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0
PWM1DH A5H
Bank0
Duty control high byte of
12 byte PWM1 ----0000 - - - - PWM1D.11 PWM1D.10 PWM1D.9 PWM1D.8
PWM1DL A4H
Bank0 Duty control high byte of
12 byte PWM1 00000000 PWM1D.7 PWM1D.6 PWM1D.5 PWM1D.4 PWM1D.3 PWM1D.2 PWM1D.1 PWM1D.0
PWM2DH BFH
Bank0 Duty control high byte of
12 byte PWM2
----0000 - - - - PWM2D.11 PWM2D.10 PWM2D.9 PWM2D.8
PWM2DL BEH
Bank0 Duty control high byte of
12 byte PWM2
00000000 PWM2D.7 PWM2D.6 PWM2D.5 PWM2D.4 PWM2D.3 PWM2D.2 PWM2D.1 PWM2D.0
Table 6.14PCA SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0CF 98H
Bank1 PCA0 flag register 0-----00 CF0 - - - - - P0CCF1 P0CCF0
P0CMD 99H
Bank1 PCA0 mode register 00---000 ECF0 P0SDEN - - - P0CPS2 P0CPS1 P0CPS0
P0CPM0 9AH
Bank1 PCA0 capture/
compare module 0 register 00000000 P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0
P0CPM1 9BH
Bank1 PCA0 capture/
compare Module 1 register 00000000 P0SMP1 P0SMN1 P0FSP1 P0FSN1 P0ECOM1 P0TCP1 P0MAT1 P0ECCF1
P0TOPL 9EH
Bank1 PCA0 count maximum low byte 11111111 P0TOPL.7 P0TOPL.6 P0TOPL.5 P0TOPL.4 P0TOPL.3 P0TOPL.2 P0TOPL.1 P0TOPL.0
P0TOPH 9FH
Bank1 PCA0 count maximum high byte 11111111 P0TOPH.7 P0TOPH.6 P0TOPH.5 P0TOPH.4 P0TOPH.3 P0TOPH.2 P0TOPH.1 P0TOPH.0
P0CPL0 9CH
Bank1 PCA0 capture/
compare module 0 low byte 00000000 P0CPL0.7 P0CPL0.6 P0CPL0.5 P0CPL0.4 P0CPL0.3 P0CPL0.2 P0CPL0.1 P0CPL0.0
P0CPH0 9DH
Bank1 PCA0 capture/
compare module 0 high byte 00000000 P0CPH0.7 P0CPH0.6 P0CPH0.5 P0CPH0.4 P0CPH0.3 P0CPH0.2 P0CPH0.1 P0CPH0.0
P0CPL1 D4H
Bank1 PCA0 capture/
compare module 1 low byte 00000000 P0CPL1.7 P0CPL1.6 P0CPL1.5 P0CPL1.4 P0CPL1.3 P0CPL1.2 P0CPL1.1 P0CPL1.0
P0CPH1 D5H
Bank1 PCA0 capture/
compare module 1 high byte 00000000 P0CPH1.7 P0CPH1.6 P0CPH1.5 P0CPH1.4 P0CPH1.3 P0CPH1.2 P0CPH1.1 P0CPH1.0
P1CF C0H
Bank1 PCA1 flag register 0-----00 CF1 - - - - - P1CCF1 P1CCF0
P1CMD C1H
Bank1 PCA1 mode register 00---000 ECF1 P1SDEN - - - P1CPS2 P1CPS1 P1CPS0
P1CPM0 C2H
Bank1 PCA1 capture/
compare module 0 register 00000000 P1SMP0 P1SMN0 P1FSP0 P1FSN0 P1ECOM0 P1TCP0 P1MAT0 P1ECCF0
(to be continued)

SH79F6441
19
(continue)
P1CPM1 C3H
Bank1 PCA1 Capture/
Compare Module 1 register 00000000 P1SMP1 P1SMN1 P1FSP1 P1FSN1 P1ECOM1 P1TCP1 P1MAT1 P1ECCF1
P1TOPL C6H
Bank1 PCA1 Count Maximum Low Byte 11111111 P1TOPL.7 P1TOPL.6 P1TOPL.5 P1TOPL.4 P1TOPL.3 P1TOPL.2 P1TOPL.1 P1TOPL.0
P1TOPH C7H
Bank1 PCA1 Count Maximum High Byte 11111111 P1TOPH.7 P1TOPH.6 P1TOPH.5 P1TOPH.4 P1TOPH.3 P1TOPH.2 P1TOPH.1 P1TOPH.0
P1CPL0 C4H
Bank1 PCA1 capture/
compare module 0 low byte 00000000 P1CPL0.7 P1CPL0.6 P1CPL0.5 P1CPL0.4 P1CPL0.3 P1CPL0.2 P1CPL0.1 P1CPL0.0
P1CPH0 C5H
Bank1 PCA1 capture/
compare module 0 high byte 00000000 P1CPH0.7 P1CPH0.6 P1CPH0.5 P1CPH0.4 P1CPH0.3 P1CPH0.2 P1CPH0.1 P1CPH0.0
P1CPL1 E4H
Bank1 PCA1 capture/
compare module 1 low byte 00000000 P1CPL1.7 P1CPL1.6 P1CPL1.5 P1CPL1.4 P1CPL1.3 P1CPL1.2 P1CPL1.1 P1CPL1.0
P1CPH1 E5H
Bank1 PCA1 capture/
compare module 1 high byte 00000000 P1CPH1.7 P1CPH1.6 P1CPH1.5 P1CPH1.4 P1CPH1.3 P1CPH1.2 P1CPH1.1 P1CPH1.0
P2CF C8H
Bank1 PCA2 Flag register 0-----00 CF2 - - - - - P2CCF1 P2CCF0
P2CMD C9H
Bank1 PCA2 Mode register 00---000 ECF2 P2SDEN - - - P2CPS2 P2CPS1 P2CPS0
P2CPM0 CAH
Bank1 PCA2 Capture/
Compare Module 0 register 00000000 P2SMP0 P2SMN0 P2FSP0 P2FSN0 P2ECOM0 P2TCP0 P2MAT0 P2ECCF0
P2CPM1 CBH
Bank1 PCA2 Capture/
Compare Module 1 register 00000000 P2SMP1 P2SMN1 P2FSP1 P2FSN1 P2ECOM1 P2TCP1 P2MAT1 P2ECCF1
P2TOPL CEH
Bank1 PCA2 Count Maximum Low Byte 11111111 P2TOPL.7 P2TOPL.6 P2TOPL.5 P2TOPL.4 P2TOPL.3 P2TOPL.2 P2TOPL.1 P2TOPL.0
P2TOPH CFH
Bank1 PCA2 Count Maximum High Byte 11111111 P2TOPH.7 P2TOPH.6 P2TOPH.5 P2TOPH.4 P2TOPH.3 P2TOPH.2 P2TOPH.1 P2TOPH.0
P2CPL0 CCH
Bank1 PCA2 capture/
compare module 0 low byte 00000000 P2CPL0.7 P2CPL0.6 P2CPL0.5 P2CPL0.4 P2CPL0.3 P2CPL0.2 P2CPL0.1 P2CPL0.0
P2CPH0 CDH
Bank1 PCA2 capture/
compare module 0 high byte 00000000 P2CPH0.7 P2CPH0.6 P2CPH0.5 P2CPH0.4 P2CPH0.3 P2CPH0.2 P2CPH0.1 P2CPH0.0
P2CPL1 F4H
Bank1 PCA2 capture/
compare module 1 low byte 00000000 P2CPL1.7 P2CPL1.6 P2CPL1.5 P2CPL1.4 P2CPL1.3 P2CPL1.2 P2CPL1.1 P2CPL1.0
P2CPH1 F5H
Bank1 PCA2 capture/
compare module 1 high byte 00000000 P2CPH1.7 P2CPH1.6 P2CPH1.5 P2CPH1.4 P2CPH1.3 P2CPH1.2 P2CPH1.1 P2CPH1.0
PCACON D8H
Bank1 PCA enable register -----000 - - - - - PR2 PR1 PR0
P0FORCE
DCH
Bank1 PCA0 forced output control register --00--00 - - P0OSC1 P0OSC0 - - P0FCO1 P0FCO0
P1FORCE
ECH
Bank1 PCA1 forced output control register --00--00 - - P1OSC1 P1OSC0 - - P1FCO1 P1FCO0
P2FORCE
FCH
Bank1 PCA2 forced output control register --00--00 - - P2OSC1 P2OSC0 - - P2FCO1 P2FCO0

SH79F6441
20
Table 6.15LPD SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LPDCON B3H
Bank0 LPD control register 00000--- LPDEN LPDF LPDV LPDIF LPDMD - - -
LPDSEL BBH
Bank0 LPD level selection register ----0000 - - - - LPDS3 LPDS2 LPDS1 LPDS0
Table 6.16 CRC SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CRCCON C1H
Bank0 CRC verify control 00------ CRC_GO CRCIF - - - - - -
CRCDL C2H
Bank0 CRC verify result low byte 00000000 CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0
CRCDH C3H
Bank0 CRC verify result high byte 00000000 CRCD15 CRCD14 CRCD13 CRCD12 CRCD11 CRCD10 CRCD9 CRCD8
CRCSTAL D4H
Bank0 CRC start address register 00000000 CRCSTA.7 CRCSTA.6 CRCSTA.5 CRCSTA.4 CRCSTA.3 CRCSTA.2 CRCSTA.1 CRCSTA.0
CRCSTAH
D5H
Bank0 CRC start address register 00000000 CRCSTA.15 CRCSTA.14 CRCSTA.13 CRCSTA.12
CRCSTA.11 CRCSTA.10 CRCSTA.9 CRCSTA.8
CRCSTOL
DCH
Bank0 CRC end address register 00000000 CRCSTO.7 CRCSTO.6 CRCSTO.5 CRCSTO.4 CRCSTO.3 CRCSTO.2 CRCSTO.1 CRCSTO.0
CRCSTOH
DDH
Bank0 CRC end address register 00000000 CRCSTO.15 CRCSTO.14
CRCSTO.13 CRCSTO.12 CRCSTO.11 CRCSTO.10 CRCSTO.9 CRCSTO.8
Table 6.17 LCM SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
UART0CR C4H
Bank0 TXD0 & RXD0 selection register -011-010 - TX0CR2 TX0CR1 TX0CR0 - RX0CR2 RX0CR1 RX0CR0
UART1CR C5H
Bank0 TXD1 & RXD1 selection register -001-000 - TX1CR2 TX1CR1 TX1CR0 - RX1CR2 RX1CR1 RX1CR0
TWICR C6H
Bank0 SCK & SDA selection register -011-010 - SCKCR2 SCKCR1 SCKCR0 - SDACR2 SDACR1 SDACR0
PWMCR CAH
Bank0 PWM0 & PWM1 selection register -001-011 - PW1CR2 PW1CR1 PW1CR0 - PW0CR2 PW0CR1 PW0CR0
CEXCR CBH
Bank0 P0CEX1 & P0CEX0
selection register -011-101 - CE1CR2 CE1CR1 CE1CR0 - CE0CR2 CE0CR1 CE0CR0
ECICR C9H
Bank0 ECI0 & INT2 selection register -000-011 - INT2CR2 INT2CR1 INT2CR0 - ECICR2 ECICR1 ECICR0
Note: - : reservedbits.