Sino Wealth SH69P561 User manual

SH69P561/K561
OTP/MASK 4K 4-bit Micro-controller With LCD Driver & 8-bit SAR ADC
1 V2.1
Features
SH6610D-Based Single-Chip 4-bit Micro-Controller With
LCD Driver & 8-bit SAR ADC
OTP ROM: 4K X 16 bits (SH69P561)
MASK ROM: 4K X 16 bits (SH69K561)
RAM: 274 X 4bits
- 58 System control register
- 216 Data memory
- 72 bits LCD RAM
Operation Voltage:
- fOSC = 32.768kHz - 4MHz, VDD = 2.4V - 5.5V
- fOSC = 4MHz - 8MHz, VDD = 4.5V - 5.5V
15 CMOS Bi-directional I/O Pins
8-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Loaded Timer/Counter
Warm-Up Timer
Powerful Interrupt Sources:
- A/D Interrupt
- Timer0 Interrupt
- Timer1 Interrupt
- External Interrupts: PORTB (Rising/Falling Edge)
2 Clock Oscillator
OSC:
- Crystal Oscillator: 32.768kHz
- RC Oscillator: 262kHz
OSCX:
- Ceramic/Crystal Oscillator: 400kHz - 8MHz
- RC Oscillator: 400kHz - 8MHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT And STOP
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) (Code Option)
LCD Driver:
18SEG X 4COM (1/4 duty, 1/3 bias)
2 Channels 10-bit PWM output
5 Channels 8-bit Resolution Analog/Digital Converter
(ADC)
Built-in Pull-high/Pull-low Resistor for PORTA - PORTE
Built-in Alarm Generator
Built-in Electroluminescent Light (EL-light) Driver
ROM Data Read Table function
Zero Cross Detect function for AC Power Line
LCD shared as LED matrix (Code Option)
LCD SEG 9-28 shared with scan output
OTP type & Code Protect (SH69P561)
MASK type (SH69K561)
44-pin QFP package
General Description
SH69P561/69K561 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer, LCD
driver, I/O ports, EL-light driver, watchdog timer, 5 channels 8-bit ADC, alarm generator, low voltage reset, 2 channels 10-bit
high speed PWM output, zero cross detect function. This chip builds in a dual-oscillator to enhance the total chip performance.
SH69P561/69K561 is suitable for the home appliance application.

SH69P561/K561
2
Pin Configuration (44 QFP Package)
12 3 45678 9 10 11
44
43
42
41
40
39
38
37
34
35
36
SH69P561/K561
PORTE.0/SEG5
PORTE.1/SEG6
PORTE.2/SEG7
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
PORTE.3/SEG8
12
13
14
15
16
17
18
19
22
21
20
232425
26
2728
33 31
32 30 29
PORTC.3/T0
PORTA.0/VREF/AN0
PORTA.1/AN1 PORTA.2/AN2 PORTB.0/AN4 PORTB.1/AN5
PORTB.2/ELP
PORTB.3/ELC
PORTC.0/PWM0 PORTC.1/PWM1
PORTC.2/BUZ
SEG20 COM1 COM2 COM3 COM4 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21
RESET
TEST
OSCI
VDD
GND
OSCXI
OSCXO
NC
NC
NC
OSCO

SH69P561/K561
3
Pin Description (44 QFP Package)
Pin No. Pin Name I/O Description
1 PORTC.3
/T0
I/O
I
Bit programmable I/O
Shared with T0 input
2 PORTC.2
/BUZ
I/O
O
Bit programmable I/O
Shared with BUZ output
3 PORTC.1
/PWM1
I/O
O
Bit programmable I/O
Shared with PWM1 output
4 PORTC.0
/PWM0
I/O
O
Bit programmable I/O
Shared with PWM0 output
5 - 6 PORTB.3 - 2
/ELC-ELP
I/O
I
O
Bit programmable I/O
Vector interrupt (active falling/rising edge)
Shared with EL-light driving circuit output
7 - 8 PORTB.1 - 0
/AN5 - AN4
I/O
I
I
Bit programmable I/O
Vector interrupt (active falling/rising edge)
Shared with ADC input channel AN5 - AN4
9 - 10 PORTA.2 - 1
/AN2 - AN1
I/O
I
Bit programmable I/O
Shared with ADC input channel AN2 - AN1
11
PORTA.0
/VREF
/AN0
I/O
I
I
Bit programmable I/O
Shared with external ADC VREF input
Shared with ADC input channel AN0
12 VDD P Power supply pin
13 GND P Ground pin
14 OSCXI I
OSCX input connected to high-frequency ceramic/crystal oscillator or
external resistor
15 OSCXO O OSCX output connected to high-frequency ceramic/crystal oscillator
19 OSCO O OSC output connected to low-frequency crystal oscillator
20 OSCI I OSC input connected to low-frequency crystal or external resistor
21 RESET I Reset input (active low, Schmitt trigger input)
22 TEST I Test pin pull-low internally (No connection for users)
23 - 26 COM1 - 4 O Common signal output for LCD display
27 - 40 SEG26 - 13 O Segment signal output for LCD display shared with output port
41 - 44 PORTE.3 - 0
/SEG8 - 5
I/O
O
Bit programmable I/O
Shared with SEG8 - 5
16 - 18 NC No connection for users
OTP Programming Pin Description* (44 QFP Package)
Pin No. Symbol I/O Sharing Pin Description
12 VDD P VDD, AVDD Programming Power supply (+5.5V)
21 VPP P RESET Programming high voltage Power supply (+11.0V)
13 GND P AGND, GND Ground
20 SCK I OSCI Programming Clock input Pin/Pad
11 SDA I/O PORTA.0 Programming Data Pin/Pad
*: Only SH69P561 has the OTP Program Mode, SH69K561 has not the OTP Program Mode

SH69P561/K561
4
Block Diagram
Oscillator
CPU
WDT RC
PORTC.3 - 0
LCD/LED Driver
Timer 0
Watchdog
Timer
Reset Circuit
Timer 1
OSCI/SCK
OSCXO
GND
PORTA.2 - 0
RESET
PORTA.2 - 0
ADC VREF
AN2 - AN0
PORTB.3 - 0
AN5 - AN4
PORTB.3 - 0
PORTC.3 - 0
8 bits
ADC Circuit
10 bits
PWM Circuit
Power Circuit
SEG13 - 26
OSCXI
OSCO
PORTE.3 - 0 PORTE.3 - 0
/SEG8 - 5
COM1 - 4
TEST
EL-Light Driver
Alarm Generator
VDD
RAM
216 X 4 bits
Data Memory
ROM
4096 X 16 bits
RAM
58 X 4 bits
System Register
RAM
168 bits
LCD Data Memory

SH69P561/K561
5
Functional Descriptions
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code bit7-bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM
(3-bit) and DPL (4-bit). The addressing range is
000H--3FFH. Pseudo index address (INX) is used to read or
write Data memory, then RAM address bit9 - Bit0 which
comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 8 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC with the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU enters STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $027, $380 - $391
Data memory: $028 - $0FF
LCD RAM space: $304 - $319, $35C - $369
RAM Bank Table:
Bank 0
B = 0
Bank 1
B = 1
Bank 6
B = 6
Bank 7
B = 7
$028 - $07F $080 - $0FF $300 - $37F $380 - $3FF
Where, B: RAM bank bit use in instructions

SH69P561/K561
6
2.2. Configuration of System Register:
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$00 IEAD IET0 IET1 IEPB R/W Interrupt enable flags register
$01 IRQAD IRQT0 IRQT1 IRQPB R/W Interrupt request flags register
$02 - T0M.2 T0M.1 T0M.0 R/W Bit2-0: Timer0 Mode register
$03 - T1M.2 T1M.1 T1M.0 R/W Bit2-0: Timer1 Mode register
$04 T0L.3 T0L.2 T0L.1 T0L.0 R/W Timer0 load/counter low nibble register
$05 T0H.3 T0H.2 T0H.1 T0H.0 R/W Timer0 load/counter high nibble register
$06 T1L.3 T1L.2 T1L.1 T1L.0 R/W Timer1 load/counter low nibble register
$07 T1H.3 T1H.2 T1H.1 T1H.0 R/W Timer1 load/counter high nibble register
$08 0 PA.2 PA.1 PA.0 R/W
Bit2-0: PORTA data register
Bit3 must be cleared to “0” by the User’s program and
always be kept up.
Refer to I/O note
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB data register
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC data register
$0B 0 0 0 0 R/W
All bits of this register must be cleared to “0” by the
User’s program and always be kept up.
Refer to I/O note
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE data register
$0D PULLEN PH/PL OXS OXON R/W
Bit0: Turn on OSCX oscillator control register
Bit1: System clock control register
Bit2: Port pull-high and falling edge interrupt or pull-low
and rising edge interrupt control register
Bit3: Port pull-high/low enable control register
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch register
$0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register
$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble register
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble register
$12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble register
$13 T0S1 T0E1 T0S0 T0E0 R/W
Bit0: T0 clock edge in Timer0 control register
Bit1: Timer0 clock source control register
Bit2: T0 clock edge in Timer1 control register
Bit3: Timer1 clock source control register
$14 PIEN.3 PIEN.2 PIEN.1 PIEN.0 R/W Bit3-0: PORTB interrupt enable flags register
$15 PIF.3 PIF.2 PIF.1 PIF.0 R/W Bit3-0: PORTB interrupt request flags register
$16 - ALMF1 ALMF0 PAM0 R/W Bit0: Alarm output enable control register
Bit2-1: Alarm carrier frequency control register
$17 AEC3 AEC2 AEC1 AEC0 R/W Alarm envelope control register
$18 1 PACR.2 PACR.1 PACR.0 R/W
Bit2-0: PORTA input/output control register
Bit3 must be set to “1” by the User’s program and
always be kept up.
Refer to I/O note
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 R/W PORTB input/output control register
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 R/W PORTC input/output control register
$1B 1 1 1 1 R/W
All bits of this register must be set to “1” by the User’s
program and always be kept up.
Refer to I/O note
$1C PECR.3 PECR.2 PECR.1 PECR.0 R/W PORTE input/output control register

SH69P561/K561
7
Configuration of System Register (Continued)
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$1D - ELF ELPF ELON R/W
Bit0: EL-light on/off control register
Bit1: EL-light driver charge frequency control register
Bit2: EL-li
g
ht driver dischar
g
e fre
q
uenc
y
control re
g
iste
r
$1E
WDT
WDT.2 WDT.1 WDT.0 R/W
R
Bit2-0: Watchdog timer control register
Bit3: WDT overflow flag register
$1F - - - - - Reserved
$20 VREFS ACR2 ACR1 ACR0 R/W Bit2-0: ADC port configuration control register
Bit3: Internal/External reference voltage control register
$21 ADCON CH2 CH1 CH0 R/W Bit2-0: ADC channel control register
Bit3: ADC module operate control register
$22 GO/ DONE TADC1 TADC0 ADCS R/W
Bit0: A/D Conversion Time control register
Bit2-1: A/D Clock Period control register
Bit3: ADC status flag register
$23 A3 A2 A1 A0 R ADC data low nibble register
$24 A7 A6 A5 A4 R ADC data high nibble register
$25 - LCDON RLCD1 RLCD0 R/W Bit1-0: Set LCD bias resistor register
Bit2: LCD display on control register
$26 LPS1 LPS0 0 1 R/W
Bit0 must be set to “1” by the User’s program and
always be kept up.
Bit1 must be cleared to “0” by the User’s program
and always be kept up.
Bit3-2: Different LCD frame frequency control register
$27 LVD O/S2 O/S1 0 R/W
Bit0 must be cleared to “0” by the User’s program
and always be kept up.
Refer to LCD note
Bit1: PORTE as LCD SEG5-8 control register
Bit2: LCD SEG13-26 as output control register
Bit3: LCD Volta
g
e de
g
rade control re
g
iste
r
$380 PWM0S T0CK1 T0CK0 PWM0 R/W
Bit0: PWM0 output enabled control register
Bit2-1: PWM0 clock control register
Bit3: PWM0 output mode of duty cycle control register
$381 PWM1S T1CK1 T1CK0 PWM1 R/W
Bit0: PWM1 output enabled control register
Bit2-1: PWM1 clock control register
Bit3: PWM1 output mode of duty cycle control register
$382 PP0.3 PP0.2 PP0.1 PP0.0 R/W PWM0 period low nibble register
$383 PP0.7 PP0.6 PP0.5 PP0.4 R/W PWM0 period middle nibble register
$384 - - PP0.9 PP0.8 R/W Bit1-0: PWM0 period high register
$385 PD0.3 PD0.2 PD0.1 PD0.0 R/W PWM0 duty low nibble register
$386 PD0.7 PD0.6 PD0.5 PD0.4 R/W PWM0 duty middle nibble register
$387 - - PD0.9 PD0.8 R/W Bit1-0: PWM0 duty high register
$388 PP1.3 PP1.2 PP1.1 PP1.0 R/W PWM1 period low nibble register
$389 PP1.7 PP1.6 PP1.5 PP1.4 R/W PWM1 period middle nibble register
$38A - - PP1.9 PP1.8 R/W Bit1-0: PWM1 period high register
$38B PD1.3 PD1.2 PD1.1 PD1.0 R/W PWM1 duty low nibble register
$38C PD1.7 PD1.6 PD1.5 PD1.4 R/W PWM1 duty middle nibble register
$38D - - PD1.9 PD1.8 R/W Bit1-0: PWM1 duty high register
$38E RDT.3 RDT.2 RDT.1 RDT.0 R/W ROM Data table address/data register
$38F RDT.7 RDT.6 RDT.5 RDT.4 R/W ROM Data table address/data register
$390 RDT.11 RDT.10 RDT.9 RDT.8 R/W ROM Data table address/data register
$391 RDT.15 RDT.14 RDT.13 RDT.12 R/W ROM Data table address/data register

SH69P561/K561
8
3. ROM
The ROM can address 4096 X 16 bits of program area from $000 to $FFF.
3.1. Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
Address Instruction Remarks
$000 JMP* Jump to RESET service routine
$001 JMP* Jump to ADC interrupt service routine
$002 JMP* Jump to TIMER0 interrupt service routine
$003 JMP* Jump to TIMER1 interrupt service routine
$004 JMP* Jump to PORTB interrupt service routine
*JMP instruction can be replaced by any instruction.
3.2. ROM Data Read Table (RDT)
System Register:
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$38E RDT.3 RDT.2 RDT.1 RDT.0 R/W ROM Data table address/data register
$38F RDT.7 RDT.6 RDT.5 RDT.4 R/W ROM Data table address/data register
$390 RDT.11 RDT.10 RDT.9 RDT.8 R/W ROM Data table address/data register
$391 RDT.15 RDT.14 RDT.13 RDT.12 R/W ROM Data table address/data register
The RDT register consists of a 12-bit write-only PC address load register (RDT.11 - RDT.0) and a 16-bit read-only ROM table
data read-out register (RDT.15 - RDT.0).
To read out the ROM table data, users should fill 0 to higher 4 bits (RDT.15 - 12) first, then write the ROM table address to RDT
register (high nibble first then low nibble), after one instruction, the right data will put into RDT register automatically (write lowest
nibble of address into $38E will start the data read-out action).

SH69P561/K561
9
4. Initial State
4.1. System Register State:
Address Bit 3 Bit 2 Bit 1 Bit 0
Power On Reset
/Pin Reset
/LVR
WDT Reset
$00 IEAD IET0 IET1 IEPB 0000 0000
$01 IRQAD IRQT0 IRQT1 IRQPB 0000 0000
$02 - T0M.2 T0M.1 T0M.0 -000 -uuu
$03 - T1M.2 T1M.1 T1M.0 -000 -uuu
$04 T0L.3 T0L.2 T0L.1 T0L.0 xxxx xxxx
$05 T0H.3 T0H.2 T0H.1 T0H.0 xxxx xxxx
$06 T1L.3 T1L.2 T1L.1 T1L.0 xxxx xxxx
$07 T1H.3 T1H.2 T1H.1 T1H.0 xxxx xxxx
$08 - PA.2 PA.1 PA.0 x000 x000
$09 PB.3 PB.2 PB.1 PB.0 0000 0000
$0A PC.3 PC.2 PC.1 PC.0 0000 0000
$0B - - - - xxxx xxxx
$0C PE.3 PE.2 PE.1 PE.0 0000 0000
$0D PULLEN PH/PL OXS OXON 0100 01uu
$0E TBR.3 TBR.2 TBR.1 TBR.0 xxxx uuuu
$0F INX.3 INX.2 INX.1 INX.0 xxxx uuuu
$10 DPL.3 DPL.2 DPL.1 DPL.0 xxxx uuuu
$11 - DPM.2 DPM.1 DPM.0 -xxx -uuu
$12 - DPH.2 DPH.1 DPH.0 -xxx -uuu
$13 T0S1 T0E1 T0S0 T0E0 0000 uuuu
$14 PIEN.3 PIEN.2 PIEN.1 PIEN.0 0000 uuuu
$15 PIF.3 PIF.2 PIF.1 PIF.0 0000 0000
$16 - ALMF1 ALMF0 PAM0 -000 -uu0
$17 AEC3 AEC2 AEC1 AEC0 0000 uuuu
$18 - PACR.2 PACR.1 PACR.0 x000 x000
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 0000 0000
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 0000 0000
$1B - - - - xxxx xxxx
$1C PECR.3 PECR.2 PECR.1 PECR.0 0000 0000
$1D - ELF ELPF ELON -000 -uu0
$1E WDT WDT.2 WDT.1 WDT.0 0000 1000
$1F - - - - - - - ---- ----
$20 VREFS ACR2 ACR1 ACR0 0000 uuuu
$21 ADCON CH2 CH1 CH0 0000 0uuu
$22 GO/ DONE TADC1 TADC0 ADCS 0000 0uuu

SH69P561/K561
10
System Register States (continued)
Address Bit 3 Bit 2 Bit 1 Bit 0
Power On Reset
/Pin Reset
/LVR
WDT Reset
$23 A3 A2 A1 A0 xxxx uuuu
$24 A7 A6 A5 A4 xxxx uuuu
$25 - LCDON RLCD1 RLCD0 -000 -uuu
$26 LPS1 LPS0 - - 00xx uuxx
$27 LVD O/S2 O/S1 - 000x u00x
$380 PWM0S T0CK1 T0CK0 PWM0 0000 uuu0
$381 PWM1S T1CK1 T1CK0 PWM1 0000 uuu0
$382 PP0.3 PP0.2 PP0.1 PP0.0 xxxx uuuu
$383 PP0.7 PP0.6 PP0.5 PP0.4 xxxx uuuu
$384 - - PP0.9 PP0.8 --xx --uu
$385 PD0.3 PD0.2 PD0.1 PD0.0 xxxx uuuu
$386 PD0.7 PD0.6 PD0.5 PD0.4 xxxx uuuu
$387 - - PD0.9 PD0.8 --xx --uu
$388 PP1.3 PP1.2 PP1.1 PP1.0 xxxx uuuu
$389 PP1.7 PP1.6 PP1.5 PP1.4 xxxx uuuu
$38A - - PP1.9 PP1.8 --xx --uu
$38B PD1.3 PD1.2 PD1.1 PD1.0 xxxx uuuu
$38C PD1.7 PD1.6 PD1.5 PD1.4 xxxx uuuu
$38D - - PD1.9 PD1.8 --xx --uu
$38E RDT.3 RDT.2 RDT.1 RDT.0 xxxx uuuu
$38F RDT.7 RDT.6 RDT.5 RDT.4 xxxx uuuu
$390 RDT.11 RDT.10 RDT.9 RDT.8 xxxx uuuu
$391 RDT.15 RDT.14 RDT.13 RDT.12 xxxx uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’.
4.2. Others Initial States:
Others After any Reset
Program Counter (PC) $000
CY Undefined
Accumulator (AC) Undefined
Data Memory Undefined

SH69P561/K561
11
5. System Clock and Oscillator
The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals.
System clock = fOSC/4
5.1. Instruction Cycle Time
(1) 4/32.768kHz (≈ 122µs) for 32.768kHz oscillator.
(2) 4/262kHz (≈15.27µs) for 262kHz oscillator.
(3) 4/455kHz (≈8.79µs) for 455kHz oscillator.
(4) 4/4MHz (= 1µs) for 4MHz oscillator.
(5) 4/8MHz (= 0.5µs) for 8MHz oscillator.
5.2. Circuit Configuration
SH69P561/69K561 has two on-chip oscillation circuits: the OSC and the OSCX.
The OSC is a low frequency crystal (Typ. 32.768kHz) or RC (Typ.262kHz) determined by the code option. This is designed for
low frequency operation. The OSCX also has two types: ceramic/crystal (400k to 8MHz) or RC (400k to 8MHz) to be determined
by the code option. It is designed for high frequency operation.
It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low
operation clock. At the start of Power on reset, Pin reset and low power reset initialization, the OSC starts oscillation and OSCX
is turned off. But at the start of WDT reset initialization, the OSC starts oscillation and the OSCX remains the original state.
Immediatly after reset initialization, the OSC clock is automatically selected as the system clock input source.
CPU Clock
Low Frequency
Clock Oscillator
High Frequency
Clock Oscillator
System clock
Source Selector
& Switching control
System clock
Generator
OSCI
OSCO
OSCXO
OSCXI
Figure 1. Oscillator Block Diagram
OSCXO
OSCO
SYS CLOCK
High
frequency
operation
Low frequency operation High frequency operation
Switch from OSCX to OSC
OSCX turn off OSCX turn on
Switch from OSC to OSCX
Figure 2. Timing of System Clock Switching

SH69P561/K561
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5.3. OSC Oscillator
The OSC generates the basic clock pulses that provide the CPU and peripherals (Timer0, Timer1) with an operating clock.
(1) OSC Crystal Oscillator
OSCI
OSCO
C1
C2
32.768kHz
(2) OSC RC Oscillator
OSCI
ROSC VDD
External ROSC RC
5.4. OSCX Oscillator
OSCX has two clock oscillators. The code options select the ceramic or RC as the CPU's clock.
If the OSCX is not used, it must be masked to be Ceramic resonator and the OSCXI must be connected to GND.
(1) OSCX Crystal oscillator: 400kHz - 8MHz
OSCXI
OSCXO
C1
C2
Crystal
(2) OSCX Ceramic resonator: 400kHz - 8MHz
OSCXI
OSCXO
C1
C2
Ceramic
(3) OSCX RC Oscillator: 400kHz - 8MHz
OSCXI
ROSCX VDD
External ROSCX RC
5.5. Control of Oscillator
The oscillator control register configuration is shown as blow.
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks
$0D PULLEN PH/PL OXS OXON R/W
Bit0: Turn on OSCX oscillator control register
Bit1: System clock control register
Bit2: Port pull-high and falling edge interrupt or pull-low
and rising edge interrupt control register
Bit3: Port pull-high/low enable control register
OXON: OSCX oscillation on/off.
0: Turn off OSCX oscillation
1: Turn on OSCX oscillation
OXS: switching system clock.
0: select OSC as system clock
1: select OSCX as system clock
Programming Notes:
It takes at least 5ms for the OSCX oscillation circuit to go on until the oscillation stabilizes. When the CPU system clock
switching from OSC to OSCX, the user has to wait at least 5ms till the OSCX oscillation is activated. In addition, the start time
varies a lot with respect to oscillator characteristics and operational conditions. Therefore the waiting time depends on
applications. When switching from OSCX to OSC, and turning off OSCX in one instruction, the OSCX turns off control would be
delayed for one instruction cycle automatically to prevent CPU operation error.
If the OSCX is selected as system clock (OXS = 1,OXON = 1), but the OXON bit is cleared to 0 by an unexpected factor such as
noise, the OSCX will stop and the system clock will switch to the OSC automatically.

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5.6. Capacitor Selection for Oscillator
Ceramic Resonators
Frequency C1 C2 Recommend Type Manufacturer
ZTB 455KHz Vectron International
455kHz 47 - 100pF 47 - 100pF ZT 455E Shenzhen DGJB Electronic Co., Ltd.
ZTT 3.580M Vectron International
3.58MHz - - ZT 3.58M* Shenzhen DGJB Electronic Co., Ltd.
ZTT 4.000M Vectron International
4MHz - - ZT 4M* Shenzhen DGJB Electronic Co., Ltd.
* The specified ceramic resonator has internal built-in load capaciyies.
Crystal Oscillator
Frequency C1 C2 Recommend Type Manufacturer
DT 38 (φ3x8) KDS
32.768kHz 5 - 12.5pF 5 - 12.5pF φ3x8 - 32.768KHz Vectron International
HC-49U/S 4.000MHz Vectron International
4MHz 8 - 15pF 8 - 15pF 49S-4.000M-F16E Shenzhen DGJB Electronic Co., Ltd.
HC-49U/S 8.000MHz Vectron International
8MHz 8 - 15pF 8 - 15pF 49S-8.000M-F16E Shenzhen DGJB Electronic Co., Ltd.
Notes:
1. Capacitor values are used for design guidance only!
2. These capacitors were tested with the crystals listed above for basic start-up and operation. They are not optimized.
3. Be careful for the stray capacitance on PCB board, the user should test the performance of the oscillator over the expected
VDD and the temperature range for the application.
Before selecting crystal/ceramic, the user should consult the crystal/ceramic manufacturer for appropriate value of external
component to get best performance, visit http://www.sinowealth.com for more recommended manufactures.

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6. I/O Ports
The MCU provides 15 bi-directional I/O ports. The PORT data is put in register $08 - $0C The PORT control register ($18 - $1C)
controls the PORT as input or output. Each I/O port has an internal pull-high/pull-low resistor, which is controlled by PULLEN,
PH/PL of $0D and the data of the port, when the PORT is used as input.
Port I/O Address Map
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks
$08 0 PA.2 PA.1 PA.0 R/W
PORTA data register
Bit3 must be cleared to “0” by the User’s program
and always be kept up
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB data register
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC data register
$0B 0 0 0 0 R/W All bits of this register must be cleared to “0” by
the User’s program and always be kept up.
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE data register
$18 1 PACR.2 PACR.1 PACR.0 R/W
PORTA input/output control register
Bit3 must be set to “1” by the User’s program and
always be kept up.
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 R/W PORTB input/output control register
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 R/W PORTC input/output control register
$1B 1 1 1 1 R/W All bits of this register must be set to “1” by the
User’s program and always be kept up.
$1C PECR.3 PECR.2 PECR.1 PECR.0 R/W PORTE input/output control register
PA (/B/C/E) CR, n (n = 0, 1, 2, 3)
0: Set I/O as an input direction. (Power on initial)
1: Set I/O as an output direction.
Equivalent Circuit for a Single I/O Pin
I/O Pad
PULLEN PH/PL Weak
Pull high
READ DATA IN
READ
V DD
V DD
Weak
Pull Low
GND
GND
DATA
Regiser
I/O Control
Register
DATA
Figure 3

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System Register $0D
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks
$0D PULLEN PH/PL OXS OXON R/W
Bit0: Turn on OSCX oscillator control register
Bit1: System clock control register
Bit2: Port pull-high and falling edge interrupt or pull-low
and rising edge interrupt control register
Bit3: Port pull-high/low enable control register
1 X X X R/W Port Pull-high/Pull-low enable
0 X X X R/W Port Pull-high/Pull-low disable (Power on initial)
1 1 X X R/W Port Pull-high resister ON, set falling edge interrupt
(Power on initial)
1 0 X X R/W Port Pull-low resister ON, set rising edge interrupt
I/O Note:
- In user’ program, it is necessary to always keep the Bit3 of system register $08 as 0, also all the bits of system
register $0B.
- In user’ program, it is necessary to always keep the Bit3 of system register $18 as 1, also all the bits of system
register $1B.
After the chip Power on, LVR, Pin or WDT Reset, User’s program must be set as the follow step:
LDI 18H, 1xxxB ; x = 0 or 1
LDI 1BH, 1111B
LDI 08H, 0xxxB
LDI 0BH, 0000B

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7. PORTB Interrupt
The PORTB is used as port interrupt sources. Since PORTB I/O is bit programmable I/O, so only the digital input port can
generate a port interrupt. The analog input can’t generate an interrupt request (when PORTB0, PORTB1 used as AN4, AN5).
The PORTB interrupt control flags are mapped on $14, $15 of the system register. They can be accessed or tested by the
program. Those flags are cleared to 0 at initialization by the chip reset.
System Register $14
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$14 PIEN.3 PIEN.2 PIEN.1 PIEN.0 R/W Bit3-0: PORTB interrupt enable flags register
PIEN.n, (n = 0, 1, 2, 3)
0: Disable port interrupt. (Power on initial)
1: Enable port interrupt.
System Register $15
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$15 PIF.3 PIF.2 PIF.1 PIF.0 R/W Bit3-0: PORTB interrupt request flags register
PIF.n, (n = 0, 1, 2, 3)
0: Port interrupt is not presented. (Power on initial)
1: Port interrupt is presented.
Only writing these bits to 0 is available.
Following is the port interrupt function block-diagram for reference.
PORTB.n
Rising/Falling
Edge Detector
PH/PL
PBCR.n
PIF.n
PIEN.n
Port Interrupt
IEP
IRQP
Note: n = 0, 1, 2, 3
Figure 4. Port Interrupt Block Diagram
Port Interrupt Programming Notes:
When PH/PL (Bit2 of $0D) is set to 1, any one of PORTB input pin transitions from VDD to GND would set PIF.x to 1, in spite of
level of the other pin of PORTB.
If PIEN.x = 1and IEPB = 1, the x of PORTB input pin transitions from VDD to GND would generate an interrupt request (IRQPB
= 1) and interrupt the CPU, in spite of any level of the other pin of PORTB.
When PH/PL (Bit2 of $0D) is cleared to 0, any one of PORTB input pin transitions from GND to VDD would set PIF.x to “1”, in
spite of level of the other pin of PORTB.
If PIEN.x = 1and IEPB = 1, the x of PortB input pin transitions from GND to VDD would generate an interrupt request (IRQPB =
1) and interrupt the CPU, in spite of any level of the other pin of PORTB.

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8. Timer
SH69P561/69K561 has two 8-bit timers. The timer/counter
has the following features:
- 8-bit up-counting timer/counter.
- Automatic re-loads counter.
- 8-level prescaler.
- Interrupt on overflow from $FF to $00.
The following is a simplified timer block diagram.
fOSC/4
tosc SYNC
8-BIT
COUNTER
T0E0
T0S0
T0
Prescaler
MUX
T0M.2 T0M.0T0M.1
EOR
The timers provide the following functions:
- Programmable interval timer function.
- Read counter value.
8.1. Timer0 and Timer1 Configuration and Operation
Both the Timer0 and Timer1 consist of an 8-bit write-only
timer load register (TL0L, TL0H; TL1L, TL1H) and an 8-bit
read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each
of them has both low-order digits and high-order digits.
Writing data into the timer load register (TL0L, TL0H; TL1L,
TL1H) can initialize the timer counter.
The low-order digit should be written first, and then the
high-order digit. The timer/counter is automatically loaded
with the contents of the load register when the high-order
digit is written or counter counts overflow from $FF to $00.
Timer Load Register: The register H controls the physical
READ and WRITE operations.
Please follow these steps:
Write Operation:
Low nibble first
High nibble to update the counter
Read Operation:
High nibble first
Low nibble followed.
Load Reg. H
8-bit timer counter
Load Reg. L
Latch Reg. L
8.2. Timer0 Mode Register
The Timer0 can be programmed in several different prescalers by setting Timer0 Mode register (T0M).
The clock source pre-scale by the 8-level counter first, then generate the output plus to timer counter. The Timer0 Mode
registers (T0M) are 3-bit registers used for the timer control as shown below.
System Register $13: Timer0/Timer1 Clock Source and Edge Configuration Register
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$13 T0S1 T0E1 T0S0 T0E0 R/W
Bit0: T0 clock edge in Timer0 control register
Bit1: Timer0 clock source control register
Bit2: T0 clock edge in Timer1 control register
Bit3: Timer1 clock source control register
X X 0 X R/W fOSC/4 is selected as Timer0 clock source
(Power on initial)
X X 1 X R/W T0 is selected as Timer0 clock source
X X 1 0 R/W Increment on low-to-high transition when T0S0 = 1
(Power on initial)
X X 1 1 R/W Increment on high-to-low transition when T0S0 = 1

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System Register $02: Timer0 Mode Register, when T0S0 = 1
T0M.2 T0M.1 T0M.0 Prescaler Clock Source
X X X /1 T0
System Register $02: Timer0 Mode Register, when T0S0 = 0
T0M.2 T0M.1 T0M.0 Prescaler Clock Source
0 0 0 /211 fOSC/4
0 0 1 /29fOSC/4
0 1 0 /27fOSC/4
0 1 1 /25fOSC/4
1 0 0 /23fOSC/4
1 0 1 /22fOSC/4
1 1 0 /21fOSC/4
1 1 1 /20fOSC/4
External Clock/Event T0 as Timer0 Source
When external clock/event T0 input as Timer0 source, PORTC.3 is shared as T0 input and it is synchronized with OSC clock.
The external source must follow certain constraints. The OSC clock samples T0 input. Therefore it is necessary to be high (at
least 2 tOSC) and low (at least 2 tOSC). The requirement is as follows:
T0H (T0 high time) ≥2 tOSC + ∆T
T0L (T0 low time) ≥2 tOSC + ∆T; ∆T = 20ns
8.3. Timer1 Mode Register
The following is a simplified Timer1 block diagram.
PRESCALER
tOSC SYNC
8-bit
COUNTER
T1M.2 T1M.0
T1M.1
EOR
T0
MUX
System
clock
T0S1T0E1
Timer1
When OSC is selected as system clock,
System clock = fOSC/4;
When OSCX is selected as system clock,
System clock = fOSCX/4.
System Register $13: Timer0/Timer1 Clock Source and Edge Configuration Register
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$13 T0S1 T0E1 T0S0 T0E0 R/W
Bit0: T0 clock edge in Timer0 control register
Bit1: Timer0 clock source control register
Bit2: T0 clock edge in Timer1 control register
Bit3: Timer1 clock source control register
0 X X X R/W System clock is selected as Timer1 clock source
(Power on initial)
1 X X X R/W T0 is selected as Timer1 clock source
1 0 X X R/W Increment on low-to-high transition when T0S1 = 1
(Power on initial)
1 1 X X R/W Increment on high-to-low transition when T0S1 = 1

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System Register $03: Timer1 Mode Register
T1M.2 T1M.1 T1M.0 Prescaler Clock Source
0 0 0 /211 System clock /T0
0 0 1 /29System clock /T0
0 1 0 /27System clock /T0
0 1 1 /25System clock /T0
1 0 0 /23System clock /T0
1 0 1 /22System clock /T0
1 1 0 /21System clock /T0
1 1 1 /20System clock /T0
External Clock/Event T0 as Timer1 Source
When external clock/event T0 input as Timer1 source, PORTC.3 is shared as T0 input and it is synchronized with the CPU
system clock. The external source must follow certain constraints. The system clock samples it in instruction frame cycle.
Therefore it is necessary to be high (at least 2 tSYSCLK) and low (at least 2 tSYSCLK). When the prescaler ratio selects /20, it is the
same as the system clock input.
The requirement is as follows:
T0H (T0 high time) ≥2 X tSYSCLK + ∆T
T0L (T0 low time) ≥2 X tSYSCLK + ∆T ; ∆T= 20ns
When another prescaler ratio is selected, the Timer1 is scaled by the asynchronous ripple counter and so the prescaler output
is symmetrical. Then:
2
T0
timelowT0timehighT0 == ≥N
TtX2 ∆+
SYSCLK
Where: T0 = Timer0 input period
N = prescaler value
The requirement is:
TtX2
2
T0XN ∆+≥ SYSCLK
So, the limitation is applied for the T0 period time only. The pulse width is not limited by this equation. It is summarized as follows:
N
TX2tX4
periodT0 ∆
+
≥SYSCLK ; ∆T = 20ns
Notes:
When OSC is selected as system clock, tSYSCLK = 4 X tOSC;
When OSCX is selected as system clock, tSYSCLK = 4 X tOSCX.

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9. Watchdog Timer (WDT)
The watchdog timer is a count-down counter, and its clock source is an independent built-in RC oscillator, so that it will always
run even in the STOP mode. The watchdog timer automatically generates a device reset when it overflows. It can be enabled or
disabled permanently by using the code option.
The watchdog timer control bits ($1E Bit2 - 0) are used to select different overflow frequency. The watchdog timer overflow flag
($1E Bit3) will be automatically set to “1” by hardware when the watchdog timer overflows. By reading or writing the system
register $1E, the watchdog timer should re-count before the overflow happens.
System Register $1E: Watchdog Timer (WDT)
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks
$1E
WDT
WDT.2 WDT.1 WDT.0 R/W
R
Bit2-0: Watchdog timer control register
Bit3: Watchdog timer overflow flag
X 0 0 0 R/W Watchdog timer overflow period is 4096ms. (Power on initial)
X 0 0 1 R/W Watchdog timer overflow period is 1024ms.
X 0 1 0 R/W Watchdog timer overflow period is 256ms.
X 0 1 1 R/W Watchdog timer overflow period is 128ms.
X 1 0 0 R/W Watchdog timer overflow period is 64ms.
X 1 0 1 R/W Watchdog timer overflow period is 16ms.
X 1 1 0 R/W Watchdog timer overflow period is 4ms.
X 1 1 1 R/W Watchdog timer overflow period is 1ms.
0 X X X R No watchdog timer overflow resets. (Power on initial)
1 X X X R
Watchdog timer overflow, WDT reset happens
(Cleared after Power on Reset, Pin Reset or Low Voltage Reset)
Note: Watchdog timer overflow period is valid for VDD = 5V.
10. Warm-up Timer
The device has a built-in warm-up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the
following conditions:
A. Power-on Reset and Pin Reset:
(1) In RC oscillator mode, the warm-up counter prescaler divide ratio is 1/27(128).
(2) In Crystal oscillator or Ceramic resonator mode, the warm-up counter prescaler divide ratio is 1/212 (4096).
B. Wake up from stop mode, WDT Reset, LVR Reset:
(1) In RC oscillator mode, the warm-up counter prescaler divide ratio is 1/27(128).
(2) In Crystal oscillator or Ceramic resonator mode, the warm-up counter prescaler divide ratio is 1/212 (4096).
11. HALT and STOP Mode
After the execution of HALT instruction, SH69P561/69K561 will enter the HALT mode. In the HALT mode, CPU will stop
operating. But peripheral circuit (Timer0, Timer1, ADC) will keep status.
After the execution of STOP instruction, SH69P561/69K561 will enter the STOP mode. The whole chip (including oscillator) will
stop operating. But watchdog is still enabled.
In the HALT mode, SH69P561/69K561 can be waked up if any interrupt occurs.
In the STOP mode, SH69P561/69K561 can be waked up if port interrupt occurs.
When CPU is waked from the HALT/STOP by any interrupt source, it will execute the relevant interrupt serve subroutine at first.
Then the instruction next to HALT/STOP is executed.