Sony WX-C55 User manual

1
Other Specifications
CD player section
Signal-to-noise ratio 94 dB
Frequency response 5 – 20,000 Hz
Wow and flutter Below measurable limit
Laser Diode Properties
Material GaAlAs
Wavelength 780 nm
Emission Duration Continuous
Laser output power Less than 44.6 µW*
*This output is the value measured at a distance
of 200 mm from the objective lens surface on
the Optical Pick-up Block.
Cassette player section
Tape track 4-track 2-channel stereo
Wow and flutter 0.08 % (WRMS)
Frequency response 30 – 20,000 Hz
Signal-to-noise ratio
Cassette type Dolby B NR Dolby NR off
TYPE II, IV 67 dB 58 dB
TYPE I 64 dB 55 dB
Model Name Using Similar Mechanism NEW
CD Drive Mechanism Type MG-378X-121
Optical Pick-up Name KSS-521A
Model Name Using Similar Mechanism XR-C8820
Tape Transport Mechanism Type MG-25E-136
SERVICE MANUAL
US Model
E Model
WX-C55
CHANGER CONTROL AUDIO MASTER
MICROFILM
SPECIFICATIONS
– Continued on next page –
CD
Section
TC
Section
DolbynoisereductionmanufacturedunderlicensefromDolbyLabo-
ratories Licensing Corporation.
“DOLBY” and the double-D symbol aare trademarks of Dolby
Laboratories Licensing Corporation.
AUDIO POWER SPECIFICATIONS (US Model)
POWER OUTPUTAND TOTAL HARMONIC DISTORTION
13 watts per channel minimum continuous average power into
4 ohms, 4 channels driven from 20 Hz to 20 kHz with no more
than 1% total harmonic distortion.
Tuner section
FM
Tuning range US model:
87.5 – 107.9 MHz
E model:
FM tuning interval:
50 kHz/200 kHz switchable
87.5 – 108.0 MHz
(at 50 kHz step)
87.5 – 107.9 MHz
(at 200 kHz step)
Antenna terminal External antenna connector
Intermediate frequency 10.7 MHz
Usable sensitivity 9 dBf
Selectivity 75 dB at 400 kHz
Signal-to-noise ratio 65 dB (stereo),
68 dB (mono)
Harmonic distortion at 1 kHz
0.7% (stereo),
0.4% (mono)
Separation 35 dB at 1 kHz
Frequency response 30 – 15,000 Hz

25
SECTION 6
DIAGRAMS
• IC500 µPD78058GC-B51-8BT (SYSTEM CONTROL)
Pin No. Pin Name I/O Pin Description
1 VSM I FM, AM common signal meter A/D conversion input
2 NIL I Not used. (Connect to ground in this set.)
3 SD-IN I Station detecter input (“H” : with SD)
4 AVSS — Analog ground
5 FM-ST I FM stereo input pin (“L” : stereo)
6 AM-ST I AM stereo input pin (“L” : stereo)
7 AVREF — Reference power supply for D/A conversion.
8 PLL-SI I PLL serial data input
9 PLL-SO O PLL serial data output
10 PLL-CKO O PLL serial clock output
11 PLL-CE O PLL serial chip enable output
12 AMS I Music with/without detection input at AMS. (“L” : with music, “H” : without music)
13 PLAY/AMS O Tape AMS control output
14 F/R O FWD/REV detection output (“H” : FWD, “L” : REV)
15 MTL O Metal control output (“H” : metal)
16 BUS-SI I Uni-link serial interface data input
17 BUS-SO O Uni-link serial interface data output
18 BUS-CKI I Uni-link serial interface clock input
19 BUS-CKO O Uni-link serial interface clock output
20 TAPE-MUTE O Tape mute control output
21 DOLON I/O Dolby control input/output
22 EQ-CE O Equalizer serial chip enable output (Not used in this set.)
23 EQ-CLK O Equalizer serial clock output (Not used in this set.)
24 DATA O Serial data output
25 VOL-CLK O Electronic volume serial clock output
26 VOL-CE O Electronic volume serial chip enable output
27 MUT O System mute control output
28 AMP-ON O Power amplifier power supply control output
29 AUX-MUT O AUX mute control output
30 C/B I/O Dolby B/C select control output (Not used in this set.)
31 PWR-SEL I Power select initial setting input
32 TEST I Test mode setting input
33 VSS — Ground
34 NIL I Not used. (Connect to ground in this set.)
35 POWER-ON O System power supply control output
36 TUN-ON O Tuner power supply control output
37 FM-ON O FM power supply control output
38 AM-ON O AM power supply control output (Not used in this set.)
39 NIL I Not used. (Connect to ground in this set.)
40 CM-ON O Capstan motor control output
41 TP-ON O Tape power supply control output
42 LM-EJ O Loading motor control output (Eject direction)
43 LM-LOD O Loading motor control output (Loading direction)
44, 45 POS1, 0 I Position signal detection input 1, 0
46 BEEP O Buzzer control output
47, 48 POS2, 3 I Position signal detection input 2, 3
49 REL I Reel stand rotation detection input
50 RC-IN1 I Rotary commanderA/D conversion input 1
51 SUB-CE O Sub serial chip enable output (Not used in this set.)
52 SUB-DATA O Sub serial data output (Not used in this set.)
53 SUB-CLK O Sub serial clock output (Not used in this set.)
6-1. IC PIN DESCRIPTIONS

26
Pin No. Pin Name I/O Pin Description
54 SYS-RST O System reset signal output
55 BUS-ON O Bus ON control output
56, 57 RE1, 0 I Rotary encoder input 1, 0
58 AD-ON O Power supply output for A/D conversion.
59 RAMBU I RAM reset detection input
60 RESET — Reset input
61 SIRCS I Remote control input (Not used in this set.)
62 BU-IN I Backup power detection input
63 NIL — Not used (Connect to ground in this set.)
64 ACC-IN I Accessory power supply detection input
65 DIMMER I Dimmer control input
66 TEL-MUTE I Telephone mute control input
67 KEY-ACK I Key input acknowledge
68 VDD — µ-con power supply
69 X2 O Main ceramic oscillator output (5 MHz)
70 X1 I Main ceramic oscillator input (5 MHz)
71 IC — Connect to ground in this set.
72 XT2 O Sub crystal oscillator output (32.768 kHz)
73 XT1 I Sub crystal oscillator input (32.768 kHz)
74 AVDD — Power supply for A/D conversion.
75 AVREF — Reference power supply for A/D conversion.
76, 77 KEY-IN0, 1 I Key input 0, 1
78 KEY-IN2 I Key input 2 (Not used in this set.)
79 RC-IN0 I Rotary commanderA/D conversion input 0
80 DSTSEL I Initial setting input of destination. (“H” : US model, “L” : E model)

27
• IC801 µPD78054GC-A32-8BT (CD SYSTEM CONTROL)
Pin No. Pin Name I/O Pin Description
1 LEDCLK — Not used in this set.
2 LEDCKO — Not used in this set.
3 LEDSO — Not used in this set.
4 AVSS — Analog ground
5 FL-CE0 O Display driver chip select output 0
6 FL-CE1 O Display driver chip select output 1 (Not used in this set.)
7 AVREF1 — Reference power supply for D/A conversion.
8 FL-RST O Display driver reset output (Not used in this set.)
9 FL-SO O Display driver data output
10 FL-CKO O Display driver clock output
11 SRDT — Not used in this set.
12 NCO — Not used.
13 SCLK — Not used in this set.
14 FL-BLK O Display driver blank control output
15 NIL — Not used. (Connect to ground in this set.)
16 UNISI I Uni-link serial interface data input
17 UNISO O Uni-link serial interface data output
18 UNICKI I Uni-link serial interface clock input
19 LINKOFF O Link off output
20 ILLON O Illumination power supply control output
21 CMDON O CD mechanism power supply control output
22 CD-ON O CD power supply control output
23 SP-SEL O Signal (L/R channel) select control signal output to spectrum analyzer control IC.
24 SP-C O Frequency select control signal output to spectrum analyzer control IC.
25 SP-B O Frequency select control signal output to spectrum analyzer control IC.
26 SP-A O Frequency select control signal output to spectrum analyzer control IC.
27 CDMUT O CD mute control output
28 EMPH-O O Emphasis control output
29 CD-RST O CD signal process IC reset output
30 XMODE — Not used in this set.
31, 32 NIL — Not used. (Connect to ground in this set.)
33 VSS — Ground
34 TBTGSEL I CD tracking balance, tracking gain auto adjustment select input.
35 – 39 NIL — Not used. (Connect to ground in this set.)
40 GFS I GFS signal detection input
41 SQ-SI I SUB Q data input
42 SQ-CKO O SUB Q clock output
43 NIL — Not used. (Connect to ground in this set.)
44 CD-SO O CD signal process serial data output
45 CD-LAT O CD signal process latch output
46 CD-CKO O CD signal process serial clock output
47 PH2 I 8/12 cm disc detection input
48 F-OK I Focus signal detection input
49 LD-ON O Laser on/off select control output
50 D-SW I Down switch detection input
51 PH1 I Disc insert detection input
52 L-SW I Sled limit switch input
53 LM-LOD O Loading motor control output (Loading direction)
54 LM-EJ O Loading motor control output (Eject direction)
55 PH3 I Disc detect sensor input
56 CTL1 O Driver IC control output
57 NCO — Not used.

28
Pin No. Pin Name I/O Pin Description
58 EESIO O Not used in this set.
59 EECKO O Not used in this set.
60 RESET — Reset input
61 SCOR I SCOR signal detection input
62 CNIN I Track jump count input
63 SELF-SW I Disc self store detection input
64 SENS I SENS signal detection input
65 DQSY — Not used in this set.
66 BUIN I Backup power supply detection input
67 BUSON I Bus on control input
68 VDD — µ-con power supply
69 X2 O Main ceramic oscillator output (5 MHz)
70 X1 I Main ceramic oscillator input (5 MHz)
71 IC — Not used. (Not used in this set.)
72 XT2 O Sub crystal oscillator output (Not used in this set.)
73 XT1 I Sub crystal oscillator input (Connect to ground in this set.)
74 AVDD — Power supply for A/D conversion.
75 AVREF — Reference power supply for A/D conversion.
76 NIL — Not used. (Connect to ground in this set.)
77 SP-IN I Spectrum analyzer control signal input from spectrum analyzer control IC.
78 TSTIN0 I LOAD/EJECT prohibition setting input
79 NCO — Not used.
80 LEDOE — Not used in this set.

34 34
WX-C55
6-7. SCHEMATIC DIAGRAM — CD MECHANISM SECTION (1/2) — • Refer to page 35 for Waveforms and page 48 for IC Block Diagrams.
Note:
• Voltage and waveforms are dc with respect to ground
under no-signal conditions.
no mark : CD PLAY
∗: Impossible to measure
(Page 35)

35 35
WX-C55
6-8. SCHEMATIC DIAGRAM — CD MECHANISM SECTION (2/2) — • Refer to page 48 for IC Block Diagrams.
Note:
• Voltage and waveforms are dc with respect to ground
under no-signal conditions.
no mark : CD PLAY
(Page 34)
(Page 37)
• Waveforms
(MODE : CD PLAY)
1
2
3
4
5
6
7
IC1 3(MDP)
2.6Vp-p
7.6µsec
IC1 @º (LRCK)
5.8Vp-p
22.7µsec
IC1 @™ (BCK)
5.7Vp-p
474nsec
16.89MHz
IC1 #¢ (XTAI)
3.2Vp-p
Approx. 200mVp-p
IC2 $™ (TEO)
0V
Approx. 620mVp-p
IC2 1(FEO)
0V
IC2 #¡ (RFO)
1.2Vp-p

37 37
WX-C55
6-12. SCHEMATIC DIAGRAM — CD SECTION — • Refer to page 51 for IC Block Diagrams.
Note:
• Voltage is dc with respect to ground under no-signal
condition.
no mark : CD PLAY
(Page 41)
(Page 46)
(Page 41)
(Page 35)
(Page 36)
(Page 36)

40 40
WX-C55
6-14. SCHEMATIC DIAGRAM — MAIN SECTION (1/4) — • Refer to page 50 for IC Block Diagrams.
Note:
• Voltage is dc with respect to ground under no-signal
condition.
no mark : FM
():AM
(Page 41)
(Page 42)

41 41
WX-C55
6-15. SCHEMATIC DIAGRAM — MAIN SECTION (2/4) —
Note:
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
(Page 43)
(Page 42)
(Page 40)
(Page 37)
(Page 37)

42 42
WX-C55
6-16. SCHEMATIC DIAGRAM — MAIN SECTION (3/4) — • Refer to page 50 for IC Block Diagrams.
(Page 43)
(Page 40) (Page 41)
Note:
• Voltage is dc with respect to ground under no-signal
condition.
no mark : FM
( ) : TAPE PLAY

43 43
WX-C55
6-17. SCHEMATIC DIAGRAM — MAIN SECTION (4/4) — • Refer to page 50 for IC Block Diagrams.
(Page 42)
(Page 41)
(Page 47)
(Page 46)
Note:
• Voltage is dc with respect to ground under no-signal
condition.
no mark : FM
():AM

46 46
6-19. SCHEMATIC DIAGRAM — CONTROL SECTION —
(Page 37)
(Page 43)
WX-C55
Note:
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM

47
6-21. SCHEMATIC DIAGRAM — JOG SECTION —
(Page 43)
6-20. PRINTED WIRING BOARD — JOG SECTION —
(Page 39)
WX-C55

48
• IC Block Diagrams
IC1 CXD2507AQ (SERVO BOARD)
IC3 BA6796FP-T1
XLON
SPOD
SPOC
SPOB SPOA
CLKO
VDD
CNIN
SEIN
CLOK
XLAT
XLTO
DATO
52
53
5455
5657
58596061
62
63
64
51
SERVO AUTO
SEQUENCER
33
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
50
44
DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
VSS
WFCK
EMPH
DOUT
C4M
FSTT
XTSL
XTAO
XTAI
MNTO
20 21 22 23 24 25 26 27 29 30 31 3228
LRCK
PCMD
BCLK
GTOP
XUGF
XPCK
VDD
GFS
RFCK
C2PO
XROF
MNT3
MNT1
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
13
14
15
FOK
MON
MDP
MDS
LOCK
TEST
FILO
FILI
PCO
VSS
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
5
14 CPU
INTERFACE SUB CODE
PROCESSOR DIGITAL
CLV
EFM
DEMODULATOR
DIGITAL
PLL
ASYMMETRY
CORRECTOR
5D/A
INTERFACE
ERROR
CORRECTOR
3
6
3
16K
RAM
DIGITAL
OUT
CLOCK
GENERATOR
4
123 4 5678
910 11 12 13 14
OPOUT
CH4-IN
CH4
CTL1
CTL2
FWD
REV
TRAY
GND
CH3 –
CH5 –
COM
CH4 +
CH3 +
CH3-IN
CH3
VREF
CH2
CH2-IN
VCC
VCC
CH1 –
CH2 –
CH1-IN
OP IN –
CH1
CH1 +
OP IN +
CH2 +
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER DRIVE BUFFER DRIVE
BUFFER DRIVE
BUFFER
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT
DOWN
15
161718
1920
21
22
23
2425
26
27
28
LOGIC
CTL1 CTL2 FWD REV
V/I

49
IC2 CXA1782BQ
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987
6
5
43
2
1
37
38
39
40
41
42
43
44
45
46
47
48
PHD 2 PHD 1
PHD
LD
RF O
RF I
CP CB CC1 CC2 FOK
SENS
C.OUT
XRST
DATA
XLT
CLK
VCC
ISET
SL O
SL M
SL P
TA O
TA M
FSET
TG2
TGU
SRCH
FE O
FLB
FGD
FDFCT
FE M
FEI
FEO
FE BIAS
F
E
EI
VEE
TED
LPFI
TEI
ATSC
TZC
TDFCT
VC
APC LEVEL S
FOK
MIRR
RF IV AMP1
RF IV AMP2
FE AMP
TTL
IIL
FZC COMP
DFCT
IIL
TTL
IIL DATA REGISTER INPUT SHIFT REGISTER
ADDRESS DECODER
OUTPUT DECODER
TTL
IIL
TOG1-3
BAL1-3 FS1-4 TG1-2 TM1-7 PS1-4
F IV AMP
E IV AMP
BAL1
BAL2
BAL 3
TE AMP
TZC COMP
DFCT
TM1
DFCT
FS4
ATSC
WINDOW COMP
TOG1 TOG2
TOG3
FCS PHASE
COMPENSATION
FS1
F SET
TG2
TM7
TM3
TM4
TM5
TM6
ISET
TRACKING
PHASE
COMPENSATION
HPF COMP LPF COMP
TG1
FS2
TM2
RF M

50
1
2
3
4
5
6
7 8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
DATA
GND
VCC
RST
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
IC1 BU2624FV (MAIN BOARD)
IC300 CXA2510AQ
IC331, 341 NJM4558M
IC620 BA8270F
PHASE
DET
PRESCALER
MAIN
COUNT
IF COUNT
CTL
20BIT COUNT
SHIFT REGISTER LATCH
REFERENCE
DIVIDER
I/O
CTL
1
2
4
5
6
7
9
10
20
18
17
16
15
14
13
12
11
19
XIN
CE
CK
DA
CD
P0
P1
P3
XOUT
VSS
PD
VDD
FMIN
AMIN
P2
IFIN
SD
P4
+– 6
7
5
8
B
+–
2
1
3
4
A
A OUT
A IN–
A IN+
VEE
VCC
B OUT
B IN–
B IN+
+
–
+
–+–
+
–
+–
12345 6 7 8 9 10
20
19
18
17
16
15
14
13
12
11
2122232627282930
31
32
33
34
37
38
39
40
2425
PBFB2
PBRIN2
PBREF2
PBFIN2
35
36
PBGND
VCT
PBFIN1
PBREF1
PBRIN1
PBFB1
PBEQ2
PBOUT2
VCC
TAPEIN2
AUXIN2
MSLPF
LINEOUT2
TCH2
NC
PLAY
FF
MSTC
DGND
MSOUT
NC
NRSW
INSW
TAPESW
MSMODE
DRSW
MSSW NC TCH1 LINEOUT1 DIREF AUXIN1 TAPEIN1 PBEQ1 PBOUT1 GND
F2
120µ/
70µ
X1
X1
VCT
+
F1
120µ/
70µNR
OFF/B
F3
LPF
VCC
DETECT
MS ON/
OFF
NR
MODE
FWD/RVS
TAPE EQ
TAPE/AUX
NR BIAS
NR
MS
MODE
OFF/B
T2
T1

51
IC401 PCM1717E-ST2
IC350 LC75374E
IC502 RN5VD23AA-TL
IC600 LB1930M
+
–
+
–
+
–
+
–+
–
+
–
+
–
+
–
+
–
+
–
+
–+
–
+
–
+
–
DECODER LATCH SHIFT
REGISTER
CONTROL
–
+
+
–
12 3 45 6 7 8 9 10
20
19
18
17
16
15
14
13
12
11
21
22
2324252627282930313233
34
35
36
37
38
39
40
41
42
43
44
LSELO
L4
L3
L2
L1
VDD
R1
R2
R3
R4
RSELO
RVRIN
RCOM
RT1 RT2 RT3
RTOUT
RSIN
NC NC
RSB1 RSB2
RFIN
RFOUT
RROUT
VSS
CL
DI
CE
VREF
LROUT
LFOUT
LFIN
LSB2
LSB1 NC NC LSIN LTOUT LT3 LT2 LT1 LCOM LVRIN
3
4
5
6
7
18
19
20
17
16
15
14
8
9
10
13
12
11
2
1CLK
CONTROL
INPUT
INTERFACE
DIGITAL
FILTER
5LEVE DAC
LOWPASS FILTER
CMOS
AMP
5LEVEL DAC
LOWPASS FILTER
CMOS
AMP
MODE
CONT
ROL
XTI
DGND
VDD
LRCIN
DIN
BCKIN
ZERO
D/C R
VOUTR
AGND VCC
VOUTL
D/C L
MODE
RSTB
MD/DM0
MC/DM1
ML/MUTE
CLKO
XTO
NOISE SHAPER
12 3
4
5
+
–
VREF
CD NC
OUT
VDD
GND
1
2
3
4
56
7
8
9
10
VCC
IN2
S-GND
IN1
NC NC
OUT2
NC
P-GND
OUT1
CONTROL
CIRCUIT
MOTOR
DRIVE
CIRCUIT
BUFFER
BUFFER

52
IC802 BA3834F
IC680 BA3918-V2
REGISTER
PEAK
HOLD
68Hz
B.P.F.
REGISTER
PEAK
HOLD
170Hz
B.P.F.
REGISTER
PEAK
HOLD
420Hz
B.P.F.
REGISTER
PEAK
HOLD
1kHz
B.P.F.
REGISTER
PEAK
HOLD
2.4kHz
B.P.F.
REGISTER
PEAK
HOLD
5.9kHz
B.P.F.
REGISTER
PEAK
HOLD
14.4kHz
B.P.F.
DIFFERENTIAL
AMPLIFIER
MULTIPLEXER
123456789
BIASC
VREFC
RREF
NC
D
IFOUT
NC
CIN
AIN
VCC
DECODER
1011
12
13
14
15
1617
18
A
B
C NC
SEL NC
TEST
AOUT
GND
+
–
+
–
+
–
+
–
OVER VOLTAGE
PROTECT
REGULATOR
12 3 45 6 7 8 9 10 1211
NC
MODE2 MODE1
STB
VDD
AMP
VCC ANT
COM
AM
FM
GND