ST STM32U575 Series Installation and operating instructions

Introduction
This application note is intended for system designers who require a hardware implementation overview of the development
board features, such as power supply, clock management, reset control, boot mode settings and debug management.
This document details how to use the STM32U575xx and STM32U585xx microcontrollers (also named STM32U575/585) and
describes the minimum hardware resources required to develop an application using these MCUs.
Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces
and modes.
Getting started with STM32U575/585 MCU hardware development
AN5373
Application note
AN5373 - Rev 1 - June 2021
For further information contact your local STMicroelectronics sales office.
www.st.com

1General information
This document applies to the STM32U575/585 Arm®-based microcontrollers.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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2Power supply management
2.1 Power supplies
The STM32U575/585 devices require a 1.71 to 3.6 V operating voltage supply (VDD).
The independent supplies listed below, can be provided for specific peripherals:
•VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset,
power management and internal clocks. VDD is provided externally through the VDD pins.
•VDDA = 1.58 V (COMPs) / 1.6 V (DACs/OPAMPs) / 1.62 V (ADCs) / 1.8 V (VREFBUF) to 3.6 V
VDDA is the external-analog power supply for A/D converters, D/A converters, voltage reference buffer,
operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage. The
VDDA pin must preferably be connected to VDD voltage supply when these peripherals are not used.
Note: In case the VDDA pin is left at high impedance or is tied to VSS, the maximum input voltage that can be applied
on the I/Os with "_a" I/O structure, is reduced (refer to device datasheet for more details).
•VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step-down converter. It is provided externally through
the VDDSMPS pin, and must be connected to the same supply as VDD pin.
•VLXSMPS
The VLXSMPS pin is the switched SMPS step-down converter output.
•VDD11
VDD11 is a digital core supply provided through the internal SMPS step-down converter VLXSMPS pin. Two
VDD11 pins are present only on packages with internal SMPS, connected to a total of 4.7 µF (typical)
external capacitors.
•VCAP
VCAP is the digital core supply, from the internal LDO regulator. VCAP pins (one or two) are present only on
packages with LDO only (no SMPS), connected to a total of 4.7 µF (typical) external capacitor.
Note: – In case there is two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF capacitor,
for a total around 4.4 µF (maximum 4.7 µF).
– The SMPS power supply pins (VLXSMPS, VDD11, VDDSMPS, VSSSMPS) are available only on packages
with SMPS. In such packages, the STM32U575/585 devices embed two regulators, one LDO and one
SMPS in parallel, to provide the VCORE supply to digital peripherals. A 4.7 μF total external capacitor and a
2.2 µH coil are required on VDD11 pins.
– The Flash memory is supplied by VCORE and VDD.
•VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external-independent power supply for USB transceivers. The VDDUSB voltage level is
independent from the VDD voltage. The VDDUSB pin must preferably be connected to VDD voltage supply
when the USB is not used.
Note: In case the VDDUSB pin is left at high impedance or is tied to VSS, the maximum input voltage that can be
applied on the I/Os with "_u" I/O structure, is reduced (refer to device datasheet for more details).
•VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level is independent from
the VDD voltage, and must preferably be connected to VDD when PG[15:2] are not used.
Note: On small packages, VDDA, VDDIO2 or VDDUSB independent power supplies may not be present as a dedicated
pin, and are internally bonded to a VDD pin. They are neither not present when the related features are not
supported on the product.
•VBAT = 1.65 V to 3.6 V (functionality guaranteed down to VBOR_VBAT minimum value, refer to the product
datasheet)
VBAT is the power supply when VDD is not present (through power switch) for RTC, TAMP, external clock
32 kHz oscillator, backup registers and optionally backup SRAM.
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•VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage
reference buffer (VREFBUF) when enabled. The VREF+ pin can be grounded when ADC and DAC are not
active.
The internal voltage reference buffer supports four output voltages, that are configured with the VRS[2:0]
field in VREFBUF_CSR register:
– VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
– VREF+ around 1.8 V. This requires VDDA ≥ 2.1 V.
– VREF+ around 2.048 V. This requires VDDA ≥ 2.4 V.
– VREF+ around 2.5 V. This requires VDDA ≥ 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA
and VDDA pins, respectively.
When the VREF+ pin is double-bonded to VDDA in a package, the internal VREFBUF is not available and
must be kept disabled.
VREF- must always be equal to VSSA.
The following figures present an overview of the STM32U575/585 devices power supply, depending on the SMPS
presence.
Figure 1. STM32U575xx and STM32U585xx power supply overview (no SMPS)
USB transceiver
Core
SRAM1
SRAM2
SRAM3
SRAM4
Digital
peripherals
LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
VDDA domain
Backup domain
Standby circuitry
(Wakeup logic, IWDG)
Low-voltage detector
I/O ring VCORE domain
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
VCAP
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
LDO regulator
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Figure 2. STM32U575xQ and STM32U585xQ power supply overview (with SMPS)
USB transceiver
Core
SRAM1
SRAM2
SRAM3
SRAM4
Digital
peripherals
LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
VDDA domain
Backup domain
Standby circuitry
(Wakeup logic, IWDG)
LDO regulator
Low-voltage detector
I/O ring
VCORE domain
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
2x VDD11
SMPS regulator
Voltage regulator
VLXSMPS
VDDSMPS
VSSSMPS
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
In devices without SMPS, the I/Os and system analog peripherals (such as PLLs and reset block) are fed by VDD
supply source. The VCORE power supply for digital peripherals and memories is generated from the LDO.
Note: If the selected package has the SMPS step-down converter option but the SMPS is not used by the application
(and the embedded LDO is used instead), it is recommended to set the SMPS power supply pins as follows:
• VDDSMPS and VLXSMPS connected to VSS
• VDD11 pins connected to VSS through two 2.2 µF capacitors as in normal mode
2.1.1 Independent analog peripherals supply
To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have
an independent power supply that can be separately filtered and shielded from noise on the PCB.
The voltage supply input of the analog peripherals is available on a separate VDDA pin. An isolated supply
ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. After reset, the analog peripherals supplied by VDDA are
logically and electrically isolated and therefore are not available. The isolation must be removed before using
these peripherals, by setting the ASV bit in the PWR_SVMCR register, once the VDDA supply is present.
The VDDA supply can be monitored by analog voltage monitors (AVM), and compared with two thresholds
(1.6 V for AVM1 or 1.8 V for AVM2). For more details, refer to the device datasheet and section 'Peripheral
voltage monitoring (PVM)' of the reference manual.
When a single supply is used, the VDDA pin can be externally connected to the same VDD supply, through an
external filtering circuit, in order to ensure a noise-free VDD reference voltage.
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ADC and DAC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ pin, a separate
reference voltage lower than VDDA.
VREF+ is the highest voltage, represented by the full-scale value, for an analog input (ADC) or output (DAC)
signal. VREF+ can be provided either by an external reference or by the VREFBUF, that can output a configurable
voltage: 1.5, 1.8, 2.048 or 2.5 V. The VREFBUF can also provide the voltage to external components through the
VREF+ pin.
For further information, refer to the device datasheet and section 'Voltage reference buffer (VREFBUF)' of the
reference manual.
2.1.2 Independent I/O supply rail
Some I/Os from port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can
range from 1.08 V to 3.6 V, and is provided externally through the VDDIO2 pin. The VDDIO2 voltage level is
completely independent from VDD or VDDA.
The VDDIO2 pin is available only for some packages (refer to the pinout details in the datasheet for the I/O list).
After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and are therefore not available. The
isolation must be removed before using any I/O from PG[15:2], by setting the IO2SV bit in PWR_SVMR register,
once the VDDIO2 supply is present.
The VDDIO2 supply is monitored by the VDDIO2 voltage monitoring (IO2VM) and compared with the internal
reference voltage (3/4 VREFINT, around 0.9 V).
For more details, refer to the device datasheet and section 'Peripheral voltage monitoring (PVM)' of the reference
manual .
2.1.3 Independent USB transceiver supply
The USB transceivers are supplied from a separate VDDUSB power supply. VDDUSB range is from 3.0 V to 3.6 V
and is completely independent from VDD or VDDA.
After reset, the USB features supplied by VDDUSB are logically and electrically isolated, and are therefore not
available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the
PWR_SVMR register, once the VDDUSB supply is present.
The VDDUSB supply is monitored by the USB voltage monitoring (UVM) and compared with the internal reference
voltage (VREFINT, around 1.2 V). For more details, refer to the device datasheet and section 'Peripheral voltage
monitoring (PVM)' of the product reference manual .
2.1.4 Battery Backup domain
To retain the content of the backup registers and supply the RTC when VDD is turned off, the VBAT pin can be
connected to an optional backup voltage, supplied by a battery or by another source.
The VBAT pin powers RTC, TAMP, LSE oscillator and PC13 to PC15 I/Os, allowing the RTC to operate even
when the main power supply is turned off.
The backup SRAM is optionally powered through the VBAT pin, when the BREN bit is set in the PWR_BDCR1
register.
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset block.
Caution: • During tRSTTEMPO (at VDD startup) or after a PDR (power-down reset) detection, the power switch between
VBAT and VDD remains connected to VBAT pin.
• During the startup phase, if VDD is established in less than tRSTTEMPO (refer to the datasheet for tRSTTEMPO
value), and VDD > VBAT + 0.6 V, a current may be injected into VBAT pin through an internal diode
connected between the VDD pin and the power switch (VBAT). If the power supply/battery connected to
the VBAT pin cannot support this current injection, it is strongly recommended to connect an external
low-drop diode between this power supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin externally to VDD with
a 100 nF external ceramic decoupling capacitor.
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When the Backup domain is supplied by VDD (analog switch connected to the VDD pin), the following pins are
available:
• PC13, PC14 and PC15, that can be used as GPIO pins
• PC13, PC14 and PC15, that can be configured by RTC or LSE (refer to the RTC section of the reference
manual)
• Pins listed below, that are configured by TAMP as tamper pins:
– PE3 (TAMP_IN6/TAMP_OUT3)
– PE4 (TAMP_IN7/TAMP_OUT8)
– PE5 (TAMP_IN8/TAMP_OUT7)
– PE6 (TAMP_IN3/TAMP_OUT6)
– PC13 (TAMP_IN1/TAMP_OUT2)
– PA0 (TAMP_IN2/TAMP_OUT1)
– PA1 (TAMP_IN5/TAMP_OUT4)
– PC5 (TAMP_IN4/TAMP_OUT5)
Note: • Due to the fact that the power switch can transfer only a limited amount of current (3 mA), the use of
PC13 to PC15 I/Os in output mode is restricted: the speed must be limited to 2 MHz with a maximum load
of 30 pF. These I/Os must not be used as current source (for example to drive a LED).
• Under VDD, TAMP_OUTx pins (PE3, PE4, PE5, PE6, PA0, PA1, PC5) keep the same speed features as
the GPIOs to which they are connected. However, under VBAT, the speed of TAMP_OUTx pins must be
limited to 500 kHz.
• The speed of PC13 pin is always limited to 2 MHz, under VDD or under VBAT.
Backup domain access
After a system reset, the Backup domain (RCC_BDCR, PWR_BDCR1, RTC, TAMP and backup registers, plus
backup SRAM) is protected against possible unwanted write accesses. To enable access to the Backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bit in RCC_AHB3ENR register.
2. Set the DBP bit in PWR_DBPR register to enable access to the Backup domain.
VBAT battery charging
When VDD is present, the external battery can be charged on VBAT through an internal resistance, 5 kΩ or 1.5 kΩ,
depending on the VBRS bit in PWR_BDCR2 register.
The battery charging is enabled by setting VBE bit in PWR_BDCR2. It is automatically disabled in VBAT mode.
2.1.5 Voltage regulator
The STM32U575/585 devices embed the following internal regulators in parallel to provide the VCORE supply for
digital peripherals, SRAM1/2/3/4, and embedded Flash memory:
• SMPS step-down converter
• LDO (linear voltage regulator)
They can be selected when the application runs, depending on the application requirements. The SMPS allows
the power consumption to be reduced, but the noise generated by the SMPS may impact some peripheral
behaviors, requiring the application to switch to LDO when running the peripheral, in order to reach the best
performances.
Except for Standby circuitries and the Backup domain, LDO or SMPS can be used in all voltage scaling ranges
(range 1/2/3/4), in all Stop modes (Stop 0/1/2/3) and in Standby with SRAM2 (refer to the 'low-power mode
summary' table in the reference manual).
The STM32U575/585 devices without SMPS embed only the LDO regulator, that controls all voltage-scaling
ranges and power modes.
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Dynamic Voltage scaling management
Both LDO and SMPS regulators can provide four different voltages (voltage scaling) and can operate in all Stop
modes. Both regulators also can operate in the following ranges:
•Range 1 (1.2 V, 160 MHz), high performance: provides a typical output voltage at 1.2 V and is used when
the system clock frequency is up to 160 MHz.
•Range 2 (1.1 V, 110 MHz), medium-high performance: provides a typical output voltage at 1.1 V and is used
when the system clock frequency is up to 110 MHz.
•Range 3 (1.0 V, 55 MHz), medium-low power: provides a typical output voltage at 1.0 V and is used when
the system clock frequency is up to 55 MHz.
•Range 4 (0.9 V, 25 MHz), low power: provides a typical output voltage at 0.9 V and is used when the system
clock frequency is up to 25 MHz.
Voltage scaling is selected through the VOS[1:0] field in PWR_VOSR register.
Caution: The EPOD (embedded power distribution) booster must be enabled and ready before increasing the system
clock frequency above 50 MHz in Range 1 and Range 2 (refer to reference manual for sequences to switch
between voltage scaling ranges).
2.1.6 Power supply for I/O analog switches
Some I/Os embed analog switches for both analog peripherals (ADCs, COMPs, DACs) and TSC (touch
sensing controller) functions. These switches are by default supplied by VDDA, but can be supplied by a
VDDA voltage booster or by VDD, depending on the configuration of ANASWVDD and BOOSTEN bits in
SYSCFG_CFGR1 register.
It is recommended to supply the I/O switches with the highest voltage value between VDDA, VDDA booster
and VDD.
Note: If possible, select VDDA or VDDA booster rather than VDD, as they are often less noisy.
The analog switches for TSC function are supplied by VDD.
2.2 Power supply schemes
The device is powered by a stabilized VDD power supply as described below:
•VDD pins must be connected to VDD with external decoupling capacitors: a 10 μF (typical value, 4.7 µF
minimum) single tantalum or ceramic capacitor for the package, and a 100 nF ceramic capacitor for each
VDD pin.
•VDD11 pins are present only on packages with SMPS. The SMPS step-down converter requires a 2.2 μH
(typical) external ceramic coil connected between VLXSMPS and VDD11 pins. In addition, two 2.2 μF
capacitors on VDD11 pins are connected to the VSSSMPS pin.
• The VCAP pin is present only on standard packages (without SMPS). It requires a 4.7 µF (typical) external
decoupling capacitor connected to VSS. If there are two VCAP pins (UFBGA169 package), each VCAP pin
must be connected to a 2.2 µF (typical) capacitor (for a maximum of 4.7 µF).
• The VDDA pin must be connected to two external decoupling capacitors: 100 nF ceramic and 1 μF tantalum
or ceramic.
Additional precautions can be taken to filter digital noise: VDDA can be connected to VDD through a ferrite
bead.
•VDDIO2 pins must be connected to an external decoupling capacitors of 4.7 µF, tantalum or ceramic. In
addition, each VDDIO2 pin requires an external 100 nF ceramic capacitor.
• VDDUSB pin must be connected to an external 100 nF ceramic capacitor.
• The VREF+ pin can be provided by an external voltage reference. In this case, an external 100 nF + 1 μF
tantalum or ceramic capacitor must be connected on this pin.
It can also be provided internally by the VREFBUF. In this case, an external 100 nF + 1 μF (typical) capacitor
must be connected on this pin.
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• The VBAT pin can be connected to an external battery to preserve the content of the Backup domain:
– When VDD is present, the external battery can be charged on VBAT through a 5 kΩ or 1.5 kΩ internal
resistor. In this case, the user can insert a capacitor according to the expected discharging time (1 µF
is recommended).
– If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD with
a 100 nF external ceramic decoupling capacitor.
• The VDDUSB pin when present in a package can be connected to a ceramic capacitor of 100 nF.
The figures below details the power supply schemes for packages with and without SMPS.
Figure 3. Power supply scheme for STM32U575x and STM32U585x (without SMPS)
VDDIO2
VDD
Level shifter
I/O
logic
Kernel logic
(CPU, digital
and
memories)
Backup circuitry
(LSE, RTC, TAMP
backup registers,
backup SRAM)
IN
OUT
LDO
regulator
GPIOs
1.65 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+ 1 x 10 µF
m x 100 nF
Level shifter
I/O
logic
+ 4.7 µF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
100 nF
+1 µF
VDDA
VSSA
VREF
100 nF+ 1 µF
VCORE
4.7 µF
VCAP
VDDUSB
3.3 V
100 nF
Caution: If there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF (typical) capacitor
(for a total around 4.4 µF).
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Figure 4. Power supply scheme for STM32U575xQ and STM32U585xQ (with SMPS)
VDDIO2
VDD
Kernel logic
(CPU, digital
and memories)
Level shifter
IO
logic
Backup circuitry
(LSE, RTC, TAMP,
backup registers,
backup SRAM)
IN
OUT
GPIOs
1.65 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+ 10 µF
m x100 nF
Level shifter
IO
logic
+ 4.7 µF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
100 nF
+ 1 µF
VDDA
VSSA
VREF
100 nF+ 1 µF
VSSSMPS
2 x VDD11
VLXSMPS
VDDSMPS
VDD
2.2 µH
2 x 2.2 µF
10 µF
SMPS ON
SMPS OFF
LDO
SMPS
VDDUSB
3.3 V
100 nF
Voltage regulator
Note: • SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on application
requirements. However, only one of them is active at the same time. When SMPS is active, it feeds the
VCORE on the two VDD11 pins provided through the SMPS VLXSMPS output pin. A 2.2 µH coil and a
2.2 μF capacitor on each VDD11 pin are then required. When LDO is active, it provides the VCORE and
regulates it using the same decoupling capacitors on VDD11 pins.
• It is recommended to add a decoupling capacitor of 100 nF near each VDD11 pin/ball, but it is not
mandatory.
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2.3 Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD
2.3.1 Power supply isolation
The devices feature a powerful reset system that ensures the main power supply (VDD) has reached a valid
operating range before releasing the MCU reset.
This reset system is also in charge of isolating the independent power domains: VDDA, VDDUSB, VDDIO2, and
VDD. This reset system is supplied by VDD and is not functional before VDD reaches a minimal voltage (1 V in
worse-case conditions).
In order to avoid leakage currents between the available supplies and VDD (or ground), VDD must be provided first
to the MCU and released last with tolerance during power down (refer to Section 2.3.3 ).
2.3.2 General requirements
During power-up and power-down phases, the following power sequence requirements must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2 and VDDUSB) must remain below
VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
Figure 5. Power-up/power-down sequence
0.3
1
VDD_MIN
VDD_MAX
Operating modePower-on Power-down time
V
VDDX(1)
VDD
Invalid supply area
VDDX < VDD + 300 mV
VDDX independent from VDD
Transient phase with energy below 1 mJ
(1) VDDX refers to any power supply among VDDA, VDDIO2 and VDDUSB.
Note: VBAT is an independent supply and has no constraint versus VDD. All power supply rails can be tied together.
2.3.3 Particular conditions during power-down phase
During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided
to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time
constants during the power-down transient phase (refer to Figure 5).
VDDX (VDDA, VDDIO2, or VDDUSB) power rails must be switched off before VDD.
Note: During the power-down transient phase, VDDX can remain temporarily above VDD (refer to Figure 5).
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Example of computation of the energy provided to the MCU during the power-down phase
If the sum of decoupling capacitors on VDDX is 10 μF and VDD drops below 1 V while VDDX is still at 3.3 V, the
energy remaining in the decoupling capacitors is:
E = ½ C x V2 = ½ x 10-5 x 3.32 = 0.05 mJ
The energy remaining in the decoupling capacitors is below 1 mJ, so it is acceptable for the MCU to absorb it.
2.4 Reset and power-supply supervisor
2.4.1 Brownout reset (BOR)
The devices have a Brownout reset (BOR) circuitry. The BOR is active in all power modes except Shutdown
mode, and cannot be disabled. The BOR monitors the Backup domain supply voltage, that is VDD when present,
VBAT otherwise.
Five BOR thresholds can be selected through option bytes.
During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified VBORx
threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the
VBORx upper limit, the device reset is released and the system can start.
For more details on the Brownout reset thresholds, refer to the electrical characteristics section in the datasheet.
Figure 6. Brownout reset waveform
Hysteresis
Reset
VDD
VBOR (rising edge)
VBOR (falling edge)
tRSTTEMPO
temporization(1)
(1) The reset temporization tRSTTEMPO is present only for the BOR lowest threslhold (VBOR0)
2.4.2 System reset
A system reset sets all registers to their reset values except the reset flags in RCC_CSR register and the
registers in the Backup domain.
A system reset is generated when one of the following events occurs (refer to reference manual for more details):
• a low level on the NRST pin (external reset)
• a window watchdog event (WWDG reset)
• an independent watchdog event (IWDG reset)
• a software reset
• a low-power mode security reset
• an option byte loader reset
• a Brownout reset
These sources act on the NRST pin, that is always kept low during the delay phase. The reset service routine
vector is selected via the boot option bytes.
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The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a
minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse
is generated while the NRST pin is asserted low.
In case of an internal reset, the internal pull-up RPU is deactivated in order to save the power consumption
through the pull-up resistor.
Figure 7. Simplified diagram of the reset circuit
External
reset
VDD
RPU
WWDG reset
Software reset
Low-power manager reset
IWDG reset
Option byte loader reset
Pulse
generator
(min 20 μs)
NRST
System reset
Filter
BOR
2.4.3 Backup domain reset
A Backup domain reset is generated when one of the following events occurs:
• a software reset, triggered by setting the BDRST bit in RCC_BDCR register
• a VDD or VBAT power-on, if both supplies have previously been powered off
A Backup domain reset only affects the LSE oscillator, the RTC and TAMP, the backup registers, the backup
SRAM, and the RCC_BDCR and PWR_BDCR1 registers.
AN5373
Reset and power-supply supervisor
AN5373 - Rev 1 page 13/37

3Packages
3.1 Package summary
The package selection must take into account the constraints that are strongly dependent upon the application.
The list below summarizes the most frequent ones:
• Amount of interfaces required: Some interfaces may not be available on some packages. Some interfaces
combinations may not be possible on some packages.
• PCB technology constrains: Small pitch and high-ball density may require more PCB layers and
higher‑class PCB.
• Package height
• PCB available area
• Noise emission or signal integrity of high-speed interfaces
• Smaller packages usually provide better signal integrity. This is further enhanced as small-pitch and high-ball
density requires multilayer PCBs that allow better supply/ground distribution.
• Compatibility with other devices
Table 1. Package summary for STM32U575/585
Package Size (mm)(1) Pitch (mm) Height (mm)(2) Without SMPS With SMPS
UFQFN48 7 x 7 0.5 0.6 X X
LQFP48 7 x 7 0.5 1.6 X X
LQFP64 10 x 10 0.5 1.6 X X
WLCSP90 4.20 x 3.95 0.4 0.59 - X
LQFP100 14 x 14 0.5 1.6 X X
UFBGA132 7 x 7 0.5 0.6 X X
LQFP144 20 x 20 0.5 1.6 X X
UFBGA169 7 x 7 0.5 0.6 X X
1. Body size, excluding pins for LQFP.
2. Maximum value.
AN5373
Packages
AN5373 - Rev 1 page 14/37

3.2 Pinout summary
Table 2. Pinout summary for STM32U575/585
Pin name
STM32U575xx and STM32U585xx
packages (without SMPS)
STM32U575xQ and STM32U585xQ
packages (with SMPS)
LQFP48
UFQFPN48
LQFP64
LQFP100
UFBGA132
LQFP144
UFBGA169
LQFP48 SMPS
UFQFPN48 SMPS
LQFP64 SMPS
WLCSP90 SMPS
LQFP100 SMPS
UFBGA132 SMPS
LQFP144 SMPS
UFBGA169 SMPS
Specific I/Os
PC14-OSC32_IN X(1) X X X X X X X X X X X X
PC15-
OSC32_OUT X X X X X X X X X X X X X
PH0-OSC_IN X X X X X X X X X X X X X
PH1-OSC_OUT X X X X X X X X X X X X X
System pins
NRST X X X X X X X X X X X X X
PH3-BOOT0 X X X X X X X X X X X X X
Power pins
VBAT X X X X X X X X X X X X X
VDDUSB -(2) X X X X X - X X X X X X
VSSA(3) o o X o X o o o o o o o o
VREF- o o X o X o o o o o o o o
VREF+(4) o o X o X X o o X X X X X
VDDA o o X o X X o o X X X X X
VDDIO2 - - - X X X - - X - X X X
VDD11 - - - - - - X X X X X X X
VDDSMPS - - - - - - X X X X X X X
VSSSMPS - - - - - - X X X X X X X
VLXSMPS - - - - - - X X X X X X X
VCAP X X X X X X - - - - - - -
Number of VDD 3 3 5 6 9 10 3 3 4 5 6 9 10
Number of VSS 3 4 5 6 11 11 3 3 4 5 6 11 11
1. 'X' means the pin is present.
2. '-' means the pin is absent.
3. 'o' means that VSSA and VREF- are internally connected and available on a single pin.
4. 'o' means that VDDA and VREF+ are internally connected and available on a single pin.
AN5373
Pinout summary
AN5373 - Rev 1 page 15/37

Caution: STM32U575/585 packages with and without SMPS are not compatible, in almost all power supply pins of
the above table.
Example: VDDIO2 is the pin number 130 on SMPS package. Pin 130 on the package without SMPS is mapped
to a VSS pin. It means the system is short-circuited when a legacy package is mounted on an SMPS socket.
AN5373
Pinout summary
AN5373 - Rev 1 page 16/37

4Clocks
The following clock sources can be used to drive the system clock (SYSCLK):
• HSI16: high-speed internal 16 MHz RC oscillator clock
• MSIS: multi-speed internal RC oscillator clock
• HSE: high-speed external crystal or clock, from 4 to 50 MHz
• PLL1 clock
The MSIS is used as system clock source after startup from reset, configured at 4 MHz.
The devices have the following additional clock sources:
• MSIK: multi-speed internal RC oscillator clock used for peripherals kernel clocks
• LSI: 32 kHz low-speed internal RC that drives the independent watchdog and optionally the RTC used for
auto-wakeup from Stop and Standby modes
• LSE: 32.768 kHz low-speed external crystal or clock that optionally drives the real-time clock (rtc_ck)
• HSI48: internal 48 MHz RC that potentially drives the OTG FS, the SDMMC and the RNG
• SHSI: secure high-speed internal RC that drives the secure AES (SAES).
• PLL2 and PLL3 clocks
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
Several pre-scalers can be used to configure the AHB and the APB frequencies domains with a maximum
frequency of 160 MHz.
4.1 HSE clock
The high-speed external clock signal (HSE) can be generated from the following clock sources:
• HSE external crystal/ceramic resonator
• HSE user external clock that feeds OSC_IN pin
The resonator and the load capacitors must be placed as close as possible to the oscillator pins in order
to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted
according to the selected oscillator.
AN5373
Clocks
AN5373 - Rev 1 page 17/37

Table 3. HSE/LSE clock sources
Clock source Hardware configuration
External clock OSC_IN OSC_OUT
GPIO
External souce
Crystal/ceramic resonators
OSC_OUTOSC_IN
CL1 CL2
Load capacitors
CL1 and CL2 values depend on the quartz. Refer to the application note Oscillator
design guide for STM8AF/AL/S and STM32 microcontrollers (AN2867) for more
details.
4.1.1 External crystal/ceramic resonator (HSE crystal)
The 4 to 50 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Table 3. Refer to the electrical characteristics section of the
datasheet for more details.
4.1.2 External source (HSE bypass)
In this mode, an external clock source must be provided, with a frequency up to 50 MHz. The external clock signal
(square, sinus or triangle) with ~40 to 60 % duty cycle depending on the frequency (refer to the datasheet), must
drive the OSC_IN pin while the OSC_OUT pin can be used as a GPIO (see Table 3).
Note: For details on pin availability, refer to the pinout section of the datasheet. To minimize the consumption, the
square signal is recommended.
4.2 HSI16 clock
The HSI16 clock signal is generated from an internal 16 MHz RC oscillator. The HSI16 RC oscillator provides
a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal
oscillator. However, even with calibration, the frequency is less accurate than an external crystal oscillator or
ceramic resonator.
The HSI16 clock can be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails.
For more details, refer to section 'Clock security system (CSS)' in the reference manual.
4.3 MSI (MSIS and MSIK) clocks
The MSI is made of four internal RC oscillators: MSIRC0 (48 MHz), MSIRC1 (4 MHz), MSIRC2 (3.072 MHz) and
MSIRC3 (400 kHz). Each oscillator feeds a prescaler providing a division by 1, 2, 3 or 4.
Two output clocks are generated from these divided oscillators:
• MSIS, that can be selected as system clock
• MSIK, that can be selected by some peripherals as kernel clock
MSIS and MSIK frequency range can be adjusted by software, by using respectively the MSISRANGE [3:0] and
MSIKRANGE [3:0] fields in RCC_ICSCR1 register, with MSIRGSEL = 1. Sixteen frequency ranges are available,
generated from the four internal RCs (see the reference manual for more details).
AN5373
HSI16 clock
AN5373 - Rev 1 page 18/37

The MSI clock can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails (see
section' Clock security system (CSS)' in the reference manual).
The MSI oscillator provides a low-cost (no external components) low-power clock source. In addition, when used
in PLL‑mode with the LSE, the MSI provides a very accurate clock source that can be used by the USB OTG-FS
peripheral, and feeds the PLL to run the system at the maximum speed 160 MHz.
Hardware auto calibration with LSE (PLL-mode)
When a 32.768 kHz external oscillator is present in the application, either MSIS or MSIK can be configured in a
PLL-mode. This mode is enabled as follows:
• for MSIS: by setting the MSIPLLEN bit to 1 in RCC_CR register
• for MSIK: by setting the MSIPLLEN bit to 0 in RCC_CR register
In case MSIS and MSIK ranges are generated from the same MSIRC source, the PLL-mode is applied on both
MSIS and MSIK. When configured in PLL-mode, the MSIS or MSIK automatically calibrates itself thanks to the
LSE. This mode is available for all MSI frequency ranges. At 48 MHz, the MSIK in PLL-mode can be used for the
USB OTG-FS device, avoiding the need of an external high-speed crystal.
For more details on how to measure the MSI frequency variation, refer to section Internal/external clock
measurement with TIM15/TIM16/TIM17 in the reference manual.
4.4 LSE clock
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator (see Table 3). It provides a
low-power but highly-accurate clock source to the RTC (real-time clock) peripheral for clock/calendar or other
timing functions.
The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the RCC_BDCR
register, to obtain the best compromise between robustness and short start-up time on one side and low-power-
consumption on the other side.
External source (LSE bypass)
In this mode, an external clock source must be provided, with a frequency up to 1 MHz. The external clock signal
(square, sinus or triangle) with ~50 % duty cycle, must drive the OSC32_IN pin while the OSC32_OUT pin can be
used as GPIO (see Table 3).
AN5373
LSE clock
AN5373 - Rev 1 page 19/37

5Boot configuration
5.1 Boot mode selection
At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0]/SECBOOTADD0[24:0] option bytes are used to
select the boot memory address that includes:
• Boot from any address in user Flash memory
• Boot from system memory (bootloader)
• Boot from any address in embedded SRAM
• Boot from root security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user
option bit to free the GPIO pad if needed.
When TrustZone® is disabled by resetting TZEN option bit (TZEN = 0), the boot space is as detailed in the table
below.
Table 4. Boot modes when TrustZone is disabled (TZEN = 0)
nBOOT0
FLASH_
OPTR[27]
BOOT0
pin PH3
nSWBOOT0
FLASH_
OPTR[26]
Boot address
option‑byte selection Boot area ST programmed default value
- 0 1 NSBOOTADD0[24:0] Boot address defined by user option
bytes NSBOOTADD0[24:0] Flash: 0x0800 0000
- 1 1 NSBOOTADD1[24:0] Boot address defined by user option
bytes NSBOOTADD1[24:0]
Bootloader:
0x0BF9 0000
1 - 0 NSBOOTADD0[24:0] Boot address defined by user option
bytes NSBOOTADD0[24:0] Flash: 0x0800 0000
0 - 0 NSBOOTADD1[24:0] Boot address defined by user option
bytes NSBOOTADD1[24:0]
Bootloader:
0x0BF9 0000
When TrustZone is enabled by setting the TZEN option bit (TZEN = 1), the boot space must be in a secure area.
The SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address. A unique boot entry
option can be selected by setting the BOOT_LOCK option bit. All other boot options are ignored.
AN5373
Boot configuration
AN5373 - Rev 1 page 20/37