ST ST10R272L User manual

®
ST10R272L
USER’S MANUAL
Release 1.0

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Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 BASIC CPU CONCEPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 High instruction bandwidth / fast execution . . . . . . . . . . . . . . . . . . . 12
2.1.2 High function 8-bit and 16-bit arithmetic and logic unit . . . . . . . . . . 12
2.1.3 Extended bit processing and peripheral control . . . . . . . . . . . . . . . . 13
2.1.4 High performance branch, call, and loop processing . . . . . . . . . . . . 13
2.1.5 Instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.6 Programmable multiple priority interrupt system . . . . . . . . . . . . . . . 14
2.2 ON-CHIP SYSTEM RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Peripheral event controller (PEC) and interrupt control . . . . . . . . . . 15
2.2.2 Memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 External bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 SYSTEM CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 PLL operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.3 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.4 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 ON-CHIP PERIPHERAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.1 Peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Peripheral timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.3 Programming hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.4 Reserved bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.5 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.6 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.7 General purpose timer (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.8 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 PROTECTED BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 INTERNAL RAM AND SFR AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 System stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.2 General purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.3 PEC source and destination pointers . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.4 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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3.2 EXTERNAL MEMORY SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 CROSSING MEMORY BOUNDARIES . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 INSTRUCTION PIPELINING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.1 Sequential instruction processing . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.2 Standard branch instruction processing . . . . . . . . . . . . . . . . . . . . . 39
4.1.3 Jump cache instruction processing . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.4 Pipeline effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 BIT-HANDLING AND BIT-PROTECTION . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 INSTRUCTION EXECUTION TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4 CPU SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.1 The system configuration register SYSCON . . . . . . . . . . . . . . . . . . 47
5 MULTIPLY-ACCUMULATE UNIT (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1 MAC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2 MAC OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2.1 Instruction pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2.2 Address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2.3 16 x 16 signed/unsigned parallel multiplier . . . . . . . . . . . . . . . . . . . 72
5.2.4 40-bit signed arithmetic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2.5 40-bit accumulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.6 Data limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.7 Accumulator shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2.8 Repeat unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2.9 MAC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.2.10Number representation & rounding . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3 MAC REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.1 Address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.2 Accumulator & control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.4 MAC INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6 INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1 INTERRUPT SYSTEM STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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6.1.1 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.1.2 Normal interrupt processing and PEC service . . . . . . . . . . . . . . . . . 85
6.1.3 Interrupt system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.4 Interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.5 Interrupt control functions in the PSW . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 OPERATION OF THE PEC CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3 PRIORITIZING INTERRUPT AND PEC SERVICE REQUESTS . . . . . . 94
6.4 INTERRUPT CLASS MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5 SAVING THE STATUS DURING INTERRUPT SERVICE . . . . . . . . . . . 96
6.5.1 Context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.6 INTERRUPT RESPONSE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.7 PEC RESPONSE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.8 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.8.1 Fast external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.9 TRAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.9.1 Software traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.9.2 Hardware traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.9.3 Trap flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.9.4 External NMI trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.9.5 Stack overflow trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.9.6 Stack underflow trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.9.7 Undefined opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.8 Protection fault trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.9 Illegal word operand access trap . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.10Illegal instruction access trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.11Illegal external bus access trap . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.9.12MAC interrupt on condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.1 PORT 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.1.1 Alternate functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.2 PORT 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.2.1 Alternate functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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7.3 PORT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.3.1 Alternate functions of port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.4 PORT 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.4.1 Alternate functions of Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.5 PORT 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.5.1 Alternate functions of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.6 PORT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.6.1 Alternate functions of port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.7 PORT 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.7.1 Alternate functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.8 PORT 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.8.1 Alternate functions of Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8 DEDICATED PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9 EXTERNAL BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.1 SINGLE CHIP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.2 EXTERNAL BUS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.2.1 Multiplexed bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.2.2 Demultiplexed bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.2.3 Switching between bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.2.4 External data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.2.5 Disable/enable control for pin BHE (BYTDIS) . . . . . . . . . . . . . . . . 152
9.2.6 Segment address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.2.7 CS signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.2.8 Segment address versus chip select . . . . . . . . . . . . . . . . . . . . . . . 154
9.3 PROGRAMMABLE BUS CHARACTERISTICS . . . . . . . . . . . . . . . . . . 155
9.3.1 ALE length control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.3.2 Programmable memory cycle time . . . . . . . . . . . . . . . . . . . . . . . . 157
9.3.3 Programmable memory tri-state time . . . . . . . . . . . . . . . . . . . . . . . 158
9.3.4 Read/write delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.3.5 READY/READY controlled bus cycles . . . . . . . . . . . . . . . . . . . . . 160
9.3.6 Programmable chip select timing control . . . . . . . . . . . . . . . . . . . . 162
9.4 CONTROLLING THE EXTERNAL BUS CONTROLLER . . . . . . . . . . . 163

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9.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
9.4.2 Defining address areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
9.4.3 Prioritizing address areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
9.4.4 Precautions and hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.5 EBC IDLE STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.6 EXTERNAL BUS ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.6.1 Entering the hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
9.6.2 Exiting the hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
9.7 THE XBUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10 PWM MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.1 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.1.1Mode 0 - standard PWM generation (edge aligned PWM) . . . . . . 179
10.1.2Mode 1 - symmetrical PWM generation (center aligned) . . . . . . . 181
10.1.3Single shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
10.2 PWM MODULE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10.2.1Up/down counter PT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10.2.2Period register PP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10.2.3Pulse width register PW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
10.2.4PWM control register PWMCON0 . . . . . . . . . . . . . . . . . . . . . . . . . 186
10.2.5PWM control register PWMCON1 . . . . . . . . . . . . . . . . . . . . . . . . . 187
10.3 INTERRUPT REQUEST GENERATION . . . . . . . . . . . . . . . . . . . . . . . 188
10.4 PWM OUTPUT SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11 GENERAL PURPOSE TIMER UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.1 TIMER BLOCK GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.1.1GPT1 core timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
11.1.2GPT1 auxiliary timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . 201
11.1.3Interrupt control for GPT1 timers . . . . . . . . . . . . . . . . . . . . . . . . . 208
11.2 TIMER BLOCK GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.2.1GPT2 core timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.2.2GPT2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.2.3Interrupt control for GPT2 timers and CAPREL . . . . . . . . . . . . . . 225
12 ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE . . . . . . . . . . . 226

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12.1 ASYNCHRONOUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.2 SYNCHRONOUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.3 HARDWARE ERROR DETECTION CAPABILITIES . . . . . . . . . . . . . . 233
12.4 ASC0 BAUD RATE GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.4.1Asynchronous mode baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.4.2Synchronous mode baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
12.5 ASC0 INTERRUPT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
12.6 USING THE ASC0 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
13 SYNCHRONOUS SERIAL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
13.1 XBUS IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
13.2 SSP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
13.2.1SSP control register 0 - SSPCON0 . . . . . . . . . . . . . . . . . . . . . . . . 240
13.2.2SSP Control Register 1 - SSPCON1 . . . . . . . . . . . . . . . . . . . . . . 242
13.2.3SSP transmit buffer registers - SSPTBx . . . . . . . . . . . . . . . . . . . . 243
13.2.4Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
13.2.5Starting a transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
13.2.6Performing a Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
13.2.7Chip enable lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
13.2.8Using the SSP chip enable and clock lines for output functions . . 248
13.2.9Continuous transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
13.2.10Interrupt control for the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
13.2.11SSP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
13.2.12Accessing the on-chip SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
13.2.13Visibility of accesses to the SSP . . . . . . . . . . . . . . . . . . . . . . . . . 253
13.2.14Single chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
13.2.15External bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
13.2.16Accessing the SSP in hold mode . . . . . . . . . . . . . . . . . . . . . . . . 254
13.2.17Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
14 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
14.1 WATCHDOG TIMER OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
15 SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

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Table of Contents
15.1 ASYNCHRONOUS HARDWARE RESET . . . . . . . . . . . . . . . . . . . . . . 259
15.2 SYNCHRONOUS HARDWARE RESET (WARM RESET) . . . . . . . . . . 261
15.3 SOFTWARE RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
15.4 WATCHDOG TIMER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
15.5 PINS AFTER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
15.5.1RESET input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
15.5.2RESET output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15.6 WATCHDOG TIMER OPERATION AFTER RESET . . . . . . . . . . . . . . 269
15.7 REGISTERS RESET VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15.8 INTERNAL RAM AFTER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.9 PORTS AND EXTERNAL BUS CONFIGURATION DURING RESET . 270
15.10APPLICATION SPECIFIC INITIALIZATION ROUTINE . . . . . . . . . . . . 271
15.10.1System start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.10.2Emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
15.10.3Adapt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
15.10.4System clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
15.10.5External bus type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
15.10.6Chip select lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
15.10.7Segment address lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
15.10.8BHE pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
16 REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.1 REGISTER DESCRIPTION FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . 276
16.2 GENERAL PURPOSE REGISTERS (GPRS) . . . . . . . . . . . . . . . . . . . . 277
16.3 SPECIAL FUNCTION REGISTERS ORDERED BY NAME . . . . . . . . . 279
16.4 SPECIAL FUNCTION REGISTERS ORDERED BY ADDRESS . . . . . 284
16.5 IDENTIFICATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
17 POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
17.1 IDLE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

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Table of Contents
17.2 POWER DOWN MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
17.2.1Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
17.2.2Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
17.2.3Exiting interruptible power down mode . . . . . . . . . . . . . . . . . . . . . 297
17.2.4Selecting R and C values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
17.3 STATUS OF OUTPUT PINS DURING IDLE AND POWER DOWN MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
18 SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
18.1 INSTRUCTIONS PROVIDED AS SUBSETS OF INSTRUCTIONS . . . 303
18.2 BCD CALCULATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
18.3 STACK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
18.3.1Internal system stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
18.3.2Circular (virtual) Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
18.3.3Linear stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
18.3.4User stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
18.4 REGISTER BANKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
18.5 CALL PROCEDURE ENTRY-AND-EXIT . . . . . . . . . . . . . . . . . . . . . . . 309
18.5.1Passing parameters on the system stack . . . . . . . . . . . . . . . . . . . 309
18.5.2Cross segment subroutine calls . . . . . . . . . . . . . . . . . . . . . . . . . . 309
18.5.3Providing local registers for subroutines . . . . . . . . . . . . . . . . . . . . 310
18.6 TABLE SEARCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
18.7 PERIPHERAL CONTROL AND INTERFACE . . . . . . . . . . . . . . . . . . . 312
18.8 FLOATING POINT SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
18.9 TRAP/INTERRUPT ENTRY AND EXIT . . . . . . . . . . . . . . . . . . . . . . . . 313
18.10INSEPARABLE INSTRUCTION SEQUENCES . . . . . . . . . . . . . . . . . . 313
18.11OVERRIDING THE DPP ADDRESSING MECHANISM . . . . . . . . . . . 313
18.12SHORT ADDRESSING IN THE EXTENDED SFR (ESFR) SPACE . . 314
19 INDEX OF REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

March 2001 9/320
ST10R272L
USER’S MANUAL
1 INTRODUCTION
The ST10R272L is a new member of the ST10 family designed to give high performance in
applications where low-power operation is important.
The low-power features of the ST10R272L include:
•3.3V operation: Half the power consumption of an equivalent 5V device (250mW at
25MHz).
•Idle Mode: Consumes less than 100mW at 25MHz.
•Power-Down Mode: Less than 170uW.
•Static Design: Operates at a lower clock speed for lower power consumption.
The Performance Features of the ST10R272Linclude:
•Operation up to 50MHz: Double the performance of existing ST10/C166 devices
•On-chip DSP co-processor: Up to 25Mips DSP performance
The ST10R272L is fully software compatible with other members of the ST10 and C166
families. Most designs using R163 or R165 type devices can be adapted for the R272L with
minimal change, giving the immediate benefits of lower power consumption and higher
performance.
This manual describes the functionality of the ST10R272L. The architectural overview gives a
general description of the ST10R272L device. It describes in brief, the CPU performance, the
on-chip system resources, the clock generator, the peripheral blocks and the protected bits.
The detailed operation of the CPU, the MAC and the on-chip peripherals - parallel ports,
external bus interface, peripheral event controller, general purpose timers, serial interfaces,
watchdog timer, bootstrap loader, capcom units, pulse width module and the analog-digital
converter - are contained in the subsequent chapters. The operating modes - system reset,
power reduction, interrupt handling and system programming - are described in detail, in
separate chapters.The special function registers are listed by both name and hexadecimal
address. The instruction set is covered in the ‘ST10 Family Programming Manual’ and is not
described in this manual.
The DC and AC electrical characteristics and the pin description for each available package
are covered in the device Data Sheet and Errata Sheet, and are not described in this manual.
Before starting on a new design, verify the device characteristics with an up-to-date copy of
the device Data Sheet and Errata Sheet. An index of registers is contained at the back of the
manual.

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2 ARCHITECTURAL OVERVIEW
The architecture of the ST10R272L combines the advantages of both RISC and CISC
processors with an advanced peripheral subsystem. The following block diagram shows the
different on-chip components and the advanced - high bandwidth - internal bus structure of
the ST10R272L.
Figure 1 ST10R272L block diagram
ST10 CORE
1KByte
DPRAM
Interrupt Controller
Port 4 Port 1
8-bit 2x8-bit Port 0
2x8-bit
Port 2
4-bit
Port 6
8-bit
I/O
CS(4:0)
I/O
HOLD
HLDA
BREQ A(15:0)
I/O, D(7:0)
D(15:8), D(7:0)
A(15:8), AD(7:0)
AD(15:8), AD(7:0)
I/O
Port 3
15-bit
I/O
EXIN(3:0)
XTAL1
dedicated
pins
ASC GPT1/2
&PEC
I/O
CLKOUT,
BHE/WRH, RxD0,
TxD0, T2IN, T3IN,
T4IN, T3EUD,
T3OUT, CAPIN,
T6OUT
I
T2EUD,
T4EUD, T5IN,
T6IN, T5EUD,
T6EUD
EA, ALE, RD,
WR/WRL,
READY, NMI,
RSTIN,
RSTOUT
WDT XSSP
4-bit
I/O
A(23:16),
SSPCLK,
SSPDAT,
SSPCE(1:0)
Port 5
6-bit
OSC
PLL
XTAL2
Port 7
4-bit
PWM
I/O
POUT3
MAC

ST10R272L - ARCHITECTURAL OVERVIEW
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2.1 Basic CPU concepts
The main core of the CPU contains a 4-stage instruction pipeline, a MAC
multiply-accumulation unit, a separate multiply and divide unit, a bit-mask generator and a
barrel shifter. Most instructions can be executed in one CPU clock cycle.
The CPU includes an actual register context, consisting of 16 wordwide GPRs physically
located in the on-chip RAM area. A Context Pointer (CP) register determines the base
address of the active register bank to be accessed by the CPU. The number of register
banks is only restricted by the available internal RAM space. For easy parameter passing,
one register bank may overlap others.
A system stack of up to 1024 bytes stores temporary data. The system stack is allocated in
the on-chip RAM area, and is accessed by the CPU, via the stack pointer (SP) register. Two
separate SFRs, STKOV and STKUN, are compared against the stack pointer value during
each stack access, to detect stack overflow or underflow.
The MAC improves the performance of signal processing algorithms. It provides
non-pipelined single-cycle instructions - including 32-bit signed arithmetic (addition,
subtraction, shift,...), 16 by 16 multiplication, and multiplication with cumulative subtraction/
addition.
Figure 2 CPU block diagram
16
16
Internal
RAM
1KByte
R15
R0
General
Purpose
Registers
R0
R15
MDH
MLD
Barrel-Shift
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
Context Ptr
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
CPU
IDX0 IDX1
QX1QX0
QR0 QR1
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs

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2.1.1 High instruction bandwidth / fast execution
Most of the ST10R272L’s instructions can be executed in just one instruction cycle - shift
and rotate instructions (irrespective of the number of bits to be shifted). Branch, multiply and
divide instructions normally take more than one instruction cycle, but have also been
optimized. For example, branch instructions require only one additional machine cycle when
a branch is taken, and because of the ‘Jump Cache’, most branches taken in loops require
no additional machine cycles.
The four-stage pipeline improves CPU processing speed:
fetch: an instruction is fetched from the internal ROM or RAM or from the
external memory, based on the current IP value
decode: the previously fetched instruction is decoded and the required
operands are fetched
execute: the specified operation is performed on the previously fetched
operands
write back: the result is written to the specified location
If this technique were not used, each instruction would require four machine cycles.
2.1.2 High function 8-bit and 16-bit arithmetic and logic unit
Instruction decoding is primarily generated from PLA outputs, based on the selected
opcode. No microcode is used and each pipeline stage receives control signals, staged in
control registers, from the decode stage PLAs. Pipeline holds are primarily caused by wait
states for external memory accesses, and cause a signal to be held in the control registers.
Multiple-cycle instructions are performed through instruction injection and simple internal
state machines which modify the required control signals.
All standard arithmetic and logical operations are performed in the 16-bit ALU. For byte
operations, signals are provided from bits six and seven of the ALU result, and are used to
set the condition flags. Multiple precision arithmetic is provided through a 'CARRY-IN' signal,
to the ALU, from previously calculated portions of the desired operation. Most internal
execution blocks perform operations on either 8-bit or 16-bit quantities. Once the pipeline
has been filled, one instruction is completed per machine cycle, except for multiply and
divide. An advanced Booth algorithm allows four bits to be multiplied and two bits to be
divided per machine cycle. Therefore, these operations use two coupled 16-bit registers
(MDL and MDH), and require four and nine machine cycles respectively, to perform a 16-bit
by 16-bit (or 32-bit by 16-bit) calculation, plus one machine cycle to setup and adjust the
operands and the result. The longer multiply and divide instructions can be interrupted
during their execution, to permit fast interrupt response. The Instruction Set contains
instructions for byte packing in memory, and byte and word sign extension for wide
arithmetic operations.

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A set of consistent flags is automatically updated in the PSW after each arithmetic, logical,
shift, or movement operation. These flags cause branching on specific conditions.
User-specifiable branch tests give support for signed and unsigned arithmetic. These flags
are preserved automatically by the CPU on entry into an interrupt or trap routine. All targets
for branch calculations are computed in the central ALU.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic
shifts are also supported.
2.1.3 Extended bit processing and peripheral control
A large number of instructions have been dedicated to bit processing, to provide efficient
control and testing of peripherals while enhancing data manipulation. These instructions
provide direct access to two operands in the bit-addressable space, without using temporary
flags.
The same logical instructions that are available for words and bytes, are also supported for
bits. A peripheral control bit can be compared and modified in one instruction. Multiple bit
shift instructions avoid long instruction streams of single bit shift operations. These are also
performed in a single machine cycle.
Bit field instructions can modify multiple bits from one operand, in a single instruction.
2.1.4 High performance branch, call, and loop processing
Branch instructions only require one extra machine cycle when a branch is taken, because
the target address is pre-calculated while decoding the instruction. To decrease loop
execution overhead, three enhancements have been provided:
•Single cycle branch execution is perfomed after the first iteration of a loop. Therefore,
only one machine cycle is lost during the execution of the entire loop. In loops which fall
through on completion, no machine cycles are lost when exiting the loop. No special
instructions are required to perform loops, and loops are automatically detected during
execution of branch instructions.
•End-of-table detection avoids the use of two compare instructions embedded in loops.
The lowest negative number is placed at the end of the table and branching is specified
if neither this value nor the compared value have been found. The loop is terminated if
either condition is met. The terminating condition can then be tested.
•The third loop enhancement provides a more flexible solution than the Decrement and
Skip on Zero instruction found in other microcontrollers. Through the use of Compare
and Increment or Decrement instructions, the user can make comparisons to any value.
This allows loop counters to cover any range, which is useful in table searching.
The system state is automatically saved on the internal system stack . Instructions are not
required to preserve state upon entry and exit of interrupt or trap routines. Call instructions

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push the value of the IP on the system stack, and require the same execution time as branch
instructions.
Instructions have been added to support indirect branch and call instructions, supporting the
implementation of multiple CASE statement branching in assembler macros and high level
languages.
2.1.5 Instruction formats
The ST10 Family instruction set has two parts: a standard instruction set which is used for all
ST10 Family products, and a MAC instruction set which is used for products containing the
MAC. Code compiled for the non-MAC ST10/C166 processors, will run on the ST10R272L.
However, MAC instructions run on non-MAC ST10/C166 processors will be trapped because
undefined opcodes are used. The instruction set is described in the ST10 Family
Programming Manual.
The standard instruction set has different addressing modes to access word, byte and bit
data. Specific instructions support the conversion (extension) of bytes to words. A variety of
direct, indirect or immediate addressing modes specify operands. ATOMIC and EXTended
instructions disable standard and PEC interrupts and class A traps.
The MAC instruction set uses some standard ST10 addressing modes such as GPR or
#data4 for immediate shift value. New MAC instruction addressing modes supply the MAC
with up to 2 new operands per instruction cycle. These allow indirect addressing with
address pointer post-modification. Double indirect addressing requires 2 pointers, one can
be supplied by any GPR, the other is provided by one of two new specific SFRs IDX0 and
IDX1. Two pairs of offset registers QR0/QR1 and QX0/QX1 are associated with each pointer
(GPR or IDXi). The GPR pointer gives access to the entire memory space, whereas IDXiare
limited to the internal Dual-Port RAM, except for the CoMOV instruction.
2.1.6 Programmable multiple priority interrupt system
There are several response mechanisms to service requests generated from various
sources, internal or external to the microcontroller. Any of these interrupt requests can be
programmed to be serviced, either by the Interrupt Controller, or by the Peripheral Event
Controller (PEC).
Fast external-interrupt inputs service external-interrupts with high-precision requirements.
These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge
or both edges).
Software-interrupts are supported by the ‘TRAP’ instruction, in combination with an
individual trap (interrupt) number.
Hardware-traps cause immediate non-maskable system reaction, similar to a
standard-interrupt service (branching to a dedicated vector table location). The occurrence

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of a hardware trap is, additionally, signified by an individual bit in the trap flag register (TFR).
Except when another higher-priority trap service is in progress, a hardware-trap will interrupt
any actual program execution. In turn, hardware-trap services can not, normally be
interrupted by a standard-interrupt or PEC-interrupt.
2.2 On-chip system resources
The ST10R272L provides a number of powerful system resources designed around the
CPU.
2.2.1 Peripheral event controller (PEC) and interrupt control
The Peripheral Event Controller responds to an interrupt request with a single data-transfer
(word or byte) which consumes one instruction cycle, and does not require a ‘save and
restore machine-status’. Each interrupt source is prioritized in every machine cycle, in the
interrupt control block. If a PEC service is selected, a PEC transfer is started. If a
CPU-interrupt service is requested, the current CPU priority level (stored in the PSW
register) is tested to determine whether a higher-priority interrupt is currently being serviced.
When an interrupt is acknowledged, the current machine-state is saved on the internal
system-stack, and the CPU branches to the system specific vector for the peripheral.
The PEC contains a set of SFRs which store the count value and control bits for eight data
transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the
source and destination addresses. The PEC is controlled by SFRs containing the channel
configuration.
An individual PEC-transfer counter is implicitly decremented for each PEC service, except
when performing in the continuous-transfer mode. When the counter reaches zero, a
standard-interrupt is performed to the vector location related to the corresponding source.
PEC services are very well suited, for example, to move register contents to or from a
memory table. The ST10R272L has 8 PEC channels, each of which offers fast
interrupt-driven data transfer capabilities.
2.2.2 Memory areas
The memory space of the ST10R272L is configured in a Von Neumann architecture which
means that code memory, data memory, registers and IO ports are organized within the
same linear address spaces. The entire memory space can be accessed bytewise or
wordwise. Particular portions of the on-chip memory are directly bit addressable.
A 1KByte 16-bit wide internal RAM is used for variables, register banks, and the system
stack. It also contains the PEC pointers and the bit-addressable space.
The CPU has an actual register context, consisting of up to 16 wordwide and/or bytewide
GPRs, which are physically located within the on-chip RAM area. A Context Pointer (CP)
register determines the base address of the active register bank accessed by the CPU. The

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number of register banks is only restricted by the available internal RAM space. For easy
parameter passing, one register bank may overlap another.
A system stack of up to 512 words stores temporary data. It is located in the on-chip RAM
area, and is accessed by the CPU via the Stack Pointer (SP) register. Two separate SFRs
(STKOV and STKUN) are implicitly compared against the stack pointer value, on each stack
access, for the detection of a stack overflow or underflow.
Hardware detection of the selected memory space is placed at the internal memory
decoders. It allows the user to specify any address directly or indirectly, and obtain the
desired data without using temporary registers or special instructions.
For special function registers 1024 Bytes of address space are reserved. The standard
Special Function Register area (SFR) uses 512 bytes, and the Extended Special Function
Register area (ESFR) uses the other 512 bytes. (E)SFRs are word-wide registers used for
controlling and monitoring the on-chip units. Unused (E)SFR addresses are reserved for
future development.
2.2.3 External bus interface
All external memory accesses are performed by the External Bus Controller (EBC). It can be
programmed either to Single-Chip Mode when no external memory is required, or to one of
four different external memory access modes:
•16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
•16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
•16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
•16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1, and data is input/output
on PORT0 or P0L, respectively. In the multiplexed bus modes, both addresses and data use
PORT0 for input/output.
Important timing characteristics of the external bus interface (memory cycle time, memory
tri-state time, length of ale and read write delay) have been made programmable, to give the
choice of a wide range of different types of memories and external peripherals. In addition,
up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) to access different resources with different bus characteristics. These address
windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1. All accesses to locations not covered by these 4 address windows are
controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be
generated to save external glue logic. Access to very slow memories is supported by the
‘Ready’ function.

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For applications which require less than 16MBytes of external memory space, the address
space can be restricted to 1MByte, 256KByte or to 64KByte. Port 4 outputs four, two or no
address lines. If an address space of 16MBytes is used, Port 4 outputs all 8 address lines.
The on-chip XBUS is an internal representation of the external bus. It is used to access
integrated application-specific peripherals/modules in the same way as external
components. It provides a defined interface for customized peripherals.
2.3 System clock generator
The on-chip clock generator provides the basic clock signal that controls the activities of the
controller hardware. Its oscillator can run with an external crystal and appropriate oscillator
circuitry (refer to “DEDICATED PINS” on page 143) or can be driven by an external
oscillator. The oscillator can directly feed the external clock signal to the controller hardware
(through buffers) and divides the external clock frequency by 2, or feeds an on-chip phase
locked loop (PLL) which multiplies the input frequency by a selectable factor F. The resulting
internal clock signal is referred to as the ‘CPU clock’. Two separate clock signals are
generated for the CPU and the peripherals. While the CPU clock is stopped during idle
mode, the peripheral clock keeps running. Both clocks are switched off when power-down
mode is entered.
The on-chip PLL circuit allows operation of the ST10R272L on a low frequency external
clock while still providing maximum performance. The PLL multiplies the external clock
frequency by a selectable factor of 1:F and generates a CPU clock signal with 50% duty
cycle. The PLL also provides fail safe mechanisms which detect frequency deviations and
the execution of emergency actions in case of an external clock failure. (Refer to
“WATCHDOG TIMER” on page 255.)

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The table below lists all the possible selections for the on-chip clock generator. Refer to the
device datasheet for the specific External Clock Input Range.
Figure 3 PLL block diagram
P0.15-13 (P0H.7-5) CPU frequencyfCPU =
fXTAL * F Notes
111F
XTAL * 4 Default configuration
110F
XTAL * 3
101F
XTAL * 2
100F
XTAL * 5
011F
XTAL * 1 Direct drive1
010F
XTAL * 1.5
001F
XTAL / 2 CPU clock via 2:1 prescaler
000 F
XTAL * 2.5
Table 1 CPU clock generation mechanisms
MUX
Oscillator
Circuit PLL Circuit
fPLL = F * fIN
reset sleep Unlock
Reset
PWRDN
XP3INT
fPLL
fXTAL
P0H.7-5
fCPU
XTAL2
XTAL1 Factor
Oscillator
Watchdog
Prescaler
(- 2) MUX
P0H.6
MUX

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2.3.1 PLL operation
The PLL is enabled except when P0H.[7..5] = ‘011’ or ‘001’ during reset. On power-up, the
PLL provides a stable clock-signal within ca. 1 ms after VCC has reached 5V+10%, even if
there is no external clock-signal (in this case, the PLL will run at its basic frequency of 2...5
MHz). The PLL will start synchronizing with the external clock signal as soon as it is
available, but only during a hardware reset. The PLL is synchronous with this clock at a
frequency of F*f
XTAL, i.e. the PLL locks to the external clock.
Note If the ST10R272L is required to operate on the desired CPU clock directly after
reset, make sure that RSTIN remains active until the PLL has locked (ca. 1 ms).
The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency, the output frequency may be
slightly higher or lower than the desired frequency. This jitter is irrelevant for long time
periods. For short periods (1...4 CPU clock cycles), it remains below 4%.
When the PLL detects that it is no longer locked, i.e. no longer stable, it generates an
interrupt request (on PLL Unlock XP3INT interrupt node). This occurs when the input clock is
unstable and especially when the input clock fails completely, e.g. due to a broken crystal. In
this case, the synchronization mechanism reduces the PLL output frequency down to the
PLL’s basic frequency (2...5 MHz). The basic frequency is still generated and the CPU can
execute emergency actions.
2.3.2 Prescaler operation
When pins P0H.[7..5] = ’001’ during reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fXTAL.
The PLL runs on a basic frequency of 2...5 MHz, and delivers the clock signal for the
oscillator watchdog.
2.3.3 Direct drive
When pins P0H.[7..5] = ’011’ during reset, the CPU clock is directly driven from the internal
oscillator with the input clock signal, i.e. fCPU = fOSC. The maximum input clock frequency
depends on the clock signal’s duty cycle, because the minimum values for the clock phases
(TCLs) must be reselected.
The PLL runs on its basic frequency of 2...5 MHz, and delivers the clock signal for the
oscillator watchdog.
1. The maximum depends on the duty cycle of the external clock signal. The maximum input
frequency is 25 MHz when using an external crystal oscillator, however, higher frequencies
can be applied with an external clock source.