2Clocks
The microcontrollers of the STM32C0 series provide the following clock sources producing primary clocks:
•HSI48 RC, a high-speed fully integrated RC oscillator producing HSI48 clock (48 MHz)
•HSE OSC, a high-speed oscillator with external crystal/ceramic resonator or external clock source,
producing HSE clock (4 to 48 MHz)
•LSI RC, a low-speed fully integrated RC oscillator producing LSI clock (about 32 kHz)
•LSE OSC, a low-speed oscillator with external crystal/ceramic resonator or external clock source,
producing LSE clock (accurate 32.768 kHz or external clock up to 1 MHz)
•I2S_CKIN, a pin for direct clock input for the I2S1 peripheral
Each oscillator can be switched on or off independently when it is not used, to optimize power consumption.
Check the subsections of this section for more functional details. For electrical characteristics of the internal and
external clock sources, refer to the device datasheet.
The device produces secondary clocks by dividing or/and multiplying the primary clocks:
•HSISYS, a clock derived from HSI48 through division by a factor programmable from 1 to 128.
•SYSCLK, a clock obtained through selecting one of the LSE, LSI, HSE, and HSISYS clocks.
•HSIKER, a clock derived from HSI48 through division by a factor programmable from 1 to 8.
•HCLK, a clock derived from SYSCLK through division by a factor programmable from 1 to 512.
•HCLK8, a clock derived from HCLK through division by eight.
•PCLK, a clock derived from HCLK through division by a factor programmable from 1 to 16.
•TIMPCLK, a clock derived from PCLK, running at PCLK frequency if the APB prescaler division factor is
set to 1, or at twice the PCLK frequency otherwise.
Additional secondary clocks are generated by fixed division of HSE, HSI48, and HCLK clocks.
The HSISYS is used as a system clock source after startup from reset, with the division by four (producing 12
MHz frequency).
The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains, respectively. Their
maximum allowed frequency is 48 MHz.
The peripherals are clocked with the clocks from the bus that they are attached to (HCLK for AHB, PCLK for APB)
except:
•TIMx, with:
– TIMPCLK running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the
PCLK frequency otherwise
•USARTx, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
– LSE
– PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI48 or LSE.
•ADC, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
The wake-up from Stop mode is supported only when the clock is HSI48.
•I2Cx, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
– PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI48.
•I2Sx, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
– I2S_CKIN pin
AN5673
Clocks
AN5673 - Rev 2 page 8/32
