Teridian 73S1209F User manual

Simplifying System Integration
TM
73S1209F
Evaluation Board User Guide
August 19, 2009
Rev. 1.3
UG_1209F_034

73S1209F Evaluation Board User Guide UG_1209F_034
2 Rev. 1.3
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Microsoft, Windows and Vista are registered trademarks of Microsoft Corporation.
Signum is a trademark of Signum Systems Corporation.
Keil is a trademark of ARM® Ltd.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL [phone], FAX [phone], http://www.teridian.com

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 3
Table of Contents
1Introduction ...................................................................................................................................4
1.1 Evaluation Kit Contents.........................................................................................................5
1.2 Evaluation Board Features....................................................................................................5
1.3 Recommended Equipment and Test Tools............................................................................5
2Evaluation Board Setup.................................................................................................................6
2.1 Connecting the Evaluation Board with an Emulation Tool......................................................7
2.2 Loading User Code into the Evaluation Board .......................................................................8
3Using the PCCID Application......................................................................................................10
3.1 Host Demonstration Software Installation............................................................................10
4Evaluation Board Hardware Description....................................................................................11
4.1 Jumpers, Switches and Modules.........................................................................................11
4.2 Test Points .........................................................................................................................16
4.3 Schematic...........................................................................................................................17
4.4 PCB Layouts.......................................................................................................................18
4.5 Bill of Materials ...................................................................................................................24
4.6 Schematic Information ........................................................................................................27
4.6.1 Reset Circuit..............................................................................................................27
4.6.2 Oscillators .................................................................................................................27
4.6.3 LCD ..........................................................................................................................28
4.6.4 Smart Card Interface .................................................................................................29
5Ordering Information...................................................................................................................30
6Related Documentation...............................................................................................................30
7Contact Information.....................................................................................................................30
Revision History..................................................................................................................................31
Figures
Figure 1: 73S1209F Evaluation Board .....................................................................................................4
Figure 2: 73S1209F Evaluation Board Basic Connections........................................................................6
Figure 3: 73S1209F Evaluation Board Basic Connections with ADM-51 ICE ............................................7
Figure 4: EmulatorWindow Showing RESET and ERASE Buttons...........................................................9
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu.....................................9
Figure 6: 73S1209F Evaluation Board Jumper, Switch and Module Locations........................................15
Figure 7: 73S1209F Evaluation Board Electrical Schematic ...................................................................17
Figure 8: 73S1209F Evaluation Board Top View (Silkscreen).................................................................18
Figure 9: 73S1209F Evaluation Board Bottom View (Silkscreen)............................................................19
Figure 10: 73S1209F Evaluation Board Top Signal Layer ......................................................................20
Figure 11: 73S1209F Evaluation Board Middle Layer 1 – Ground Plane.................................................21
Figure 12: 73S1209F Evaluation Board Middle Layer 2 – Supply Plane .................................................22
Figure 13: 73S1209F Evaluation Board Bottom Signal Layer .................................................................23
Figure 14: External Components for RESET..........................................................................................27
Figure 15: Oscillator Circuit....................................................................................................................27
Figure 16: LCD Connections..................................................................................................................28
Figure 17: Smart Card Connections.......................................................................................................29
Tables
Table 1: Flash Programming Interface Signals.........................................................................................8
Table 2: Evaluation Board Jumper, Switch and Module Description .......................................................11
Table 3: Evaluation Board Test Point Description...................................................................................16
Table 4: 73S1209F Evaluation Board Bill of Materials............................................................................24

73S1209F Evaluation Board User Guide UG_1209F_034
4 Rev. 1.3
1 Introduction
The Teridian Semiconductor Corporation (TSC) 73S1209F Evaluation Board is used to demonstrate the
capabilities of the 73S1209F Smart Card Controller device. It has been designed to operate either as a
standalone or as a development platform.
The 73S1209F Evaluation Board can be programmed to run any of the Teridian turnkey applications or a
user-developed custom application. Teridian provides its USB CCID application preloaded on the board
and an EMV testing application on the CD.
Applications can be downloaded through the In-Circuit-Emulator (ICE) or through the TSC Flash
Programmer Model TFP2. As a development tool, the evaluation board can operate in conjunction with
an ICE to develop and debug 73S1209F based embedded applications.
The 73S1209F Evaluation Board uses the same PWB as the 73S1215F. The 73S1215F has
some features that the 73S1209F does not contain. These include the 32 kHz oscillator, USB
interface, LED2 and LED3. These features are depopulated on the 73S1209F.
Figure 1: 73S1209F Evaluation Board

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 5
1.1 Evaluation Kit Contents
The 73S1209F Evaluation Kit contains the following:
•73S1209F Evaluation Board: 4-layer, rectangular PWB as shown in Figure 1(identification number
E1215N12C1 Rev C), containing the 73S1209F with the preloaded turnkey program PCCID.
•12 VDC/1,000 mA universal wall transformer with 2.1 mm plug ID (CUI Inc. – EPAS-101W-12).
•Serial cable: DB9, male/female, 2 meter length (Digi-Key AE1379-ND).
•CD containing documentation (data sheet, and user guides), Software API libraries, evaluation code,
and utilities.
1.2 Evaluation Board Features
The 73S1209F Evaluation Board (see Figure 1) includes the following:
•RS-232 interface
•Dual smart card interface
•ICE/Programmer interface
•2 line x 16 character LCDmodule
•6 x 5 Keypad
•2 LEDs
1.3 Recommended Equipment and Test Tools
The following equipment and tools (not provided) are recommended for use with the 73S1209F
Evaluation Kit:
•For functional evaluation: PC with Microsoft®Windows®XP or Vista®.
•For software development (MPU code)
Signum™ ICE (In Circuit Emulator): ADM-51. Refer to
http://signum.temp.veriohosting.com/Signum.htm.
Keil™ 8051 C Compiler Kit: CA51. Refer to http://www.keil.com/c51/ca51kit.htm and
http://www.keil.com/product/sales.htm

73S1209F Evaluation Board User Guide UG_1209F_034
6 Rev. 1.3
2 Evaluation Board Setup
Figure 2shows the basic connections of the evaluation board with the external equipment.
The power supply can come from two sources:
•A regulated lab power supply connected to the banana plugs J2, J3 and J5. In this case, the board
main switch S1 has no effect.
•Any AC-DC converter block (default), able to generate a DC power supply of 7 V min / 12 V max /
400 mA. In this case, the board main switch S1 connects or disconnects the supply to the board.
The communication with an external host is accommodated via a standard RS-232 serial interface
(TX/RX only).
The board is loaded by default with the PCCID application. It requires a PC to be connected through its
serial port. When powered-up, the board is able to run with the PC Exerciser host application. Refer to
the 73S1209F Evaluation Board Quick Start Guide to setup and run the PCCID application.
Figure 2: 73S1209F Evaluation Board Basic Connections
RS232
DB9 Cable
+7 V to +12 V
400 mA
Power Supply:
1) Lab DC dual (3.3 V,
5 V) supply
or
2) Non-regulated DC
Block
1
2
+2.7 V to
+3.6 V
400 mA
+4.0 V to
+6.5 V
400 mA

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 7
2.1 Connecting the Evaluation Board with an Emulation Tool
The 73S1209F Evaluation Board has been designed to operate with an In-Circuit-Emulator (ICE) from
Signum Systems (model ADM-51). Figure 3shows the connections between the ICE and the evaluation
board. The Signum System POD has a ribbon cable that must be directly attached to connector J11.
Signum Systems offers different POD options depending on user needs. The standard pod allows users
to perform typical emulator functions such as symbolic debugging, in-line breakpoints, memory
examination/modification, etc. Other pod options enable code trace capability and/or complex
breakpoints at an additional cost.
Figure 3: 73S1209F Evaluation Board Basic Connections with ADM-51 ICE

73S1209F Evaluation Board User Guide UG_1209F_034
8 Rev. 1.3
2.2 Loading User Code into the Evaluation Board
Hardware Interface for Programming
The signals listed in Table 1are necessary for communication between the TFP2 or ICE and the
73S1209F.
Table 1: Flash Programming Interface Signals
Signal Direction Function
E_TCLK Output from 73S1209F Data clock
E_RXTX Bi-directional Data input/output
E_RST
1
Bi-directional Flash Downloader Reset (active low)
1
The E_RST signal should only be driven by the TFP2 when enabling these
interface signals. The TFP2 must release E_RST at all other times.
These signals, along with 3.3 V and GND are available on the emulator header J11. Production modules
may be equipped with much simpler programming connectors, e.g. a 5x1 header.
Programming of the flash memory requires either the Signum Systems ADM51 in-circuit emulator or the
TSC Flash Programmer Model TFP2 provided by Teridian.
Loading Code with the In-Circuit Emulator
If firmware exists in the 73S1209F flash memory, the memory must be erased before loading a new file
into memory. In order to erase the flash memory, the RESET button in the emulator software must be
clicked followed by the ERASE button (see Figure 4).
Once the flash memory is erased, the new file can be loaded using the Load command in the File menu.
The dialog boxshown in Figure 5makes it possible to select the file to be loaded by clicking the Browse
button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC.
At this point, the emulator probe (cable) can be removed. Once the 73S1209F device is reset using the
reset button on the evaluation board, the new code starts executing.
Loading Code with the TSC Flash Programmer Model TFP2
Follow the instructions given in the TSC Flash Programmer Model TFP2 User's Manual.

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 9
Figure 4: Emulator Window Showing RESET and ERASE Buttons
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu
RESET
BUTTON
ERASE
BUTTON

73S1209F Evaluation Board User Guide UG_1209F_034
10 Rev. 1.3
3 Using the PCCID Application
The PCCID firmware is pre-installed on the 73S1209F Evaluation Board. It requires a PC with the serial
RS-232 port. When powered-up, the board is able to run the PCCID demonstration host application which
allows:
•Smart card activation and deactivation, in ISO or EMV mode.
•Smart card APDU commands to be exchanged with the smart card inserted in the board.
•Starting a test sequence in order to test and evaluate the board performance against an EMV test
environment.
3.1 Host Demonstration Software Installation
Installation on Windows XP
Follow these steps to install the software on a PC running Windows XP:
•Extract “PCCID Vz.zz Release.zip” (where z.zz is the latest version of the firmware release).
oCreate an install directory. For example: “C:\TSC\”.
oUnzip “PCCID Vz.zz Release.zip” to the just created folder. All applications and documentation
needed to run the board with a Windows PC will be loaded to this folder.
•Plug the supplied adapter into the 5V DC jack and a wall outlet.
•Connect the serial cable between the host system and the 73S1209F Evaluation Board.
•Press the ON/OFF switch to turn the board on.
•Run “TSCP-CCID.exe” (located in the path - x:\yyy\ PCCID Vz.zz Release\Host
Applications\Windows App\App\Bin\Release) on the host system to execute the host demonstration
application (where xrefers to the drive, yyy refers to the directory the installation .zip file was
expanded to and z.zz is the latest version of the firmware release).
At this point the application window should appear. For additional information regarding the use of the
Teridian Host application, refer to the Pseudo-CCID Host GUI Users Guide (UG_12xxF_037).

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 11
4 Evaluation Board Hardware Description
4.1 Jumpers, Switches and Modules
Table 2 describes the73S1209F Evaluation Board jumpers, switches and modules. The Item # in Table 2
references Figure 6.The default setting refers to setup for running USB-CCID application.
Table 2: Evaluation Board Jumper, Switch and Module Description
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
1 J2, J3, J5 No
Connect Banana plugs for
external regulated
power supply
Must be used to connect an external regulated
power supply. These inputs are intended to allow
control of the input supply voltage of the board
(e.g. different than 5.0 V and 3.3 V on-board
regulators).
JP5 must be in position “5V EXT” and JP1 must be
in position “5V ”when using this 5 V power supply
input. JP6 must be in position “EXT” ”when using
this 3.3 V power supply input.
The evaluation board is sensitive to the polarity:
One red plug is +3.3 V nominal and the other red plug is +5.0 V. Theblack plug is ground. The
voltage supply input should be in the range +2.7 V to +3.6 V and 4.75 V to 5.5 V respectively.
2 JP4 Inserted VDD jumper In normal use, a jumper must be inserted in this
header, to connect the +3.3 V power supply of the
board to the VDD pins of the 73S1209F. This
jumpercan be replaced by a µA / mA-meter to
measure the actual current drawn by the 73S1209F.
3 JP3 Inserted 3.3 V jumper In normal use, a jumper must be inserted in this
header, to connect the +3.3 V power supply of the
RS-232 transceiver and the 73S8010R. This
jumper can be removed to minimize power
consumption if these devices are not used.
4 JP6 ‘INT’ Jumper:
power supply selection
(#1)
A jumper must be inserted to select one of the
following settings:
•In position “EXT”, the evaluation board 3.3 V is
supplied from the external power supply inputs
(banana plug J3). In this case, the voltage must
be externally regulated
•In position “INT”, the evaluation board is
powered from the 3.3 V voltage regulator U1.
The regulator can be powered either from the
USB bus power supply (USB-powered
application), or from an external non-regulated
power supply (connector PJ1).
. The power supply line is
directly applied to the board power supply. This
external power supply must not exceed 3.6 V.
5 S1 Main switch This switch turns the power On / Off to the
evaluation board, when the jumper JP1 is in
position “VOUT”. When using a lab regulated
power supply connected to the bananaplugs J2
and J3, this switch has no effect.

73S1209F Evaluation Board User Guide UG_1209F_034
12 Rev. 1.3
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
6 PJ1 Connect DC jack Plug to connect an external DC block. Must be
used in conjunction with appropriate settings of
S1, JP1 and JP6 (see details above).
Power supply features are:
Voltage: 7 V min; 12 V max
Current: 400 mA
7 J11 No
Connect In-Circuit Emulator connector This connector must be used when using an external In-Circuit Emulator (SIGNUM 8052 ADM51 ICE).
Refer to the Electrical Schematic for pin assignment.
8 JP20 Not
Inserted Jumper:
analog in Jumper will select between the VBUS or analog in test point for the analog input. Using VBUS on the
analog input will free up the USR7 interrupt for
other uses. The analog input can be set up to use
the compare to detect when the USB cable is
inserted/removed.
9 P1 No
Connect DB9 RS232 female socket This socket allows connection of an RS232 cable to a computer. Use a crossed wires (RX/TX)
cable. The evaluation board has an on-board
level shifter (U7) to allow direct connection to a
computer.
Connection o
f a RS232 link is required when using
the
pre-downloaded application.
10 D2, D3, D4,
D5 LEDs:
Serial link activity and
four dedicated LED
pins.
These LEDs (D2, D3) reflect the activity on the
serial link (RS232 or serial), and the others are
used for general purpose indicators without the
need for current limiting resistors.
•D2 reflects the activity on the RX line (Data
going TO the 73S1209F)
•D3 reflects the activity on the TX line (Data
coming FROM the 73S1209F)
•D4 to D5 are the LED0-LED1 output pins .
11 U5 LCD Module On-board LCD module:
•2 lines of 16 characters, each character dot
matrix is 5x7.
•Includes an embedded Hitachi HD44780 LCD
driver, controlled from the on-board 73S1209F
USR interface.
12 RV1 Adjustable resistor to
adjust LCD brightness Can be used to adjust the brightness of the on- board LCD module.
13 S2 to S31 On-board keypad 5x6 keyboard directly connected to the on-board
73S1209F IC. The assignment of the keys, as
silk-printed on the PCB is the one supported by
the TSC Application Programming Interface.
14 – Board reference and
serial number Should be mentioned in any communication with TSC Application Engineers when requesting
support.

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 13
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
15 JP2 Inserted Jumper VPC In normal use, a jumper must be inserted in this
header to connect the +5.0 V power supply of the
board to theVPC pins of the 73S1209F. This
jumper can be replaced by a µA / mA-meter to
measure the actual current drawn by the
73S1209F.
16 – Breadboard area This breadboard area allows engineers to add
their own circuitry / connection of peripherals,
when prototyping and developing a 73S1209F
based application. User I/Os, GPIOs, interrupt
pins and power supply pins are located close to
this area to allow easy connection.
17 JP16,
JP17 Inserted Jumper: LED pins In normal use, a jumper must be inserted in this
header, to connect the LEDs to the LED pins of
the 73S1209F. This jumper can be replaced by a
µA / mA-meter to measure the actual current
drawn by the LED outputs of the 73S1209F.
18 JP12 Inserted Jumper: 73S8010R
VPC connect Insertion of the jumper will provide 5.0 V to the
73S8010R VPC pin. If the 73S8010Ris not used,
the jumper can be removed.
19 JP13 Not
Inserted Jumper: USR7/SDA
select This jumper selects which signal is connected to the daughter board connector pin USR7:
•In position “USR7”, the 73S1209F USR7 signal
is connected to the daughter card pin USR7.
•In position “SDA”, the I2C SDA signal is
connected to the daughter card pin USR7. This
allows the SDA line to connect to an SDA pin
on a 73S8010R daughter card.
20 JP14 Not
Inserted Jumper: USR5/AUX2
select This jumper allows the on board 73S8010 AUX2 pin to be connected to USR5 if needed. If not
needed the jumper should be removed.
21 U4 On board 73S8010R The board contains a built-in 73S8010R that is
connected to the external smart card interface of
the 73S1209F. If not used, this device can be
disconnected from the 73S1209F by removing
jumpers JP12 and JP21.
22 JP21 Inserted Jumper: 73S8010R
interrupt This jumper will allow the on-board 73S8010 interrupt output to connect to INT2 on the
73S1209F. Remove this jumper if the on-board
73S8010 is not used.
23 J7,J8 Not
Inserted Optional 73S80xxX
Daughter Board
interface
When developing applications that require more
than 2 smart card interfaces, an optional daughter
board can be populated to use the 73S1209F
external smart card interface (lines SCIO and SCK),
in conjunction with the USR(0:7) port and the INT2
interrupt input of the 73S1209F). Refer to the
Electrical Schematic for pin assignment.

73S1209F Evaluation Board User Guide UG_1209F_034
14 Rev. 1.3
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
24 J9, J10 SIM / SAM and Smart
Card connectors –
external interface (#2)
Allows the evaluation board to communicate with a
smart card using either the standard (credit card
size) or SIM/SAM format. This slot is connected to
the 73S1209F external card interface # 2.
Note that J10 is wired is parallel to the smart card
connector J9 (underneath the PCB). Both
connectors cannot be populated at the same time.
25
JP11 Not Inserted Jumper: USR6/SCL
select This jumper selects which signal is connected to the daughter board connector pin USR6:
•In position “USR6”, the 73S1209F USR6 signal
is connected to the daughter card pin USR6.
•In position “SCL”, the I2C SCL signal is
connected to the daughter card pin USR6. This
allows the SCL line to connect to an SCL pin on
a 73S8010R daughter card.
26 JP10 Not
Inserted Jumper: USR6/AUX1
select This jumper allows the on board 73S8010 AUX1 pin to be connected to USR6 if needed. If not
needed the jumper should be removed.
27 JP8 ‘Active
High’ Jumper: Selection of the
polarity of the card
detection switches of
internal smart card
connector
On-board smart card connectors and SIM/SAM
connectors are equipped with card presence
switches, normally open when no card is inserted.
When the switches are closed (card inserted), the
polarity must be selected by a jumper on JP8:
•In position “ACTIVE HIGH”, the card detection
switches connect +3.3 V to the card detection
inputs of the 73S1209F.
•In position “ACTIVE LOW”, the card detection
switches connect ground to the card detection
inputs of the 73S1209F.
The 73S1209F firmware can handle both polarities
for card detection. Therefore, this setting is
firmware dependent. The default firmware
settings are JP8 = ACTIVE HIGH and JP7 =
PRES.
28 S27 Reset button Evaluation board main reset: Asserts a hardware
reset to the on-board 73S1209F IC.
29 JP7 ‘PRES’ Jumper: Selection of
the PRES and PRESB
inputs
Selects the card detect input PRES or PRESB.
PRES is the active high input and PRESB is the
active low input.
See item 29 for more detail.
30 JP15 ‘GND’ Jumper: security fuse
control This jumper should be removed at all times. Connecting the jumper will allow the security fuses
to be blown under firmware control. Refer to the
73S1209F Data Sheet for further information
about the security fuse.

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 15
TERIDIAN
123
4
5
6
7
8
910 11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
30
32
29
31
33
34
35
25
Figure 6: 73S1209F Evaluation Board Jumper, Switch and Module Locations

73S1209F Evaluation Board User’s Guide UG_1209F_034
16 Rev. 1.3
4.2 Test Points
The test point numbers listed in Table 3refer to the test point numbers shown in the electrical schematic
and in the silkscreen of the PCB.
Table 3: Evaluation Board Test Point Description
Test
Point # Name Use
TP2, TP3 +3.3V +3.3 V main board power supply, coming from the internal or external
source, as defined from the jumpers JP3 and JP6. TP3 and TP4 are close
to the breadboard area for easy wiring of the power supply.
TP6
TP7 VDD VPC 2-pin test point, with one ground and one VDD signal directly connected to
the 73S1209F and its decoupling capacitors. Can be used to measure the
integrity of the digital power supply of the 73S1209F, or to add a decoupling
capacitor.
TP8 +5V +5 V coming from the external DC block (connected to JP5), as selected
with jumper on JP1. Can be used to test voltage presence.
TP9 +3.3VFIX +3.3 V coming from the on-board regulator (powered up from the external
DC block). Can be used to test voltage presence.
TP10 Smart Card
Contacts –
Interface #1
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC1, RST1, CLK1, C81 and C41. Each contact
has its own ground pin on the header.
TP11 to
TP17 GND Ground test points. Can be used for grounding of lab equipment probes.
TP18 Card Detect –
Interface #1 Card detect signal coming directly from the card connectors.
TP21 USR(7:0) Standard 8-bit user I/O port of the 73S1209F.
Some of the user I/Os are shared by the extension 73S80xx daughter
board and theLCD interface. Only one should be used at a time.
TP22 USB – N/A TP22 is not populated with the 73S1209F.
TP24 VBUS – N/A TP24 is not populated with the 73S1209F.
TP25 Smart Card
Contacts –
Interface #2
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC2, RST2, CLK2, C42 and C82. Each contact
has its own ground pin on the header.
TP26 INT3 Interrupt input #3 secondary test points.
TP27 ROW[0:5] The row pins used for the keypad interface.
TP28 LED0-1 The LED outputs from the 73S1209F. (LED2 and LED3 are N/C on the
73S1209F)
TP29 COL[0:4] The column pins used for the keypad interface.
TP30 INT2-3 Interrupt input #2 and #3 of the 73S1209F. This header is close to the
breadboard area for easy wiring.
TP31 RX, TX The TX and RX serial UART I/O signals (3.3 V digital logic level).
TP32 ANALOG IN Analog input test point. Analog voltage can be connected to this test point
for voltage comparison.
TP34 CPUCLK
This pin outputs the oscillator clock of the 73S1209F device. Can be used
as a clock source for any purpose.

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 17
4.3 Schematic
1 2
3
4 5
6 7
8
9 10
11 12
13
14 15
16
17 18
19 20
J12 PROTO TYPE AREA
TP6(VDD), TP9(VPC) and
decoupling capacitors should
be located close to U6.
(BLK)
+3.3VDC
USR4
5V
R8
10
Y1
12.000MHz
12
S27
SW
1
GND
3.3V
C4
GND
OSC_IN_12 OSC_IN_32 OSC_OUT_32
OSC_OUT_12
USR5
OSC_IN_12
OSC_OUT_12
1
2
3
4
TP28
HEADER 4
GND
GND
CLK
OSC_IN_32
OSC_OUT_32
1
2
3
4
5
6
7
8
9
TP21
HEADER 9
CLR
USR5
0
F1
VCC
1
G5
USR6/SCL
Layout TP10 & TP25 as 8x2 header and TP23 and TP26 as 4x2 header.
Populate 2pin header to every other rows such as pin1-2, pin5-6,
pin9-10 and pin13-14 for TP10 and TP25.
2
GND
UP
Y
GND
ROW2
COL4
COL2
COL1
COL3
COL0
R28 0
RST_EMUL
C30
0.1uF
1215
1200
DNIINSTALL
DEVICE
USR8
ROW3
1
2
3
4
5
6
TP27
HEADER 6
R34
1M
+
C29
1uF
1
G6
SIO
1
2
TP31
RXD
RXD
TXD
TXD
SCLK
C39
20 pF
VPC
DNI
J3
Banana
D4
LED
LED0
ROW4
LED2
D5
LED
D6
LED
LED1
1
2
3
JP15
HEADER 3_0
C18
1uF
USR7
D7
LED LED3
LED3
+C27
10uF
R29 0
12
34
TP22
HEADER 2X2
1
2
3
4
5
6
7
8
9
10
J7
TSM_110_01_L_SV
C37
1000pF
3.3V
11
22
33
PJ1
+5VDC
LED0
3.3V
LED2
LED1
INT3
SEC
TXD
ANALOG IN
LCD
BRIGHTNESS
ADJUST
LED0
1
LED2
2
LED1
3
LED3
4
SCL
5
SDA
6
X32OUT
7
X32IN
8
GND
9
X12IN
10
X12OUT
11
COL0
12
COL1
13
COL2
14
ANAIN
15
COL3
16
RXD
17
TXD
18
COL4
19
USR7
20
ROW0
21
ROW1
22
USR6
23
ROW2
24
GND
25
DP
26
DM
27
VDD
28
USR5
29
USR4
30
USR3
31
USR8
32
USR2
33
ROW3
34
USR1 35
USR0 36
ROW4 37
ROW5 38
CPUCLK 39
ERST 40
TCLK 41
VDD 42
TBUS3 43
GND 44
RXTX 45
NC 46
TBUS2 47
SCLK 48
TBUS1 49
SIO 50
INT3 51
INT2 52
TBUS0 53
TEST 54
SCPWRDN/VPC 55
RDY/PRESB 56
CLKIN/CLK 57
RST/GND 58
CMDVCC3B/RST 59
CMDVCC5B/VCC 60
C8/AUX2 61
C4/AUX1 62
I/O / I/O 63
DETCARD/PRES 64
VDD 65
RESET 66
SEC 67
ISBR 68
U6
1200/15
1
2
3JP13
1
2
3
JP11
OPTIONAL LCD DISPLAY SYSTEM
16 CHARACTER BY 2 LINES
SCL
SDA
SCL
SDA
R16
10K R17
3K
R15
10K
S1
POWER_SWITCH
3.3V
1
2
TP7
1
6
2
7
3
8
4
9
5
P1
DB9_RS232
C43
1000pF
C33
0.1uF
TBUS[1]
ISYNC/BRKRQ
RXTX
1 2
3
JP1
R30 0
21
1
TP2
Y2
32.768kHz
C32
0.1uF
C35
0.1uF
1
TP3
5V
C34
0.1uF
3
C1
1
C2
2
C3
3
C5
4
C6
5
C7
6
SW1
7
SW2
8
J1
SIM/SAM Connec tor
VPC
Matches up to
daughter board
C31
0.1uF
C16
1uF
1
2JP3
HEADER 2
3.3V
1
TP8
1
G7
1 2
34
5 6
78
910
11 12
TP25
HEADER 2 x 4
3.3V
ROW0
USR8
LED2
LED0
LED1
LED3
1
2
TP6
VDD
5V
R31 0
D- 2
D+ 3
GND 4
VCC 1
GND 5
GND 6
J6
USB_CONN_4
VDD
C22
22pF
3.3V
C3
0.1uF
C4
0.1uF
C9
0.1uF
ROW5
C5
0.1uF
VDD
ROW4
1
2JP4
HEADER 2
+C2
10uF
+C7
10uF
Area of copper pattern
for U1 Vout should be
larger than 0.3 in2.
1
2
JP12
HEADER 2
C8
0.1uF
C38
20 pF
1 2
34
5 6
78
910
11 12
TP10
HEADER 2 x 4
C1
1
C2
2
C3
3
C5
4
C6
5
C7
6
SW1
7
SW2
8
J10
SIM/SAM Connec tor
1
TP9
1 2
JP2
HEADER 2
1
TP18
SEC
1
G8
VO
3VDD
2
DB0
7
NC
15
GND
1
RS
4
R/W*
5
E
6
DB7
14 DB6
13 DB5
12 DB4
11 DB3
10 DB2
9DB1
8
U5
MDL-16265
TXD
RXD
1
2
JP18 HEADER 2
1 2
JP19 HEADER 2
ROW3
1 2
JP16 HEADER 2
1
2
JP17 HEADER 2
ROW2
ROW1
ROW0
COL4
R2 24
COL3
3.3V
USR7
USR2
1
23
45
67
89
10 11
12 13
14 15
16 17
18 19
20
J11
Emulator IF
USR0
USR1
USR3
GND.
1
Vin
3Vout
4
U1 LM1117DT-5.0
USR5
USR4
USR6
SAD0
1
SAD1
2
SAD2
3
GND
4
N/C
5
VPC
6
N/C
7
AU X2
12
N/C
8
N/C
9
PRES
10
I/O
11
AU X1
13
GND
14 CLK 15
RST 16
VCC 17
VDD_ADJ 18
SCL 19
SDA 20
VDD 21
GND 22
INT 23
AUX2UC 28
AUX1UC 27
XTALOUT 25
XTALI N 24
I/OUC 26
73S8010R
U4
COL2
VBUS_MON
COL1
R32 0
COL0
USR6
1
2
TP30
INT2
INT3
TCLK
3.3V
1 2
JP10 HEADER 2
1 2
JP14 HEADER 2
VBUS
1
TP35
ROW5
1
G9
VDD
1
2
3
JP8
1
2
3
JP7
CARD #1 DETECT
POLARITY SELECT
ACTIVE LOW
C1+ 28
C1- 25
C2+ 1
C2- 3
T1IN 24
T2IN 23
T3IN 22
T4IN 19
T5IN 17
R1OUTBF 16
R1OUT 21
R2OUT 20
R3OUT 18
GND
2MBAUD
15
SHDNB
14 ENB
13 R3IN
11 R2IN
9R1IN
8
T1OU T
5
T2OU T
6
T3OU T
7
T4OU T
10
T5OU T
12
V-
4
V+
27
VCC 26
U7
MAX3237CAI
ACTIVE HIGH
R4 100k
R13
3k
R12
3k
R11 62
1
G1
R19 62
R18 62
R14 62
3.3V
R20 62
R21 62
R23 62
13
S2
SW_MOM
R22 62
ANALOG SELECT
USR1
USR4
USR2
USR5
USR3
USR0
R33 0
USR6
VDD
VDD
C20 27p
VPC
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
J9
Smart Card Connector
C41
20 pF
C15
27p
C21
27p
SDA
SCL
3.3V
GND
C17
0.1uF R5
200k
+
C1
10uF
R24 0
1
2
3
JP6
1 3
S3
SW_MOM
1
TP11
13
S4
SW_MOM
CARD DET
13
S5
SW_MOM
1
2
JP21
HEADER 2
C28
C40
20 pF
13
S6
SW_MOM
+C12
10uF
C42
20 pF
C28
U3, C19
Note: For u5 configure board according to the
following table.
R3 24
C14 27p
3.3V
R25 0
OPEN
SW1
CLOSED
CLK
1
TP12
USR7
USR7/SDA
AU X1
AU X2
AU X1
AU X2
VBUS_MON
R10
10k
J2
Banana
(RED)
1
2
3
JP5
+5.0VDC
1 3
S7
SW_MOM
1
TP13
13
S12
SW_MOM
+7 to +15
VDC UnReg
5V
1 3
S17
SW_MOM
13
S22
SW_MOM
1 3
S28
SW_MOM
1 3
S8
SW_MOM
5V
13
S13
SW_MOM
13
S18
SW_MOM
1 3
S23
SW_MOM
1 3
S29
SW_MOM
1
TP14
PRES
1 3
S9
SW_MOM
1 3
S14
SW_MOM
PRES
13
S19
SW_MOM
1
SY M1
Logo
13
S24
SW_MOM
13
S30
SW_MOM
13
S10
SW_MOM
1 3
S15
SW_MOM
13
S20
SW_MOM
1
TP15
1
2
JP23
HEADER 2
1 3
S25
SW_MOM
1 3
S31
SW_MOM
13
S16
SW_MOM
13
S11
SW_MOM
1 3
S21
SW_MOM
R26 0
13
S26
SW_MOM
13
S32
SW_MOM
VPC
+5VDC
Reg
1
TP16
GND
Unpopulated & unlabled
RESET
INT2
D
+3.3V
VPC
GND
USR7
C
GND
SERIAL
PORT
USR0
USR1
USR2
12
D1
MBR0520L
1
TP17
RST
USR4
USR5
USR3
USR6
1
TP34
CPUCLK
AU X2
GND
5V
GND
SIO
AU X1
INT2
5V
SCLK
.
GND
F2
+3.3V
1
2
3
4
5
6
7
8
9
10
J8
TSM_110_01_L_SV
EXTERNAL POWER
SUPPLY
INT3
GND
INTERNAL
SUPPLY
/
TBUS[0]
C4
C23
22pF
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
J4
Smart Card Connector
C24
22pF
C25
22pF
+3.3V
1
G2
GND
GND
3
GND
V_IN
1
GND
2
ON/OFF
3
BYPASS 4
V_OUT 5
U2
LP2985
7
INT2
EXTERNAL
SUPPLY
B
C8
30-SWITCH
KEYPAD
USR1
USR2
GND
IO
1
2 3
JP20
J5
Banana
SCLK
GND
USR7
CARD # 2 DETECT
POLARITY SELECT
SC I/F EXPANSION
USR6
F3
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
TBUS[2]
USR5
USR4
TBUS[3]
C14, C15, C16, C18,
C20 and C21 should be
located close to the
Smart Card Connector
USR3
ENTER
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
Place R11, R14, R18,
R19, R20, R21, R22
and R23 close to U6
SIO
ROW1
+5V
Z
VDD
4
C19
0.1uF
SMARTCARD
SLOT #1
SC4
C11
2.2uF
COL3
COL1 COL2
COL0
U3, C19
+5V
MOUNT HOLES FOR STAND OFFS TERIDIAN LOGO
8
R6 0
ERXD
VDD
1
TP32
R1 0
+5V SOURCE
SELECT
1
G3
R7 470
R9 470
SC8
RXD
USR0
1
TP24
VBUS
DPLUS
TXD
DMINUS
ON/CE
3.3V
+
C10
4.7uF
COL4
GND
D2
LED
VDD
5
D+ USR0
VCC tracks should be
wider than 0.5mm.
D3
LED
DNIDNIDNI
DNI
SMARTCARD
SLOT #2
+5VDC EXT
GND
USR1
C28
0.1uF
F
+C6
10uF
USR8
+3.3VFIX
CS
1
RESET
2
N/C
3
0FF
4
I/OUC
5
AUX1UC
6
AUX2UC
7
RDY
12
CMDVCC5
8
CMDVCC3
9
RSTIN
10
CLKIN
11
PWRDN
13
TEST
14 VPC 15
PRES 16
N/C 17
N/C 18
CLK 19
GND 20
RST 21
VCC 22
AU X2 23
VDD 28
GND 27
I/O 25
AU X1 24
PRES 26
U3
73S8009R
W
USR1
USB_5V
D-
C13
0.01uF
USR2
+5V
DMINUS
DPLUS
6
USR2
USR5
D-
INT2
USR0
USR3
STATUS INDICATOR
1
G4
X
9
GND
1
TP26
USR3
+5VDC
VCC
IO
1
2
3
4
5
TP29
HEADER 5
ROW5
ROW3
ROW2
ROW0
C8
ROW1
ROW4
C26
0.1uF
(RED)
GND
USR4
DOWN
A
RST
D+
These test pins should be located between two rows (4 pads each)
of SC connector and signal pins locate within 5mm from pads.
CLK track should be routed away from RST and C4.
13
2
CW
RV1
10K
C11 and C10 to
be placed within
1cm of U2
R27 0
Figure 7: 73S1209F Evaluation Board Electrical Schematic

73S1209F Evaluation Board User Guide UG_1209F_034
18 Rev. 1.3
4.4 PCB Layouts
Figure 8: 73S1209F Evaluation Board Top View (Silkscreen)

UG_1209F_034 73S1209F Evaluation Board User Guide
Rev. 1.3 19
Figure 9: 73S1209F Evaluation Board Bottom View (Silkscreen)

73S1209F Evaluation Board User Guide UG_1209F_034
20 Rev. 1.3
Figure 10: 73S1209F Evaluation Board Top Signal Layer