Teridian 73S8024C User manual

Simplifying System Integration
TM
73S8024C
Demo Board User Manual
November 11, 2009
Rev. 1.3
UM_8024C_061

73S8024C Demo Board User Manual UM_8024C_061
2 Rev. 1.3
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL [phone], FAX [phone], http://www.teridian.com

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 3
Table of Contents
1Introduction ...................................................................................................................................5
1.1 Package Contents....................................................................................................................5
1.2 Safety and ESD Notes.............................................................................................................5
2Basic Connections ........................................................................................................................6
3Hardware Description....................................................................................................................7
3.1 Demo Board Connectors, Jumpers and Test Points .................................................................7
3.2 Recommended Operating Conditions and Absolute Maximum Ratings.....................................9
3.373S8024C Pin Description.......................................................................................................9
3.4 73S8024C Pinout..................................................................................................................11
4Design Considerations................................................................................................................12
4.1 General Layout Rules ............................................................................................................12
4.2 Optimization for Compliance with EMV and NDS....................................................................12
573S8024C Demo Board Schematics, PCB Layouts and Bill of Materials..................................13
5.1 Schematic..............................................................................................................................13
5.2 Bill of Materials ......................................................................................................................14
5.3 PCB Layouts..........................................................................................................................15
6Ordering Information...................................................................................................................18
7Related Documentation...............................................................................................................18
8Contact Information.....................................................................................................................18
Revision History..................................................................................................................................19

73S8024C Demo Board User Manual UM_8024C_061
4 Rev. 1.3
Figures
Figure 1: 73S8024C Demo Board............................................................................................................5
Figure 2: 73S8024C Demo Board Basic Connections..............................................................................6
Figure 3: 73S8024C Demo Board Connectors, Jumpers and Test Points.................................................8
Figure 4: 73S8024C SO28 Pinout (Top View)........................................................................................11
Figure 5: 73S8024C Demo Board Electrical Schematic..........................................................................13
Figure 6: 73S8024C Demo Board Top View...........................................................................................15
Figure 7: 73S8024C Demo Board Bottom View......................................................................................15
Figure 8: 73S8024C Demo Board Top Signal Layer...............................................................................16
Figure 9: 73S8024C Demo Board Middle Layer 1, Ground Plane...........................................................16
Figure 10: 73S8024C Middle Layer 2, Supply Plane ..............................................................................17
Figure 11: 73S8024C Demo Board Bottom Signal Layer........................................................................17
Tables
Table 1: 73S8024C Demo Board Connector, Jumper and Test Points......................................................7
Table 2: Recommended Operating Conditions.........................................................................................9
Table 3: Absolute Maximum Ratings........................................................................................................9
Table 4: 73S8024C Card Interface Pins...................................................................................................9
Table 5: 73S8024C Miscellaneous Pins.................................................................................................10
Table 6: 73S8024C Power and Ground Pins..........................................................................................10
Table 7: 72S8024C Microcontroller Interface Pins..................................................................................10
Table 8: 73S8024C Demo Board Bill of Materials...................................................................................14
Table 9: Order Numbers and Packaging Marks......................................................................................18

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 5
1 Introduction
The 73S8024C Demo Board is a platform for evaluating the Teridian 73S8024C Smart Card Interface
device. The board incorporates the 73S8024C integrated circuit and has been designed to operate either
as a standalone platform (to be used in conjunction with an external microcontroller) or as a daughter
card to be used in conjunction with the 73S1121F evaluation platform.
The board has been designed to comply with the EMV 2000 Specification, Version 4.0. 73S8024C Demo
Boards can easily be modified to comply with NDS specifications by replacing a few external components
that are highlighted in this document.
Figure 1: 73S8024C Demo Board
1.1 Package Contents
The 73S8024C Demo Board Kit includes:
•A 73S8024C Demo Board
•The following documents on CD:
•73S8024C Data Sheet
•73S8024C Demo Board User Manual (this document)
•Application Note
1.2 Safety and ESD Notes
Extreme caution should be taken when handling the 73S8024C Demo Board after
connection to live voltages!
The 73S8024C Demo Board is ESD sensitive! ESD precautions should be taken when
handling this board!

73S8024C Demo Board User Manual UM_8024C_061
6 Rev. 1.3
2 Basic Connections
The basic connections to the demo board are described below and shown in Figure 2.
1. Connect power supply: Apply 3.3 V to pin 10 of J4.
2. Control signals to the device can be connected through J2 and J4 (see Figure 2 and the Electrical
Schematic, Figure 5).
3. To set the clock frequency with an external clock source:
•Set JP1 to the SCLK setting.
•Apply clock source to pin 1 of J2.
•Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows:
CLKDIV1 = CLKDIV2 = 0 clock frequency = SCLK/8
CLKDIV1 = 0, CLKDIV2 =1 clock frequency = SCLK/4
CLKDIV1 = 1, CLKDIV2 =0 clock frequency = SCLK
CLKDIV1 = CLKDIV2 = 1 clock frequency = SCLK/2
4. To set the clock frequency using crystal Y1:
•The crystal included on the demo board is 12 MHz.
•Set JP1 to XTAL position.
•Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows:
CLKDIV1 = CLKDIV2 = 0 clock frequency = 1.5 MHz
CLKDIV1 = 0, CLKDIV2 =1 clock frequency = 3 MHz
CLKDIV1 = 1, CLKDIV2 =0 clock frequency = 12 MHz
CLKDIV1 = CLKDIV2 = 1 clock frequency = 6 MHz
Figure 2: 73S8024C Demo Board Basic Connections
1
2
CKDIV2
CKDIV1
RSTIN
CMDVCC
GND
VDD
PWRDN
5V/#V
GND
SCLK
OFF
I/OUC
AUX1UC
AUX2UC
External clock source. JP1 must be in
position SCLK when using an
external clock. Otherwise, pin SCLK
can be left open.
V
PC
Power
Supply:
Configure JP2
to 3.3V
V
DD
Power Supply:
+2.7V to +3.6V
(3.3V Typ.) / 50mA
Note: CLKSTOP and CLKLEV
can be left NC if unused.
5V/#V too, for 5V cards only.

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 7
3 Hardware Description
3.1 Demo Board Connectors, Jumpers and Test Points
Table 1 describes the73S8024C Demo Board connectors, jumpers and test points. The Item # in Table 1
refers to Figure 3.
Table 1: 73S8024C Demo Board Connector, Jumper and Test Points
Item
#
Schematic/
Silkscreen
Reference Name Function
Connectors:
1 J2 5V Board Supply /
Auxiliary Interface 73S8024C auxiliary interface (I/OUC, AUX1UC,
AUX2UC), external clock (SCLK) and interrupt (OFF)
pins. The external clock (SCLK) can be left open when
JP1 is in position XTAL.
The 5V power supply is unused and must be left open
and JP2 must be inserted in position 3.3V.
9 J4 3.3V Board Power /
Digital Control
Signals
3.3V board power supply and the 73S8024C host
control signals RSTIN, CMDVCC, 5V/#V, PWRDWN,
CLKDIV2 and CLKDIV1.
16 J5 Smart Card
Connector Smart card connector.
When inserting a card (credit card size format), contacts
must face up.
11 J6 Smart Card
Connector SIM/SAM smart card format connector.
J6 is wired in parallel to the smart card connector J5
(underneath the PCB). No SIM/SAM should be inserted
when using the credit-card size connector J5.
Jumpers:
3 JP1 Clock Selection Jumper to select between a crystal or an external clock
as the frequency reference to the device. The default
setting is for a crystal.
17 JP2 VPC Select Jumper to select the value of the power supply for the
smart card DC-DC converter (73S8024C input VPC).
To support both card voltages, JP2 must be set to
position 3.3V. The default setting is 3.3V.
2 JP3 VDD Select Jumper to select the digital voltage which supplies the
73S8024C. Must be set for 3.3V.
8 JP4 – Not used.
15
14 JP5 JP6 Card Polarity
Detect Select The setting of JP5 and JP6 depends on the type of smart card connector used (nominally open or closed)
and which 73S8024C card presence switch input is
used. The switch is nominally open for the 73S8024C
Demo Board. The jumpers can be set to:
1. Use of PRES (default): JP5 set to PRES; JP6 set
to VDD.
2. Use of PRES: JP5 set to PREB; JP6 set to GND.

73S8024C Demo Board User Manual UM_8024C_061
8 Rev. 1.3
Item
#
Schematic/
Silkscreen
Reference Name Function
Test Points:
10 TP1 Pin 17 (VDDF_ADJ) VDD voltage fault adjustment. The pin to the left is
connected to the VDDF_ADJ pin of the 73S8024C and
the pin to the right is GND. When either a resistor R3,
or a resistor network R1 and R3 is populated on the
board, it adjusts the VDD fault level that internally
triggers a card deactivation sequence.
By default, the resistors R1 and R3 are not connected.
This provides a VDD fault level of 2.3V typical (internally
set to the 73S8024C). Refer to the 73S8024C Data
Sheet for further information about VDD fault level and
determination of the resistor values.
20 TP2 Factory Test Factory test pin. Do not connect.
7
12
6
13
5
4
TP3
TP4
TP5
TP6
TP7
TP8
VCC
I/O
RST
C8
CLK
C4
2-pin test points for each respective smart card signal.
The pin label name is the respective signal (i.e. VCC,
CLK) and the 2nd pin is GND.
Figure 3: 73S8024C Demo Board Connectors, Jumpers and Test Points

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 9
3.2 Recommended Operating Conditions and Absolute Maximum Ratings
Table 2 lists the recommended operating conditions and Table 3 lists the absolute maximum ratings.
Operation outside these rating limits may cause permanent damage to the device.
Table 2: Recommended Operating Conditions
Parameter Rating
Supply Voltage VDD 2.7 to 3.6 VDC
Supply Voltage VPC 2.7 to 3.6 VDC
Ambient Operating Temperature -40 °C to +85 °C
Input Voltage for Digital Inputs 0 V to VDD + 0.3 V
Table 3: Absolute Maximum Ratings
Parameter
Rating
Supply Voltage VDD -0.5 to 4.0 VDC
Supply Voltage VPC -0.5 to 4.0 VDC
Input Voltage for Digital Inputs -0.3 to (VDD+0.5) VDC
Storage Temperature -60 °C to 150 °C
Pin Voltage -0.3 to (VDD+0.5) VDC
Pin Current ±100 mA
ESD Tolerance – Card interface pins +/- 6 kV
ESD Tolerance – Other pins +/- 2 kV
ESD testing on Card pins is HBM condition, 3 pulses, each polarity referenced to ground.
3.3 73S8024C Pin Description
Table 4: 73S8024C Card Interface Pins
Name
Pin #
Description
I/O 11 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
AUX1 13 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
AUX2 12 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
RST 14 Card reset: provides reset (RST) signal to card.
CLK 15 Card clock: provides clock signal (CLK) to card. The rate of this clock is
determined by crystal oscillator frequency or external clock input and
CLKDIV selections.
PRES 10 Card Presence switch: active high indicates card is present. Should be tied
to GND when not used, but it includes a high-impedance pull-down resistor.
PRES 9 Card Presence switch: active low indicates card is present. Should be tied
to VDD when not used, but it includes a high-impedance pull-up resistor.
VCC 17 Card power supply: logically controlled by sequencer output of LDO
regulator. Requires an external filter capacitor to the card GND.
GND 14 Card ground.

73S8024C Demo Board User Manual UM_8024C_061
10 Rev. 1.3
Table 5: 73S8024C Miscellaneous Pins
Name Pin # Description
XTALIN 24 Crystal oscillator input: can either be connected to crystal or driven as a
source for the card clock.
XTALOUT 25 Crystal oscillator output: connected to crystal. Left open if XTALIN is being
used as external clock input.
VDDF_ADJ 18 VDD fault threshold adjustment input: this pin can be used to adjust the VDDF
values (controls deactivation of the card). Must be left open if unused.
NC 5,7 Non-connected pin.
Table 6: 73S8024C Power and Ground Pins
Name
Pin #
Description
VDD 21 System interface supply voltage and supply voltage for internal circuitry.
VPC 6 DC-DC converter power supply source.
GND 4 DC-DC converter ground.
GND 22 Digital ground.
LIN 5 External inductor. Connect external inductor from pin 2 to VPC. Keep the
inductor close to pin 2.
Table 7: 72S8024C Microcontroller Interface Pins
Name Pin # Description
CMDVCC
19
Command VCC (negative assertion): Logic low on this pin causes the LDO
regulator to ramp the VCC supply to the card and initiates a card activation
sequence, if a card is present.
5V/#V 3 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card
interface, logic low selects 3 volt operation.
When the part is to be used with
a single card voltage, this pin should be tied to either GND or VDD. However,
it includes a high impedance pull-up resistor to default this pin high
(selection of 5V card) when not connected.
PWRDN 8 Power Down control input. Active high. When the Power Down mode is set
high, all internal analog functions are disabled to place the 73S8024C in its
lowest power consumption mode. The Power Down mode is only allowed
out of a card session (i.e. when CMDVCC = 1)
CLKDIV1
CLKDIV2
1
2 Sets the divide ratio from the XTAL oscillator (or external clock input) to the
card clock. These pins include pull-down resistors.
CLKDIV1
CLKDIV2
CLOCK RATE
0 0 XTALIN/8
0
1
XTALIN/4
1
1
XTALIN/2
1 0 XTALIN
OFF 23 Interrupt signal to the processor. Active low - multi-function indicating fault
conditions and/or card presence. Open drain output configuration; includes
an internal 22 kΩ pull-up to VDD.
RSTIN 20 Reset Input: This signal is the reset command to the card.
I/OUC 26 System controller data I/O to/from the card. Includes a pull-up resistor to VDD.
AUX1UC 27 System controller auxiliary data I/O to/from the card. Includes a pull-up
resistor to VDD.
AUX2UC 28 System controller auxiliary data I/O to/from the card. Includes a pull-up
resistor to VDD.

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 11
3.4 73S8024C Pinout
CLKDIV1
CLKDIV2
5V/#V
GND
VPC
PRES
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALIN
XTALOUT
OFF
VDD
RSTIN
CMDVCC
VCC
RST
CLK
NC
LIN
PWRDN
VDDF_ADJ
GND
73S8024C
1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
19
20
28
27
26
25
24
23
22
21
Figure 4: 73S8024C SO28 Pinout (Top View)

73S8024C Demo Board User Manual UM_8024C_061
12 Rev. 1.3
4 Design Considerations
4.1 General Layout Rules
•Route the auxiliary signals away from card interface signals.
•Keep the CLK signal as short as possible and with fewbends in the trace. Keep the route of the CLK
trace to one layer (avoid vias to other plane). Keep the CLK trace away from other traces, especially
RST and VCC. Filtering of the CLK trace is allowed for noise purpose. Up to 30 pF to ground is
allowed at the CLK pin of the smart card connector. In addition, the zero ohm series resistor, R7, can
be replaced for additional filtering (no more than 100 Ω).
•Keep the VCC trace as short as possible. Make the trace a minimum of 0.5 mm thick. In addition,
keep the VCC away from other traces, especially RST and CLK.
•Keep the trace from L1 to pin 5 of the IC as short as possible.
•Keep the RST trace away from the VCC and CLK traces. Up to 30 pF to ground is allowed for
filtering.
•Keep the 0.1 µF capacitor close to the VDD pin of the device and directly take the other end to
ground.
•Keep the 0.1 µF capacitor close to the VPC pin of the device and directly take the other end to
ground.
•Keep the 3.3 µF (1.0 µF for NDS) capacitor close to the VCC pin of the smart card connector and
directly take other end to ground.
4.2 Optimization for Compliance with EMV and NDS
The default configuration of the demo board contains a 27 pF capacitor (C12) from the CLK pin of the
smart connector to ground and a 27 pF capacitor (C13) from the RST pin of the smart connector to
ground. These capacitors serve as filters for the CLK and RST signals in the case of long traces or test
equipment perturbations. The capacitor on CLK reduces ringing on the trace, reduces coupling to other
traces and slows down the edge of the CLK signal. The capacitor on RST helps the perturbation
specification in a noisy environment. The filter capacitors can be useful in the EMV test environment and
have no effect on NDS testing.
C12 and C13 are represented on both the schematic and the BOM. These capacitors are optional filter
capacitors on the smart card lines CLK and RST, respectively for each card interface. These capacitors
may be adjusted (value not to exceed 30 pF) or removed to optimize performance in each specific
application (PCB, card clock frequency, compliance with applicable standards etc).
The default VCC capacitor of 3.3 µF is required to meet the dynamic VCC (smart card supply) transient
current requirement as specified in the EMV2000 version 4.0 specification. For compliance with NDS, a
smaller capacitor of 1 µF is required to meet the activation discharge time specification.

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 13
5 73S8024C Demo Board Schematics, PCB Layouts and Bill of Materials
5.1 Schematic
USR3
CLK
GND
JP6
1
2
3
PGND
5V C4
22pF
J4
TSM_110_01_L_SV
1
2
3
4
5
6
7
8
9
10
SC4
3.3V
R8
Ru
TP6
1
2
VDD
USR5
C4
VPC
R10
Ru
Resistors
not
populated
+
C10 10uF
3.3V
GND
C11
0.1uF
Connectors are positioned to allow
multiple 8024C boards (stacking) to a
73S1121F evaluation board. Also used for
connecting external signals when used as a
stand alone board.
JP4
HEADER LOCK 3
1
2
3
CLKDIV1
GND
USR2
+
C1 10uF
JP2 must be
set to 3.3V
Card detection
switches are
normally open
CARD DETECT
POLARITY SELECT
I/O
VDD
R11
Rd
SIO
L1
10uF
R2
0
R5 R7
0
R12
Rd
C8
GND
5.0V
TP7
1
2
JP2
1 2 3
R13
Rd
USR1
3.3V
C2 0.1uF
R6
OFFB
R4 0
C8
0.1uF
C1, C2, C8, C9 and L1 must be
placed within 5mm of the U1 pins
and connected by thick track
(wider than 0.5mm)
5V
S_C8
Resistors not
populated
U1
73S8024C
1
2
3
4
5
6
7
12
8
9
10
11
13
14 15
16
17
18
19
20
21
22
23
28
27
25
24
26
CLKDIV1
CLKDIV2
5V3V
GND_4
LIN
VPC
NC
AUX2
PWRDN
PRES
PRES
I/O
AUX1
GND_14 CLK
RST
VCC
VDDF_ADJ
CMDVCC
RSTIN
VDD
GND
OFF
AUX2UC
AUX1UC
XTALOUT
XTALIN
I/OUC
JP3 must be
set to 3.3V
J5 Smart Card Connector
1 2 3 4 5 6 7 8 9 10
VCC
RST
CLK
C4
GND
VPP
I/O
C8
SW-1 SW-2
SIO
TP2
1 2
CLKDIV2
JP3
1
2
3
3.3V
J2
TSM_110_01_L_SV
1
2
3
4
5
6
7
8
9
10
+
C3 10uF
5.0V
TP8
1
2
SC8
5V3VB
3.3V
TP4
1
2
PIN18
Signal names
refer to
73S1121F
Evaluation
board.
GND
NC
USR6
JP5
1
2
3
VDD
C5
22pF
5V
XTALIN
SELECT
GND
PWRDN
USR4
J1
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
SCLK
R9
Ru
TP1
1
2
SCLK
VDD
SELECT
Signal names
refer to
73S1121F
Evaluation
board.
VDD
CMDVCCB
TP5
1
2
XTAL
TP3 to TP8 to be placed
very close to the pads
of J5
R3
J6 SIM/SAM Connector
1 2 3 4 5 6 7 8
C1 C2 C3 C5 C6 C7
SW1 SW2
SCLK
+5V
TP3
1
2
RSTIN
L1 must be
placed close
to pin 5
VPC
SELECT
INT2
PRESB
S_C4
+5V
JP1
1
2
3
GND
PRES
J3
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
VCC
C9
0.47uF
+3.3V
VDD
C13
27pF
R1
RST
Y1
12.000MHz
1 4
C12
27pF
5.0V
USR7
USR0
Figure 5: 73S8024C Demo Board Electrical Schematic

73S8024C Demo Board User Manual UM_8024C_061
14 Rev. 1.3
5.2 Bill of Materials
Table 8 provides the bill of materials for the 73S8024C Demo Board schematic provided in Figure 5.
Table 8: 73S8024C Demo Board Bill of Materials
Item Quantity Reference Part PCB Footprint
Digikey Part
Number Part Number Manufacturer
1 3 C1,C3,C10 10 µF 805 PCC2225CT-ND ECJ-2FB0J106M Panasonic
2 2 C2,C8 0.1 µF 603 PCC1762CT-ND ECJ-1VB1C104K Panasonic
3 2 C4,C5 22 pF 603 PCC220ACVCT-ND ECJ-1VC1H220J Panasonic
4
1
C11
3.3 µF
805
PCC1925CT-ND
ECJ-2YB0J335K
Panasonic
5 2 C12, C13 27 pF 402 PCC270CQCT-ND ECJ-0EC1H270J Panasonic
6 1 L1 10 µH X SLF6025 TDK
7 5 JP1,JP2,JP3,JP5,
JP6 HEADER 3 3pins, 2.54 mm pitch S1011-36-ND PZC36SAAN Sullins
8
1
JP4
Header Lock 3
3pins, 2.54 mm
pitch
WM2701-ND
22-11-2032
Molex
9 2 J1,J3 SSM_110_L_SV SSM_110_L_SV X SSM_110_L_SV Samtec
10 2 J2,J4 TSM_110_01_L_SV TSM_110_01_L_SV X TSM_110_01_L_S
V Samtec
11 1 J5 Smart Card
Connector
ITT_CCM02-2504 ccm02-2504-ND ccm02-2504 ITTCannon
12 1 J6 SIM/SAM Connector ITT_CCM03-3754 CCM03-3754CT-ND
CCM03-3754 ITTCannon
13 3 R2,R4,R7 0 603 P0.0GCT-ND ERJ-3GEY0R00V Panasonic
14 2 R5,R6 X 603 X X
15 4 R1,R8,R9,R10 Ru 603 X X
16 4 R3,R11,R12,R13 Rd 603 X X
17 8 TP1,TP2,TP3,TP4,
TP5,TP6,TP7,TP8 TP2 2X1_Header S1011-36-ND PZC36SAAN Sullins
18 1 U1 73S8024C 28SOP X 73S8024C Teridian
Semiconductor
19
1
Y1
12.000 MHz
HC-49US
X190-ND
ECS-120-20-4DN
ECS
20 2 C4,C5 22 pF 603 PCC220ACVCT-ND ECJ-1VC1H220J Panasonic
1Ru and Rd are not populated on the board. They can be implemented to adjust the features of the smart card reader.

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 15
5.3 PCB Layouts
Figure 6: 73S8024C Demo Board Top View
Figure 7: 73S8024C Demo Board Bottom View

73S8024C Demo Board User Manual UM_8024C_061
16 Rev. 1.3
Figure 8: 73S8024C Demo Board Top Signal Layer
Figure 9: 73S8024C Demo Board Middle Layer 1, Ground Plane

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 17
Figure 10: 73S8024C Middle Layer 2, Supply Plane
Figure 11: 73S8024C Demo Board Bottom Signal Layer

73S8024C Demo Board User Manual UM_8024C_061
18 Rev. 1.3
6 Ordering Information
Table 9 lists the order number used to identify the 73S8024C Demo Board.
Table 9: Order Numbers and Packaging Marks
Part Description Order Number
73S8024C 28-Pin SO Demo Board 73S8024C-DB
7 Related Documentation
The following 73S8024C documents are available from Teridian Semiconductor Corporation:
73S8024C Data Sheet
73S8024C Demo Board User Manual (this document)
Teridian 73S8024C versus Philips TDA8024T Application Note
8 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the
73S8024C, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: [phone]
FAX: [phone]
Email: [e-mail]
For a complete list of worldwide sales offices, go to http://www.teridian.com.

UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 19
Revision History
Revision Date Description
1.0 6/8/2004 First publication.
1.1 8/2/2004 Minor corrections.
1.2
8/23/2005
Added new logo.
1.3 11/11/2009 Added Section 1.1, Package Contents.
Added Section 1.2, Safety and ESD Notes.
Added Section 6, Ordering Information.
Added Section 7, Related Documentation.
Added Section 8, Contact Information.
Miscellaneous editorial changes.

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Authorized Distributor
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73S8024C-DB