Texas Instruments OMAP5912 User manual

OMAP5912 Multimedia Processor
Device Overview and Architecture
Reference Guide
Literature Number: SPRU748A
March 2004

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3
OMAP5912SPRU748A
Preface
Read This First
About This Manual
This document introduces the setup, components, and features of the
OMAP5912 multimedia processor and provides a high-level view of the device
architecture.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
www.ti.com.
OMAP5912 Multimedia Processor Device Overview and Architecture
Reference Guide (literature number SPRU748) introduces the setup,
components, and features of the OMAP5912 multimedia processor and
provides a high-level view of the device architecture.
OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference
Guide (literature number SPRU749) introduces and briefly defines the
main features of the OMAP3.2 subsystem of the OMAP5912 multimedia
processor.
OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit-
erature number SPRU750) describes the OMAP5912 multimedia proc-
essor DSP subsystem. The digital signal processor (DSP) subsystem is
built around a core processor and peripherals that interface with: 1) The
ARM926EJS via the microprocessor unit interface (MPUI); 2) Various
standard memories via the external memory interface (EMIF); 3) Various
system peripherals via the TI peripheral bus (TIPB) bridge.

Related Documentation From Texas Instruments
4OMAP5912 SPRU748A
OMAP5912 Multimedia Processor Clocks Reference Guide (literature
number SPRU751) describes the clocking mechanisms of the
OMAP5912 multimedia processor. In OMAP5912, various clocks are
created from special components such as the digital phase locked loop
(DPLL) and the analog phase-locked loop (APLL).
OMAP5912 Multimedia Processor Initialization Reference Guide (litera-
ture number SPRU752) describes the reset architecture, the configura-
tion, the initialization, and the boot ROM of the OMAP5912 multimedia
processor.
OMAP5912 Multimedia Processor Power Management Reference Guide
(literature number SPRU753) describes power management in the
OMAP5912 multimedia processor. The ultralow-power device (ULPD)
generates and manages clocks and reset signals to OMAP3.2 and to
some peripherals. It controls chip-level power-down modes and handles
chip-level wake-up events. In deep sleep mode, this module is still active
to monitor wake-up events.This book describes the ULPD module and
outline architecture.
OMAP5912 Multimedia Processor Security Features Reference Guide
(literature number SPRU754) describes the security features of teh
OMAP5912 multimedia processor. The OMAP5912 security scheme re-
lies on the OMAP3.2 secure mode. The distributed security on the
OMAP3.2 platform is a Texas Instruments solution to address m-com-
merce and security issues within a mobile phone environment. The
OMAP3.2 secure mode was developed to bring hardware robustness to
the overall OMAP5912 security scheme.
OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support
Reference Guide (literature number SPRU755) describes the direct
memory access support of the OMAP5912 multimedia processor. The
OMAP5912 processor has three DMAs:
JThe system DMA is embedded in OMAP3.2. It handles DMA
transfers associated with MPU and shared peripherals.
JThe DSP DMA is embedded in OMAP3.2. It handles DMA
transfers associated with DSP peripherals.
JThe generic distributed DMA (GDD) is an OMAP5912 resource
attached to the SSI peripheral. It handles only DMA transfers
associated with the SSI peripheral.

Related Documentation From Texas Instruments
5
OMAP5912SPRU748A
OMAP5912 Multimedia Processor Memory Interfaces Reference Guide
(literature number SPRU756) describes the memory interfaces of the
OMAP5912 multimedia processor.
JSDRAM (external memory interface fast, or EMIFF)
JAsynchronous and synchronous burst memory (external
memory interface slow, or EMIFS)
JNAND flash (hardware controller or software controller)
JCompactFlash on EMIFS interface
JInternal static RAM
OMAP5912 Multimedia Processor Interrupts Reference Guide (literature
number SPRU757) describes the interrupts of the OMAP5912 multime-
dia processor. Three level 2 interrupt controllers are used in
OMAP5912:
JOne MPU level 2 interrupt handler (also referred to as MPU
interrupt level 2) is implemented outside of OMAP3.2 and can
handle 128 interrupts.
JOne DSP level 2 interrupt handler (also referred to as DSP
interrupt level 2.1) is instantiated outside of OMAP3.2 and can
handle 64 interrupts.
JOne OMAP3.2 DSP level 2 interrupt handler (referenced as DSP
interrupt level 2.0) can handle 16 interrupts.
OMAP5912 Multimedia Processor Peripheral Interconnects Reference
Guide (literature number SPRU758) describes various periperal inter-
connects of the OMAP5912 multimedia processor.
OMAP5912 Multimedia Processor Timers Reference Guide (literature
number SPRU759) describes various timers of the OMAP5912 multime-
dia processor.
OMAP5912 Multimedia Processor Serial Interfaces Reference Guide (lit-
erature number SPRU760) describes the serial interfaces of the
OMAP5912 multimedia processor.
OMAP5912 Multimedia Processor Universal Serial Bus (USB) Reference
Guide (literature number SPRU761) describes the universal serial bus
(USB) host on the OMAP5912 multimedia processor. The OMAP5912
processor provides several varieties of USB functionality. Flexible multi-
plexing of signals from the OMAP5912 USB host controller, the
OMAP5912 USB function controller, and other OMAP5912 peripherals
allow a wide variety of system-level USB capabilities. Many of the
OMAP5912 pins can be used for USB-related signals or for signals from
other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing

Related Documentation From Texas Instruments
6OMAP5912 SPRU748A
controls each pin individually to select one of several possible internal pin
signal interconnections. When these shared pins are programmed for
use as USB signals, the OMAP5912 USB signal multiplexing selects how
the signals associated with the three OMAP5912 USB host ports and the
OMAP5912 USB function controller can be brought out to OMAP5912
pins.
OMAP5912 Multimedia Processor Multi-channel Buffered Serial Ports
(McBSPs) Reference Guide (literature number SPRU762) describes
the three multi-channel buffered serial ports (McBSPs) available on the
OMAP5912 device. The OMAP5912 device provides multiple high-
speed multichannel buffered serial ports (McBSPs) that allow direct in-
terface to codecs and other devices in a system.
OMAP5912 Multimedia Processor Camera Interface Reference Guide (lit-
erature number SPRU763) describes two camera inerfaces implement-
ed in the OMAP5912 multimedia processor: compact serial camera port
and camera parallel interface.
OMAP5912 Multimedia Processor Display Interface Reference Guide (lit-
erature number SPRU764) describes the display interface of the
OMAP5912 multimedia processor.
JLCD module
JLCD data conversion module
JLED pulse generator
JDisplay interface
OMAP5912 Multimedia Processor Multimedia Card (MMC/SD/SDIO) (liter-
ature number SPRU765) describes the multimedia card (MMC) interface
of the OMAP5912 multimedia processor. The multimedia card/secure
data/secure digital IO (MMC/SD/SDIO) host controller provides an inter-
face between a local host, such as a microprocessor unit (MPU) or digital
signal processor (DSP), and either an MMC or SD memory card, plus up
to four serial flash cards. The host controller handles MMC/SD/SDIO or
serial port interface (SPI) transactions with minimal local host interven-
tion.
OMAP5912 Multimedia Processor Keyboard Interface Reference Guide
(literature number SPRU766) describes the keyboard interface of the
OMAP5912 multimedia processor. The MPUIO module enables direct
I/O communication between the MPU (through the public TIPB) and ex-
ternal devices. Two types of I/O can be used: specific I/Os dedicated for
8 x 8 keyboard connection, and general-purpose I/Os.
OMAP5912 Multimedia Processor General-Purpose Interface Reference
Guide (literature number SPRU767) describes the general-purpose in-

Related Documentation From Texas Instruments
7
OMAP5912SPRU748A
terface of the OMAP5912 multimedia processor. There are four GPIO
modules in the OMAP5912. Each GPIO peripheral controls 16 dedicated
pins configurable either as input or output for general purposes. Each pin
has an independent control direction set by a programmable register.
The two−edge control registers configure events (rising edge, falling
edge, or both edges) on an input pin to trigger interrupts or wake−up re-
quests (depending on the system mode). In addition, an interrupt mask
register masks out specified pins. Finally, the GPIO peripherals provide
the set and clear capabilities on the data output registers and the inter-
rupt mask registers. After detection, all event sources are merged and
a single synchronous interrupt (per module) is generated in active mode,
whereas a unique wake−up line is issued in idle mode. Eight data output
lines of the GPIO3 are ORed together to generate a global output line at
the OMAP5912 boundary. This global output line can be used in conjunc-
tion with the SSI to provide a CMT−APE interface to the OMAP5912.
OMAP5912 Multimedia Processor VLYNQ Serial Communications Inter-
face Reference Guide (literature number SPRU768) describes the
VLYNQ of the OMAP5912 multimedia processor.
VLYNQ is a serial communications interface that enables the extension
of an internal bus segment to one or more external physical devices. The
external devices are mapped into local, physical address space and ap-
pear as if they are on the internal bus of the OMAP 5912. The external
devices must also have a VLYNQ interface. The VLYNQ module serial-
izes bus transactions in one device, transfers the serialized data be-
tween devices via a VLYNQ port, and de-serializes the transaction in the
external device.
OMAP5912 includes one VLYNQ module connected on OCPT2 target
port and OCPI initiator port. These connections are configured via a stat-
ic switch, which selects either SSI or VLYNQ module. This switch, for-
bids the simultaneous use of GDD/SSI and VLYNQ. The switch is con-
trolled by the VLYNQ_EN bit in the OMAP5912 configuration control reg-
ister (CONF_5912_CTRL).
OMAP5912 Multimedia Processor Pinout Reference Guide (literature
number SPRU769) provides the pinout of the OMAP5912 multimedia
processor. After power-up reset, the user can change the configuration
of the default interfaces. If another interface is available on top of the de-
fault, it is possible to enable a new interface for each ball by setting the
corresponding 3-bit field of the associated FUNC_MUX_CTRL register.
It is also possible to configure on-chip pullup/pulldown. This document

Trademarks
8OMAP5912 SPRU748A
also describes the various power domains so that the user can apply the
different interfaces seamlessly with external components.
OMAP5912 Multimedia Processor Window Tracer (WT) Reference Guide
(literature number SPRU770) describes the window tracer module used
to capture the memory transactions from four interfaces: EMIFF, EMIFS,
OCP-T1, and OCP-T2. This module is located in the OMAP3.2 traffic
controller (TC).
OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit-
erature number SPRUxxx) describes the real-time clock of the
OMAP5912 multimedia processor. The real-time clock (RTC) block is an
embedded real-time clock module directly accessible from the TIPB bus
interface.
Trademarks
OMAP and the OMAP symbol are trademarks of Texas Instruments.

Contents
9
OMAP5912SPRU748A
Contents
1 Overview 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Subsystems 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 SDRAM/DDRAM Memory Interface 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Synchronous/Asynchronous Burst Memory Interface 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 CompactFlash 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Other Memory Types 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Serial Interfaces 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Camera and Display Interfaces 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Emulation and Test Interfaces 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 General-Purpose Interfaces 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Interfaces Multiplexing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 OMAP5912 Interface Usage Examples 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11.1 Audio Interfaces 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11.2 Bluetooth Interface 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11.3 Modem Connection 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 OMAP5912 Description 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 OMAP3.2 Gigacell 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 OMAP5912 Module Descriptions 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Clock and Reset Generation 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-MHz Oscillator 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ultralow-Power Device (ULPD) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OMAP5912 Clock and Reset Architecture 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Peripherals Subsystem 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCONV 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CompactFlash Controller 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Adjustment Counter (FAC) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light Pulse Generator (LPG) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SHA-1/MD5 Accelerator 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DES_3DES Accelerator 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Number Generator 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Camera Interface 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Counter 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS Timer 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Width Time (PWT) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
10 OMAP5912 SPRU748A
Pulse Width Length (PWL) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDQ/1-Wire Battery Monitoring Serial Interface 33. . . . . . . . . . . . . . . . . . . . . . . . . .
MCSI1 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCSI2 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mWire 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU GPIOs 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UARTs 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Clocking Scheme 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Available I/Os per UART 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP2 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP3 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Interface (SPI) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-Integrated Circuit (I2C) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB On-The-Go (OTG) 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Bit Dual-Mode Timer 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Synchronization Counter 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compact Camera Port (CCP) 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interconnect 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SoSSI 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMC/SDIO 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLYNQ 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Other Modules 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG TAP Controller 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eFuse Modules 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Device Configuration 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Security Layer 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic Distributed DMA (GDD) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 OMAP5912 Wake-up Capabilities 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 OMAP5912 Pin Description 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
11
OMAP5912SPRU748A
Figures
1 Top-Level OMAP5912 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 OMAP5912 Top-Level Detailed Diagram 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 OMAP3.2 Gigacell 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 LDCONV Integration 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 CompactFlash Interface 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 HDQ/1-Wire Overview 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 MCSI1 Interface 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 MCSI2 Interface 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 mWire Interface 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 6x5 Keyboard Connection 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 UART Clock Scheme 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 McBSP Interface With I2S-Compliant External Codec 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 McBSP Interface With Communication Processor 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 McBSP3 Interface Connected to Optical Device 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 I2C System Overview 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 USB OTG Integration at System Level 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 CCP Internal Block Diagram 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 CMT-APE Interchip Communication 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19 SoSSI Internal Block Diagram 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 MMC/SDIO Block Connection 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
12 OMAP5912 SPRU748A
Tables
1 MPU Private Peripherals 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 DSP Private Peripherals 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 MPU Shared Peripherals 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 DSP Shared Peripherals 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 MPU/DSP Statically Shared Peripherals 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 MPU/DSP Dynamically Shared Peripherals 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 OMAP5912 Dedicated Modules 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 OMAP5912 Test Modules 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Available I/Os per UART 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Event Captures for Peripheral Wake-up Capability 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13
IntroductionSPRU748A
Introduction
This document introduces the setup, components, and features of the
OMAP5912 multimedia processor and provides a high-level view of the device
architecture.
1 Overview
OMAP5912 is the next generation of OMAP processors and succeeds the
Texas Instruments OMAP5910 processor. It is built with TI 130-nm process
technology and has dual input/output voltage (1.8 V−3.3 V) capability. Like its
predecessor, it is fully programmable to perform one or more of the following
personal communication system tasks:
-Call manager
-Mail/fax reader/composer
-Internet access
-Personal digital assistant (PDA)
-Personal information management (PIM)
-Multimedia engines
This system is optimized for various multimedia codecs, such as:
-MPEG4
-MP3
-JPEG
-H.263
Furthermore, it is capable of running advanced speech applications:
-Text to speech
-Speech recognition
The OMAP5912 also supports secure operations.
Figure 1 shows OMAP5912 at the top level.

Overview
Introduction
14 SPRU748A
Figure 1. Top-Level OMAP5912
M
I
F
S
M
I
F
F
O
E
E
C
P
−
T1
O
C
P
−
T2
O
C
P
−
I
Memory interface
traffic controller (TC)
MPU private peripherals
Timers (3)
Watchdog timer
Level 1/2 interrupt handlers
Configuration registers
System DMA
Secure watchdog
RNG
DES/3DES
SHA1/MD5
32-kHz watchdog
LCDCONV
ULPD
Clock and reset management
OSC OSC
µWire I/F
Camera I/F
RTC
PWT
PWL
Keyboard I/F
HDQ/1-Wire
MMCSDIO1
MPUIO
LPG1, 2
FAC
OS timer
MPU public peripherals
CCP
SoSSI
USB controllers
External clock
requests
ResetClock
32 kHz12 MHz
16
32
16
32
32
32
32
32
32 32
32
16
16 16
32
32 16
OMAP5912
MPU private
peripheral bus
MPU public
peripheral bus
DSP public (shared)
peripheral bus
DSP
public peripheral bus
Frame
Buffer
ETM9
MPU core
ARM926EJS
(Instruction
cache, data
cache, MMU)
LCD
I/F
Flash
and
SRAM
SDRAM
CompactFlash
Boot ROM
Secure eFUSE
Secure RAM
Security layer
DSP
MMU
Endianism
conversion
MPU
interface
System
DMA
controller
MPU
peripheral
bridge
Endianism
conversion
MPU bus
TMS320C55x DSP
(Instruction cache, SARAM,
DARAM, DMA,
H/W accelerators)
DSP public peripherals
DSP private peripherals
Timers (3)
Watchdog timer
Level 1/2 interrupt handlers
McBSP1 (audio PCM I/F)
MPU/DSP shared peripherals
Mailbox
MPU/DSP static shared
8 x GPTIMERS
SPI
UART1, 2, 3
I2C
MMCSDIO2
McBSP2
MPU/DSP dynamic shared
GPIO1, 2, 3, 4
32-kHz synchro counter
McBSP3 (optical I/F)
MCSI1 (Bluetooth voice I/F)
MCSI2 (moden voice)
Switch
VLYNQ
GDD
SSI
JTAG/emulation I/F
The OMAP5912 includes the microprocessor unit (MPU) subsystem, the
digital signal processor (DSP) subsystem, the system direct memory access
(SDMA), and part of the L3 and L4 interconnects. All other components of
OMAP5912 are associated with the OMAP gigacell revision 3.2.
The OMAP5912 device provides a secure environment to run secure
applications. The security hardware components include:
-OMAP3.2 gigacell security state machine
-Dedicated secure RAM
-Secure boot ROM
-Secure electrical fuse (eFuse) components
-Secure peripherals

Overview
15
IntroductionSPRU748A
1.1 Subsystems
The OMAP5912 chip subsystems have these characteristics:
-The MPU subsystem is based on the ARM926EJ core, which performs
most operations on the chip.
-The DSP subsystem is based on a TMS320C55xtDSP core, which
performs intensive data computing tasks.
-The internal memory subsystem (frame buffer) is a single-port SRAM .
-The system DMA helps the MPU perform data memory transfer-specific
tasks, leaving a million more instructions available per second (MIPS) for
both processors.
-The system components (ULPD, oscillators, etc.) are responsible for
managing system interactions, such as interrupt, clock control, and idle.
-The memory interfaces define the system memory access organization of
OMAP5912.
-The peripheral subsystem defines all of the components used to interface
OMAP5912 with specific external devices, such as compact camera port
(CCP), keyboard, and smart display.
-The security modules include ROM, a single port SRAM, eFuse cells, and
secure peripherals, which enable the system to support secure
applications.
-The universal serial bus (USB) and synchronous serial interconnect (SSI)
interface enable the platform to support a universal serial link and a
dedicated modem interface, which in turn enable a high data transfer rate
between the modem and the OMAP5912.
-The device features two types of interconnectivity:
JThe L3 interconnect is the memory interconnection among the MPU,
DSP, DMA, and an external host (through USB or SSI interface).
JThe L4 interconnect provides all of the peripheral interconnections
among the MPU, DSP, and DMA.

Overview
Introduction
16 SPRU748A
1.2 SDRAM/DDRAM Memory Interface
The OMAP5912 external memory interface fast (EMIFF) is an synchronous
dynamic RAM (SDRAM) controller that manages all accesses by the various
initiators of an OMAP system. It can support one 16-bit device or two 8-bit
devices. The external interface data bus width is always 16 bits.
The following devices are supported:
-Standard single-data-rate SDRAM
-Low-power single-data-rate SDRAM (mobile SDRAM)
-Standard double-data-rate SDRAM (DDRAM)
-Low-power double-data-rate SDRAM (mobile DDRAM)
In terms of capacity and organization of the memory components that can be
attached, the EMIFF can handle:
-1G-bit, 512M-bit, 256M-bit, 128M-bit, 64M-bit, and 16M-bit devices
-2-bank or 4-bank devices for 16M-bit or 64M-bit devices
-4-bank devices only for any other capacity
-x8 (two devices) or x16 (single device) data bus configuration, except for
the 1G-bit device. The EMIFF supports only two x8, 512M-bit devices and
a single x16, 1G-bit device (128 megabytes, maximum memory
configuration).
1.3 Synchronous/Asynchronous Burst Memory Interface
The synchronous/asynchronous external memory interface slow (EMIFS)
supports most common memory interface protocols through flexible
programming and timing signals control.
The EMIFS controls up to six devices without adding any external logic through
six independent chip-selects (CSs) and through dedicated memory interface
control signals. Two configurable options are supported:
1.4 CompactFlash
OMAP5912 supports CompactFlash with a dedicated compact flash
controller.
1.5 Other Memory Types
OMAP5912 includes multiple serial interfaces that can be used to connect
multiple types of memories, including:
-Up to two multimedia cards through the multimedia memory card
interfaces (MMC/SDIO)

Overview
17
IntroductionSPRU748A
1.6 Serial Interfaces
OMAP5912 provides several serial interfaces:
-A master/slave serial port interface (SPI), enabling serial data transfer
compatible with common SPI protocol
-Three multichannel buffered serial port (McBSP) peripherals, enabling
emulation of the following serial protocols:
JSerial port interface
JAn I2S-compatible interface
JA DSP serial input/output
JMultichannel time division multiplexer
-An I2C with multimaster and slave support
-A multichannel and full duplex serial synchronous interface (SSI)
-A universal serial bus (USB) interface client, host, and USB On-The-Go
configuration
-A serial µWire interface
-Two multichannel serial interfaces (MCSI)
-Three universal asynchronous transceivers (UART1, UART2, UART3)
-HDQ and 1-Wire interfaces
1.7 Camera and Display Interfaces
There are three video interfaces:
-The compact camera port (CCP) interface is a unidirectional serial
interface that connects to a camera.
-The camera IF is an 8-bit parallel interface with horizontal/vertical camera
input signal.
-Two types of LCD display IFs:
JAn 8-bit/16-bit configurable parallel bidirectional display interface that
enables a smart display connection using the MeSSI standard
JThe OMAP internal LCD controller that enables simple LCD interfaces
and control

Overview
Introduction
18 SPRU748A
1.8 Emulation and Test Interfaces
OMAP5912 has these emulation and test interface features:
-JTAG emulation capabilityfor non-realtime debug
-You can use a window tracer (WT) module to capture the memory
transactions from four interfaces: EMIFF, EMIFS, OCP-T1, and OCP-T2.
The captured information is sent outto the serial tracer interface (STI) for
processing for debugging purposes. For more detail on this memory
transaction trace, see Appendix E, Window Tracer.
-An embedded trace macrocell (ETM) to enable real-time trace of the MPU
subsystem operations
-Concurrent DSP and MPU emulation
1.9 General-Purpose Interfaces
OMAP5912 includes dedicated modules to support specific modulation and
control of general-purpose inputs and outputs:
-General-purpose input/output (GPIO) modules allow the monitoring and
control of OMAP5912 device input/output pins with event detection for
external interrupts support.
-The pulse width tone (PWT) module provides OMAP5912 output pins with
waveform control for tone generation.
-The pulse width light (PWL) module allows OMAP5912 output pins
waveform control for brightness light control.
-Two light pulse generator (LPG) modules allow OMAP5912 output pins
waveform control for LED blinking control.
-Three general-purpose timers enable OMAP5912 output pins waveform
control for pulse width modulation support and OMAP5912 input pins
events detection with timing stamp.
1.10 Interfaces Multiplexing
Because of the device I/O limitations, the interfaces are not accessible at the
same time, and some of them are multiplexed. For more detail on I/O
multiplexing and control, see Chapter 22, Pinout.

OMAP5912 Description
19
IntroductionSPRU748A
1.11 OMAP5912 Interface Usage Examples
This section contains three examples of OMAP5912 usage:
-Audio interface
-Bluetoothtinterface
-Modem connection
1.11.1 Audio Interfaces
OMAP5912 supports a modem audio PCM codec interface, a modem voice
interface, and a Bluetoothtvoice interface simultaneously. These interfaces
can be provided through various OMAP5912 peripherals:
-McBSP, which is compliant with the I2C standard and can be connected
to an audio codec.
-MCSI, which can be used as voice interface (see Section 1.11.2 and
Section 1.11.3)
1.11.2 Bluetooth Interface
The Bluetooth interface has the following data, voice, and power management
interfaces:
-The data interface can be provided by UART1.
-The voice interface can be provided by MCSI1.
-The power interface is the clock request pins.
1.11.3 Modem Connection
Two examples propose ways to connect a modem to the OMAP5912 device:
-Using a CMT-APE interface: the SSI exchanges data between the modem
and OMAP5912. The control uses GPIO pins.
-Using data, control, voice, and power management interfaces:
JData interface can be the McBSP2.
JControl interface can be the UART2.
JPower management interface is the clock request pins.
JVoice interface can be the MCSI2.
2 OMAP5912 Description
Figure 2 shows the OMAP5912 in detail.

OMAP5912 Description
Introduction
20 SPRU748A
Figure 2. OMAP5912 Top-Level Detailed Diagram
System DMA
handler
MPU Inth L2
Secure watchdog
OMAP5912
configuration
RNG
DES/3DES
32K watchdog
SHA-I/MP5
LCDCONV
MPU private bus MCSI1
MCSI2
McBSP3
McBSP1
HDQ/1-Wire
µWire
MMC/SDIO1
MPUIO
Camera IF
LPG1
LPG2
SoSSI
CCP
RTC
PWL
PWT
FAC
OS timer
DSP DMA handler
DSP Inth L2.1
Dynamic switches
STI
Dynamic switches
GPIO1
GPIO2
GPIO3
GPIO4
32K
SynchroCounter
Static switches
8 X GPTIMER
SPI M/S
3 X UART (1,2,3)
I2C
MMC/SDIO2
McBSP2
DSP P
LCD/
LCD W
MPU S
DSP S
MPU P
EMIFS
EMIFF
OCP-T1
OCP-T2
OCPI
OMAP3.2
OCP interconnect
GDD
SSR
SST
SSI
USB On-The-Go
Frame
buffer
ULPD APLL
OSC
OSC
Test
(ETLM, BOM, SCM,
Die ID,
JTAG, production ID,
eFUSE ctl)
CompactFlash ctrl
Boot ROM
Secure eFuse
Secure RAM
Security layer
32
16
32
16
MPU public bus
DSP
private
bus
DSP shared bus
32
OCP_I
switch
OCP_T
switch
VLYNQ