Texas Instruments FPD23DAEVM User manual

FPD23DAEVM User's Guide
User's Guide
Literature Number: SNLU144
may 2013

Chapter 1
SNLU144–may 2013
Introduction
1.1 FPD23DAEVM
FPD23DAEVM is designed to directly adapt to one of the following types of RGB data and source
HDMI/DVI compatible video output.
• FPD-Link I (Four LVDS data/control streams and one LVDS clock pair)
OR
• Parallel LVCMOS (RGB888) signals and clock.
Hence, it act as a powerful tool to evaluate performance of FPD-Link II/III Serial link Devices.
The adapter has an on board PanelBus Digital Transmitter, TFP410 which is DVI 1.0-compliant solution.
DVI and HDMI have the same electrical specifications for their TMDS and VESA/DDC links, output of
TFP410 is routed to 19-pin HDMI type-A connector. Hence, hooking up this board with one of the
deserializer in FPD-Link II/III family allows evaluation of the serial link through direct observation of the
video data on HDMI/DVI compatible display.
Figure 1-1. FPD-Link II/III Display Adapter
FPD23DAEVM contains FPD-Link II/III Display Adapter board only. (1)
(1) Other components required: 12V DC Supply, an HDMI cable or HDMI to DVI adapter cable, an HDMI or DVI compatible display.
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www.ti.com FPD23DAEVM Features
1.2 FPD23DAEVM Features
1. PanelBus Digital Transmitter, TFP410 supports flat panel display resolutions up to UXGA and
maximum pixel rate of 165 MHz in 24-bit true color pixel format.
2. It can accept FPD-Link I input or parallel LVCMOS (RGB888) input based on a simple set of hardware
configuration.
3. Although designed to be used with an HDMI cable, it is easy to hook up the output to DVI display using
an HDMI to DVI adapter cable.
4. Once a DC supply of 12V (recommended current limit is 500mA) is connected to FPD23DAEVM, it can
supply 3.3V (400mA) DC to other devices used in the system such as deserializer.
5. Optionally, PCF8582C-2 can be populated, which is connected to on board I2C bus and allows
implementation of EDID.
6. TFP410 allows minimization of the skew between parallel RGB data and clock signal through a control
switch (S1).
7. TPD8S009 and TPD4E001 provide ESD protection at the output for display port.
1.3 Typical Application
Figure 1-2 below illustrates a typical setup for FPD23DAEVM with either FPD-Link I source or parallel
LVCMOS (RGB888) as a source for RGB data and clock signals. These signals are then translated into
TMDS for transmission over HDMI cable.
Figure 1-2. Typical Application/Evaluation Configuration
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Chapter 2
SNLU144–may 2013
Quick Start Guide
This chapter provides minimal steps required to setup FPD23DAEVM in the two hardware configuration
depending upon the type of input signals. Switch and jumper position required for this operation have
been set at the factory.
1. Verify the factory settings for the adapter board as shown in Figure 2-1 and Figure 2-2.
2. Connect either FPD-Link I input to J3 or parallel LVCMOS (RGB888) input to J2. Make sure that board
is configured for corresponding input type, refer to Section 2.1 and Section 2.2.
3. Connect 12V power supply to either J6 or J1 as shown in . LED D1(green) indicates that board is
correctly powered up and 3.3V(200mA) supply is available at J5.
4. Connect an HDMI/DVI compatible display device to J4 using an HDMI cable. Desired results can be
observed on the display. (2)
2.1 Board Setup with FPD-Link input
In this configuration, connect input to J3 and instructions below should be followed,
1. Make sure RN5, RN6, RN7 and RN8 are mounted.
2. To avoid stubs, RN1, RN2, RN3 and RN4 should not be mounted.
3. Verify pin HIGH and PDN to be shorted on JP2 while using FPD-Link I input.
Figure 2-1. FPD23DAEVM with FPD-Link input
(2) MSEN/PO1 signal on TP4 should be high, once the display/receiver connected to J4 is detected properly.
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www.ti.com Board Setup with Parallel LVCMOS input
2.2 Board Setup with Parallel LVCMOS input
In this configuration connect input to J2 and instructions below should be followed,
1. Make sure RN1, RN2, RN3 and RN4 are mounted.
2. RN5, RN6, RN7 and RN8 should not be mounted to avoid stubs.
3. Verify pin VSS and REF to be shorted on JP6 while using RGB888 parallel LVCMOS input.
Figure 2-2. FPD23DAEVM with Parallel LVCMOS input
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Chapter 3
SNLU144–may 2013
Evaluation Hardware Overview
FPD23DAEVM includes circuits and interfaces facilitating the full control over the devices present on the
board.
3.1 Power
FPD23DAEVM can be powered up by 6V(min) to 12V(max) DC supply as detailed in Figure 2-1 and
Figure 2-2.Apply power to only ONE of these ports: J1 or J6.
Table 3-1. Power
Reference Description and Default settings
12V power port
J1 Do not apply more than 12V and less than 6V DCsupply to this port.
12V power jack
J6 Do not apply more than 12V and less than 6V DCsupply to this port.
3.3V power port
J5 This port can be used to power up the Deserializer board to which the adapter is connected. It can
source up to 400mA of current.
3.2 Video Data Input
As mentioned earlier, there two input options available.
NOTE: To ensure electrical signal compatibility,
1. Board is by default configured for LVCMOS threshold of VIH(min)= 2.31V and
VIL(max)= 0.99V for the PanelBus Transmitter, TFP410. This allows using this
board with deserializer VDDIO = 3.3V.
2. To work with low signal swings (with deserializer VDDIO = 1.8V), change R7 to
40kΩand R8 to 15kΩ. This hardware change corresponds to VIH(min)= 1.1V and
VIL(max)= 0.7V.
3.2.1 FPD-Link Video Data Input
Header J3 (mounted on bottom side) accepts a 20-pin IDC or similar 0.1" spaced male header. Connect
the clock and 4 FPD-Link (LVDS) data pairs to this header as marked on the silk screen. 100Ωdifferential
termination is provided on the board near DS90CF386 (U4) device pins.
Figure 3-1. FPD-Link Input header: J3
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3.2.2 Parallel LVCMOS Video Data Input
Header J2 (mounted on bottom side) accepts R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK as inputs. The
even numbered pins are the inputs. The odd numbered pins are connected to REF (pin 2 of JP6). Jumper
JP6 is factory set to select VSS as a reference.
Figure 3-2. Parallel LVCMOS Input header: J2
3.3 Video Output
Connect an HDMI cable between connector J4 and an HDMI display OR
An HDMI to DVI adapter cable can be used to connect to a DVI display.
3.4 Hardware controls
Hardware controls present on the board determines the specific mode or state of operation.
Table 3-2. Description : Control element
Reference Description and Default settings
Allows access to multifunction input (pin 6, 7, 8) of TFP410.
For more details on function of these pin, refer Table 3-3 and device datasheet.
JP1 Default : CTL[3:1] = 100
To pull these pins High or Low, switch S1 can be used.
Connected to PDN pin of DS90CF386.
HIGH: DS90CF386 CMOS output will be switching. (This condition is required while using FPD-Link I
JP2 input)
LOW: DS90CF386 CMOS output will be low.
I2C clock port
JP3 Allows access to SCL pin of TFP410(U1), U3 and DDC_C (1).
I2C serial data port
JP4 Allows access to SDA pin of TFP410(U1), U3 and DDC_D (2).
Address select port for U3
JP5 It allows to select an appropriate address for U3 (PCF8582C-2, not provided) in the range 0x50 to 0x57.
Default : floating
To select appropriate reference for LVCMOS inputs.
JP6 Default : LVCMOS inputs refer to VSS.
It also allows strapping of parallel LVCMOS input connector pins.
Allows shorting schottky diode D3, if required.
JP7 Default : Open
This switch controls the operation of TFP410 PanelBus digital transmitter only and the default settings
are listed below,
S1.10 : CTL3 : HIGH, Default de-skew settings, although de-skew is disabled.
S1.9 : CTL2 : LOW, Default de-skew settings, although de-skew is disabled.
S1.8 : CTL1 : LOW, Default de-skew settings, although de-skew is disabled.
S1.7 : EDGE/HTPLG : LOW, Falling edge of input clock IDCK+ selected for primary latch to occur
S1 S1.6 : ISEL/RST : LOW, I2C disabled
S1.5 : DSEL/SDA : LOW, Single ended input clock mode
S1.4 : BSEL/SCL : HIGH, 24-bit, single edge input mode
S1.3 : DKEN : LOW, De-skew disabled
S1.2 : NONE : LOW, not used
S1.1 : PD : HIGH, TFP410 is in normal operation mode
Refer Table 3-3 for detailed description of TFP410 control associated with this switch.
(1) Pull up is not present for DDC_C pin.
(2) Pull up is not present for DDC_D pin.
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Indicators and Test points www.ti.com
Table 3-3 below describes function of switch S1 in more detail.
Table 3-3. Switch S1 Functions
Description
Switch Control
position I2C Disabled (ISEL/RST= LOW) I2C Enabled (ISEL/RST= HIGH)
When De-skew mode is disabled (DKEN= Acts as 3 LSBs of the 7 bit I2C address of
LOW), CTL2 & CTL1 can be used to send TFP410,
additional information across the DVI link A[3:1]=000 to select 7 bit I2C address as 0x38
during blanking interval (DE= LOW).
S1.10 CTL3 through
S1.9 CTL2 When De-skew mode is enabled (DKEN= A[3:1]=111 for 0x3F.
S1.8 CTL1 HIGH), these 3 inputs become DK[3:1], used Based on read or write operation 1 or 0 is
to adjust the setup and hold times of the appended to form the 8 bit I2C address, refer
pixel data inputs relative to IDCK+. Refer device datasheet for more details.
device datasheet for more details.
HIGH : Primary latch occurs on the rising
edge of IDCK+ Used to monitor the hot plug detect signal.
LOW : Primary latch occurs on the falling Make sure that R4 is mounted, R13 is not
S1.7 EDGE/HTPLG edge of IDCK+ mounted and S1.7 is set HIGH for the
Make sure that R13 is mounted and R4 is operation.
not mounted for the operation.
S1.6 ISEL/RST LOW : I2C disabled HIGH : I2C enabled
Depends upon VREF and BSEL, refer This switch should be positioned high for the
S1.5 DSEL/SDA TFP410 device datasheet. external pull up on SDA line.
HIGH : selects 24-bit input, single ended
input mode. This switch should be positioned high for the
S1.4 BSEL/SCL LOW : selects 12-bit input, dual edge input external pull up on SCL line.
mode.
HIGH : Enables de-skew with the trim
increment selected through S1.10, S1.9, This pin should be tied either to GND or to
S1.3 DKEN S1.8 VDD and avoid floating input. De-skew function
LOW : Disables de-skew and default trim can be accessed through I2C.
setting is used
S1.2 Not used - -
In this mode, PD pin should be tied to GND.
HIGH : Normal operating mode
S1.1 PD Power down state is selected through I2C and
LOW : Power down mode default mode is Power down.
3.5 Indicators and Test points
Table 3-4. Description : Indicators and Test points
Reference Description
D1 3.3V LDO supply indicator : Green LED
Hot plug detect / Edge Select : Red LED
• By default (I2C disabled on TFP410), it will indicate the status of the input clock (IDCK+) edge
selected (though S1.7) for primary latch on TFP410,
D2 HIGH : Rising edge
TP1 LOW : Falling edge (default)
Make sure that R13 is mounted and R4 is not mounted for the operation.
• When I2C enabled, it indicates hot plug detect signal status.
Make sure that R4 is mounted, R13 is not mounted and S1.7 is set high for the operation.
TP2 HDMI CEC pin test point
TP3 Programming time control output of U3
Monitor sense/ programmable output of TFP410
• When I2C is disabled,
HIGH level on this pin indicates a receiver is detected at the differential outputs,
TP4 Low level indicates a power on receiver is not detected
• When I2C is enabled, this output is programmable through I2C interface, refer TFP410 device
datasheet for more details.
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www.ti.com I2C and Device Addressing (3)
3.6 I2C and Device Addressing (1)
FPD23DAEVM provides flexibility to configure I2C bus as per the requirement.
Figure 3-3. I2C and Device Addressing
1. Header J7 is directly connected to U3 as shown in Figure 3-3, which allows implementation of external
EDID (2) (it requires mounting PCF8582C-2 on board). When 12V is supplied to the EVM, SCL and
SDA lines are pulled high to 5V by resistor R19 and R25 on the board.
The SCL and SDA lines are also connected to pin 1 of JP3 and JP4 respectively.
I2C device address of U3 can be configured by connecting the JP5 pins to either VSS or VDD. Refer
PCF8582C-2 device datasheet for more details.
2. Pin2 of JP3 and JP4 are connected to BSEL/SCL and DSEL/SDA pins of U1, TFP410. Note that, to
communicate with TFP410 over I2C proper settings are required on switch S1. Refer Table 3-3.
3. Pin3 of JP3 and JP4 are connected to DDC_C and DDC_D lines from the HDMI connector, J4. This
might be useful while using the actual EDID of the display.
(1) Unless resistor R19 and R25 are removed, do not put jumper across pin 1 and 2 of either JP3 or JP4. This may damage TFP410 on the
board.
(2) EDID (Extended Display Identification Data) is a display's feature of describing its identity and capabilities to the source, e.g.: video
formats, audio formats, colorimetry, lip-sync delays, etc.
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Chapter 4
SNLU144–may 2013
Using Internal Test Pattern Generation of 720p FPD-Link
III Devices
This section provides basic steps to use Internal Test Pattern Generator of 720p FPD-Link III devices to
observe the output on HDMI/DVI compatible display through FPD23DAEVM.
ALP provides an interactive GUI to control the internal pattern generator of DS90Ux92x family of devices
as shown below.
Here, a specific example of DS90UH925 & DS90UH926 serial link is considered, however similar
procedure applies to other members of DS90Ux92x family.
1. Connect USB cable to DS90UH925QSEVB and launch ALP. Once DS90UH925 is detected by the
software as shown in Figure 4-1, click on the device name and select Pattern Generator tab.
Figure 4-1. Initial Window
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2. Under Video Control, select Timing source as Internal or Internal w/Ext. Clock as shown in
Figure 4-2.
Figure 4-2. Timing Source (4) (5)
3. Under Internal Timing> Spec, select appropriate option depending upon the type of display.
Figure 4-3. Internal Timing : Spec
(4) In Internal w/Ext. Clock mode, external PCLK is required on Serializer, all other signals are generated by the device itself.
(5) In Internal mode, all signals including PCLK are generated by the device itself.
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4. If Timing Source is selected as Internal, it is required to select Approximate Pixel Clock which is
within acceptable range of PCLK of the display device connected.
Figure 4-4. Approximate Pixel Clock
5. Finally, check on Enable Generator and observe the output on display.
Optionally, Enable Scrolling to view changing patterns on the display.
Figure 4-5. Enable Generator and Scrolling
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Appendix A
SNLU144–may 2013
Board Schematic
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Board Stackup www.ti.com
A.1 Board Stackup
Figure A-1. Board Stackup
14 Board Schematic SNLU144–may 2013
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CAPS for U1
1. Place one 0.1-uF capacitor as close as possible between each device
power pin and ground.
2. A bulk decoupling capacitor such as a 10-uF or 22-uF tantalum
capacitor should be placed on
the sub-plane between the supply and 0.1-uF capacitors.
3. A ferrite bead should be used to separate the sub-plane from the
source.
Data2+/-. Data1+/-, Data0+/-, Clock+/- are high speed differential
traces.
1. Trace impedance should be controlled for optimal performance, 50
ohms recommended.
2. Each differential pair should be equal in length and symmetrical and
should have equal impedance to ground with a trace separation of 2x to
4x Height.
3. No 90° angles.
4. These high-speed transmission traces should be on an outer layer
with a continuous ground plane on the next plane layer.
5. Route this signal to J4A via U7 and U2 pins. (ESD protection)
The data (R, G, and B), control, and clock lines
(coming from resistor arrays) should all be of
equal length in order to prevent any skew being
introduced between clock and data.
The data (R, G, and B), control, and clock
lines (going to resistor arrays) should all be
of equal length in order to prevent any skew
being introduced between clock and data.
Data0+
Clock+
TGND
TVDD
TGND
TVDD
TGND
PVDD
PGND
G3 D_G3
VDD_3.3V
G2 D_G2
G1 D_G1x
VDD_3.3V
G0 D_G0
B7 D_B7
B6 D_B6
VSS
D_PCLK
B5 D_B5
B4 D_B4
B3 D_B3
B2 D_B2
B1 D_B1x
B0 D_B0x
DGND
G4
D_G4
PVDD
PGND
VREF
PD
G5
D_G5
G6
D_G6
G7
D_G7
DVDD
R0
D_R0
DSEL/SDA
R1
D_R1
R2
D_R2
TGND
VDD_3.3V
VSS
VSS
PCLK_IN
TVDD
FBIN
D_PCLK
R3
D_R3
R4
D_R4
R5
D_R5
BSEL/SCL
R6
D_R6
R7
D_R7
DKEN VSS DVDD
DKEN
DGND
DVDD
DE D_DE
VREF
HS D_HS VS D_VS
CTL3 CTL2
EDGE/HTPLG
CTL1
EDGE/HTPLG PD MSEN/PO1
DVDD
MSEN/PO1
DGND
ISEL/RST
DSEL/SDA BSEL/SCL
VDD_3.3V
VSS
VDD_3.3V
CTL3 CTL1
CTL2
ISEL/RST
Data2+
VSS
DGND
Data1+
VDD_3.3V
VDD_3.3V
VSS
PD
R0 R1 R2 R3 R4 R5 R6 R7
G0 G1 G2 G3 G4 G5 G6 G7
B0
B1 B2 B3 B4 B5 B6 B7
HS VS DE PCLK
VDD_3.3V
VSS
VSS
VSS
VSS FBIN
PCLK
PCLK_IN
PCLK_OUT
PCLK_OUT
VSS
Data2-
Data1-
Data0-
Clock-
3.3V
VSS
DSEL/SDA
BSEL/SCL
EDGE/HTPLG
2+
2-
1+
1-
0+
0-
C+
C-
R0 R1 R2 R3 R4 R5 R6 R7
G0 G1 G2 G3 G4 G5 G6 G7
B0 B1 B2 B3 B4 B5 B6 B7
HS
VS
DE
PCLK
R5
510
12
O
N
1 2 3 4 5 6 7 8 9 10
S1
SW
1
2
3
4
13
14
15
16
5
6
7
8
12 11 10 9 18 17
19
20
FB3
600ohm,250mA
+
C10
22uF
1
2
RN3 RESAR_IS_8/SM
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10
9
R34 0
12
+ C12
22uF
1
2
C18
1.0uF
RN1 RESAR_IS_8/SM
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10
9
C7
0.1uF
JP6
1
2
3
TP4
1
JP1
1 2 3
R16
5.1K
12
R11
10K
12
R36
10K
12
R15
5.1K
12
R13
1K
12
R37
NO STUFF
R39
NO STUFF
C17
10uF
1
2
R70
12
L1 2.2uH
1 2
R22 22
12
U5
CY2302
FS0
4FS1 5
OUT1 6
VDD 7
OUT2 8
GND
3IN
2FBIN
1
R33 0-NO-STUFF
12
C15
0.01uF
1
2
R17
10K
12
R24 0
12
R1410K
1
2
R9
5.1K
12
R210
12
C8
0.1uF
C16
0.1uF
1
2
FB2
600ohm,250mA
FB1
600ohm,250mA
RN2 RESAR_IS_8/SM
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10
9
R8
ADJ-NO-STUFF
12
R10
10K
12
R23 22
12
U1
TFP410
DVDD
1
DE
2
VREF
3
HSYNC
4
VSYNC
5
CTL3
6
CTL2
7
CTL1
8
EDGE
9
PD
10
MSEN
11
DVDD
12
ISEL
13
DSEL
14
BSEL
15
DGND
16
PGND 17
PVDD 18
TFADJ 19
TGND 20
TXC- 21
TXC+ 22
TVDD 23
TX0- 24
TX0+ 25
TGND 26
TX1- 27
TX1+ 28
TVDD 29
TX2- 30
TX2+ 31
TGND 32
DGND 48
DATA12 47 DATA13 46 DATA14 45 DATA15 44 DATA16 43 DATA17 42 DATA18 41 DATA19 40 DATA20 39 DATA21 38 DATA22 37 DATA23 36
DKEN 35
RESERVED 34
DVDD 33
DGND
64 DATA0
63 DATA1
62 DATA2
61 DATA3
60 DATA4
59 DATA5
58 IDCK+
57 IDCK-
56 DATA6
55 DATA7
54 DATA8
53 DATA9
52 DATA10
51 DATA11
50 NC
49
PAD
65
J2
Female HEADER 28x2
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56
R38
NO STUFF
RN4 RESAR_IS_4/SM
1 2 3 4
8 7 6 5
R12
10K
12
R200
12
R32 0-NO-STUFF
12
R40
NO STUFF
R18
10K
12
+
C6
22uF
1
2
C9
0.1uF
www.ti.com Panel Bus digital transmitter: TFP410
A.2 Panel Bus digital transmitter: TFP410
Figure A-2. Panel Bus digital transmitter: TFP410
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CAPS for U4
Same guidlines as
for U1 power pins on page 1
Place it cloase to J3
The data (R, G, and B), control, and clock
lines (going to resistor arrays) should all be
of equal length in order to prevent any skew
being introduced between clock and data.
GND
RXIN0-
RXIN0+
RXIN1-
RXIN1+
RXIN2-
RXIN2+
RXIN3+
RXIN3-
RXCLKIN+
RXCLKIN-
G6
G7
B0
B1
B2
B3
B4
B5
B6
HS
R2
VS
R3
DE
R4
B7
R5
PCLK
R6
R7
G1
G2
G3
G4
G5
VSS
RXIN0-
RXIN1-
RXIN2-
RXCLKIN-
RXIN3-
RXIN0+
RXIN1+
RXIN2+
RXCLKIN+
RXIN3+
VSS
VCC
GND
VDD_3.3V
VCC
LVDSVCC
PLLVCC
PDN
PDN
GND
VCC
R0
VDD_3.3V
VSS
PLL_GND
LVDS_GND
VSS
R1
//G0
//G1
//R0
//R0
//G1
//G0
LVDS_GND
LVDSVCC
VDD_3.3V
VSS
PLLVCC
PLL_GND
VDD_3.3V
VSS
G0
3.3V
VSS
R0
R1
R2
R3
R4
R5
R6
R7
G5
G6
G7
G0
G1
G2
G3
G4
B4
B5
B6
B7
B0
B1
B2
B3
HS
VS
DE
PCLK
R29
100
+
C24
22uF
1
2
R26 0-NO STUFF
12
RN8
RESAR_IS_4/SM
1
2
3
4
8
7
6
5
R31
100
R28
100
RN6RESAR_IS_8/SM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB5
600ohm,250mA
U4
DS90CF386
PDN
25
RXCLKOUT 26
RXIN0-
9RXIN0+
10
RXIN1-
11 RXIN1+
12
RXIN2-
15 RXIN2+
16
RXIN3-
19 RXIN3+
20
RXCLKIN-
17 RXCLKIN+
18
RXOUT0 27
RXOUT1 29
RXOUT2 30
RXOUT3 32
RXOUT4 33
RXOUT5 34
RXOUT6 35
RXOUT7 37
RXOUT8 38
RXOUT9 39
RXOUT10 41
RXOUT11 42
RXOUT12 43
RXOUT13 45
RXOUT14 46
RXOUT15 47
RXOUT16 49
RXOUT17 50
RXOUT18 51
RXOUT19 53
RXOUT20 54
RXOUT21 55
RXOUT22 1
RXOUT23 2
RXOUT24 3
RXOUT25 5
RXOUT26 6
RXOUT27 7
LVDSVCC
13
PLLVCC
23
PLLGND
22
PLLGND
24
LVDSGND
8
LVDSGND
14
LVDSGND
21
VCC
31
VCC
40
VCC
48
VCC
56
GND
4
GND
28
GND
36
GND
44
GND
52
RN7RESAR_IS_8/SM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
J3HEADER 10X2
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
JP2
1
2
3
FB6
600ohm,250mA
+
C26
22uF
1
2
C20
0.1uF
R2
10k
1
2
R27
100
R30
100
+
C25
22uF
1
2
RN5RESAR_IS_8/SM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C19
0.1uF
C21
0.1uF
FB4
600ohm,250mA
LVDS Receiver: DS90CF386 www.ti.com
A.3 LVDS Receiver: DS90CF386
Figure A-3. LVDS Receiver: DS90CF386
16 Board Schematic SNLU144–may 2013
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VDD_3.3V
VSS
VDD12Vmax
VDD_3.3V
VSS
+5V
SCL
SDA
Clock-
Clock_Shiled
Clock+
Data0-
Data0_Shield
Data0+
Data1-
Data1_Shield
Data1+
Data2-
VSS
Data2+
VDD_3.3V VSS
SCL SDA
SDA
DSEL/SDA
DDC_DDDC_C
BSEL/SCL
SCL
HOT_PLUG
VSS
EDGE/HTPLG
+5V
VSS
+5V
VDD_3.3V
HOT_PLUG
DDC_D
CEC
DDC_C
VSS
Data2_Shield
VDD_3.3V
VSS
VDD_3.3V
VSS
VSS
Data2+
Data2-
Data2_Shield
Data1_Shield
Data0_Shield
Clock_Shield
DDC_GND
Data1+
Data1-
Clock+
Clock-
CEC
DDC_D
DDC_C
+5V
HOT_PLUG
Data0+
Data0-
3.3V
VSS
DSEL/SDABSEL/SCL
EDGE/HTPLG
C-
C+
0-
0+
1-
1+
2-
2+
JP3
1 2 3
R35
NO STUFF
1
2
U3
DIP8 SOCKET(PCF8582C-2)
1
1
2
2
3
3
4
4
88
77
66
55
+
C23
10uF
1
2
TP3
1
J5
3.3V
1 2 3 4
R3
4.7K
1
2
Q1
BSS123
+
C1
22uF
1
2
TP2
1
R6
220
1
2
R25
4.7K
0603
1
2
D4
U6
REG1117-3.3/SOT
VIN
3VOUT 2
GND
1
Tab 4
JP7
1 2
J7
HEADER 4
1 2 3 4
U2
TPD4E001
IO1
1
IO4 5
VCC 6
IO3 4
IO2
2
GND
3
U7
TPD8S009
VCC
13
D3- 12
GND 11
D3+ 10
D0+ 1
GND 5
D1- 6
D2+ 7
GND 8
NC
14
D1+ 4
GND 2
VCC
15
D0- 3
D2- 9
C11
0.1uF
R19
4.7K
0603
1
2
J6
CONN JACK PWR
3
2
1
C4
0.1uF
JP5
1 2 3
C13
0.1uF
R4
1K_NO_STUFF
1 2
+
C2
10uF
1
2
D1
LED
R1220
1
2
C14
0.1uF
C22
1.0uF
U8
TPS76950-Q1
IN
1OUT 5
GND
2
EN
3NC 4
+
C5
10uF
1
2
C27
0.1uF
+
C3
10uF
1
2
D2
LED
TP1
1
J1
12V
1
2
3
4
JP4
1 2 3
J4
HDMI Type A 732-2737-2-ND
DAT2+
1
DAT2_S
2
DAT2-
3
DAT1+
4
DAT1_S
5
DAT1-
6
DAT0+
7
DAT0_S
8
DAT0-
9
CLK+
10 CLK_S
11
CLK-
12
CEC 13
NC 14
SCL
15
SDA
16
DDC/CEC GND
17 +5V
18
HPLG
19
D3
www.ti.com Power and ESD
A.4 Power and ESD
Figure A-4. Power and ESD
17
SNLU144–may 2013 Board Schematic
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18 Board Schematic SNLU144–may 2013
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Appendix B
SNLU144–may 2013
Bill of Materials
B.1 FPD23DAEVM BOM
Table B-1. Bill of Material for FPD23DAEVM
PCB
Qty Reference Part Digi-Key P/N Comments
Footprint
1 C1 22uF 2917 493-2391-2-ND CAP TANT 22UF 25V 20% 2917
3 C2, C3, C5 10uF 2312 718-1044-1-ND CAP TANT 10UF 25V 20% 2312
CAP CER 0.1UF 25V 10% X7R
1 C4 0.1uF 0805 478-3755-1-ND 0805
C6, C10, C12, C24, C25,
6 22uF 1206 718-1473-1-ND CAP TANT 22UF 10V 10% SMD
C26
C7, C8, C9, C19, C20,
7 0.1uF 0201 445-1796-1-ND CAP CER .1UF 6.3V X5R 10% 0201
C21, C27
4 C11, C13, C14, C16 0.1uF 0603 490-4779-1-ND CAP CER .1UF 50V X7R 0603
CAP CERAMIC .01UF 100V X7R
1 C15 0.01uF 0603 399-3189-1-ND 0603
1 C17 10uF 0612 445-4072-1-ND CAP CER 10UF 6.3V X5R 0612
2 C18, C22 1.0uF 0402 PCC2364CT-ND CAP CERAMIC 1UF 10V X5R 0402
1 C23 10uF 2312 718-1044-1-ND CAP TANT 10UF 25V 20% 2312
LED GREEN CLEAR THIN 0603
1 D1 LED Green 0603_LED 160-1443-2-ND SMD
LED SUPER RED CLR THIN 0603
1 D2 LED Red 0603_LED 160-1447-2-ND SMD
DIODE MBRA210LT3GOSTR-
2 D3, D4 SMA DIODE SCHOTTKY 10V 2A SMA
SCHOTTKY ND
FB1, FB2, FB3, FB4, FB5, 600ohm,250
6 0402 587-1839-1-ND FERRITE BEAD 600 OHM 0402
FB6 mA
JP1, JP2, JP3, JP4, JP5, CONN HEADER VERT .100 3POS
6 3-Pin Header Header_3P A26545-ND
JP6 15AU
CONN HEADER VERT .100 2POS
1 JP7 JUMPER Header_2P A26542-ND 30AU
CONN HEADER 4POS .100 VERT
1 J1 12V Header Header_4P WM2702-ND GOLD
Female HEADER_28 CONN HEADER FMAL 56PS .1" DL
1 J2 HEADER S7096-ND
X2_F TIN
28x2
HEADER HEADER_10 CONN RECEPT 20POS .100 VERT
1 J3 A26460-ND
10X2 X2_F DUAL
CONN HDMI RECPT 19POS SMT
1 J4 HDMI Type A HDMIconn 609-4614-2-ND R/A
CONN HEADER 4POS .100 VERT
1 J5 3.3V Header Header_4P WM2702-ND GOLD
CONN JACK DC_PWR_JA
1 J6 CP-002A-ND CONN POWER JACK 2.1MM
PWR CK CONN HEADER 4POS .100 VERT
1 J7 HEADER 4 Header_4P WM2702-ND GOLD
1 L1 2.2uH 1007 587-1954-2-ND INDUCTOR 2.2UH 20% 1007 SMD
19
SNLU144–may 2013 Bill of Materials
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FPD23DAEVM BOM www.ti.com
Table B-1. Bill of Material for FPD23DAEVM (continued)
PCB
Qty Reference Part Digi-Key P/N Comments
Footprint
BSS123LT1GOSTR- MOSFET N-CH 100V 170MA SOT-
1 Q1 BSS123 SOT_23 ND 23
(#1) RN1, RN2, RN3 RESAR_IS_8/ RES ARRAY ZERO OHM 8 RES
3 RN_1506 Y1000TR-ND
(#2) RN5, RN6, RN7 SM 1506
(#1) RN4 RESAR_IS_4/ RES ARRAY ZERO OHM 4 RES
1 RN_0804 Y7000TR-ND
(#2) RN8 SM 0804
220 OHM 1/10W 5% 0402
1 R1 220 0402 P220JTR-ND RES SMDSMD
R2, R10, R11, R12, R14, RES 10K OHM 1/10W 5% 0402
8 10K 0402 P10KJCT-ND
R17, R18, R36 SMD
RES 4.7K OHM 1/10W 5% 0402
1 R3 4.7K 0402 P4.7KJTR-ND SMD SMD
2 R4(NO STUFF), R13 1K 0402 P1.0KJTR-ND RES 1K OHM 1/10W 5% 0402 SMD
RES 510 OHM 1/10W 1% 0402
1 R5 510 0402 P510LCT-ND SMD
RES 220 OHM 1/10W 5% 0402
1 R6 220 0402 P220JTR-ND SMD SMD
RES ZERO OHM 1/16W 5% 0402
5 R7, R20, R21, R24, R34 0 0402 P0.0JTR-ND SMD.
ADJ-NO-
1 R8 603 NO STUFF 0603 SMD- DO NOT STUFF
STUFF RES 5.1K OHM 1/10W 5% 0402
3 R9, R15, R16 5.1K 0402 P5.1KJTR-ND SMD
RES 4.7K OHM 1/10W 5% 0603
2 R19, R25 4.7K 0603 P4.7KGCT-ND SMD
RES 22.0 OHM 1/10W 1% 0402
2 R22, R23 22 0402 P22.0LCT-ND SMD
1 R26 0-NO STUFF 0603 NO STUFF 0603 SMD- DO NOT STUFF
RES 100 OHM 1/10W 5% 0402
5 R27, R28, R29, R30, R31 100 0402 P100JTR-ND SMD
RES ZERO OHM 5% 0402 SMD -
2 R32, R33 0-NO-STUFF 0402 P0.0JTR-ND DO NOT STUFF
1 R35 NO STUFF 0603 NO STUFF 0603 SMD NO STUFF
4 R37, R38, R39, R40 NO STUFF 0201 P100AGTR-ND 0201 SMD- DO NOT STUFF
DIP_SW_10P SWITCH DIP EXTENDED UNSEAL
1 S1 SW GH7195-ND
OS 10POS
TEST POINT PC MULTI PURPOSE
4 TP1, TP2, TP3, TP4 NO STUFF TEST_POINT 5010K-ND RED
IC TRANSMITTER DIGITAL 64-
1 U1 TFP410 64L_TQFP 296-12666-ND HTQFP
1 U2 TPD4E001 6_USON 296-30280-2-ND IC ESD-PROT ARRAY 4CH 6USON
DIP8 (for SOCKET IC OPEN FRAME 8POS
1 U3 DIP8 3M5473-ND
PCF8582C-2) .3"
IC RCVR LVDS FPD 24BIT 56-
1 U4 DS90CF386 56_TSSOP DS90CF386MTD TSSOP
IC CLK FREQ MULTI/ZDB 2OUT
1 U5 CY2302 8_SOIC 428-2188-5-ND 8SOIC
REG1117-
1 U6 TO_263_4 296-15941-2-ND IC REG LDO 3.3V .8A D2PAK-3
3.3/SOT
1 U7 TPD8S009 15_SON 296-23829-2-ND IC 8CH ESD PROTECTION 15-SON
TPS76950-
1 U8 SOT_23_5 296-2761-2-ND IC REG LDO 5V .1A SOT-23-5
Q1
20 Bill of Materials SNLU144–may 2013
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