Texas Instruments TMS320C6A816 Series Product manual

Preliminary
TMS320C6A816x C6-Integra
DSP+ARM Processors
Technical Reference Manual
Literature Number: SPRUGX9
15 April 2011

Preliminary
2SPRUGX9–15 April 2011
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Contents
Preface ...................................................................................................................................... 91
1 Chip Level Resources ........................................................................................................ 93
1.1 Introduction ................................................................................................................. 94
1.2 MPU Subsystem ........................................................................................................... 94
1.2.1 Introduction ........................................................................................................ 94
1.2.2 Features ........................................................................................................... 95
1.2.3 MPU Subsystem Integration .................................................................................... 96
1.2.4 MPU Subsystem Clock and Reset Distribution ............................................................... 98
1.2.5 ARM Subchip .................................................................................................... 101
1.2.6 AXI2OCP and I2Async Bridges ............................................................................... 102
1.2.7 Interrupt Controller .............................................................................................. 104
1.2.8 Power Management ............................................................................................ 104
1.2.9 Host ARM Address Map ....................................................................................... 107
1.2.10 ARM Programming Model .................................................................................... 107
1.3 C674x DSP Subsystem ................................................................................................. 109
1.3.1 Introduction ...................................................................................................... 109
1.3.2 Key Features .................................................................................................... 110
1.3.3 DSP Subsystem Functional Description ..................................................................... 111
1.3.4 TMS320C674x Megamodule .................................................................................. 112
1.3.5 Advanced Event Triggering (AET) ............................................................................ 116
1.4 System MMU ............................................................................................................. 117
1.4.1 MMU Overview .................................................................................................. 117
1.4.2 MMU Intergration ................................................................................................ 117
1.4.3 MMU Functional Description .................................................................................. 118
1.4.4 MMU Low-level Programming Models ....................................................................... 130
1.4.5 MMU Registers .................................................................................................. 133
1.5 SGX530 Graphics Subsystem .......................................................................................... 145
1.5.1 SGX Overview ................................................................................................... 145
1.5.2 SGX Integration ................................................................................................. 148
1.5.3 SGX Functional Description ................................................................................... 150
1.5.4 SGX Registers ................................................................................................... 152
1.6 HD Video Processing Subsystem (HDVPSS) ........................................................................ 167
1.6.1 Features Supported ............................................................................................. 167
1.7 System Memory Map .................................................................................................... 170
1.8 Device Interrupts ......................................................................................................... 171
1.8.1 Interrupt Requests to Cortex-A8 MPU INTC ................................................................ 171
1.8.2 Interrupt Requests to Media Controller INTC ............................................................... 174
1.8.3 Interrupt Requests to DSP INTC .............................................................................. 176
1.9 EDMA and EDMA Events ............................................................................................... 179
1.9.1 Overview ......................................................................................................... 179
1.9.2 EDMA Regions .................................................................................................. 179
1.9.3 Synchronization Events ........................................................................................ 179
1.10 Device Clocking and Flying Adder PLL ............................................................................... 182
1.10.1 Overview ........................................................................................................ 182
1.10.2 I/O Domains .................................................................................................... 186
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1.10.3 Flying Adder PLL ............................................................................................... 187
1.10.4 Clock Out ....................................................................................................... 198
1.11 Bus Interconnect ......................................................................................................... 199
1.11.1 Terminology ..................................................................................................... 199
1.11.2 L3 Interconnect ................................................................................................. 199
1.12 Inter-Processor Communication ....................................................................................... 205
1.12.1 Reset Requirements ........................................................................................... 205
1.12.2 Features ......................................................................................................... 205
1.12.3 Overview and Strategy ........................................................................................ 206
1.12.4 IPC Component Configuration ............................................................................... 208
1.13 Mailbox .................................................................................................................... 209
1.13.1 Overview ........................................................................................................ 209
1.13.2 System Mailbox Integration ................................................................................... 209
1.13.3 Functional Description ......................................................................................... 210
1.13.4 Programming Guide ........................................................................................... 214
1.13.5 Mailbox Registers .............................................................................................. 217
1.14 Spinlock ................................................................................................................... 237
1.14.1 Overview ........................................................................................................ 237
1.14.2 Integration ....................................................................................................... 238
1.14.3 Functional Description ......................................................................................... 239
1.14.4 Programming Guide ........................................................................................... 241
1.14.5 Spinlock Registers ............................................................................................. 243
1.15 Error Location Module ................................................................................................... 247
1.15.1 Error Location Module Overview ............................................................................. 247
1.15.2 ELM Integration ................................................................................................ 248
1.15.3 ELM Functional Description .................................................................................. 249
1.15.4 ELM Basic Programming Model ............................................................................. 252
1.15.5 ELM Registers .................................................................................................. 258
1.16 Control Module ........................................................................................................... 270
1.16.1 Registers ........................................................................................................ 270
1.17 Interrupt Controller ....................................................................................................... 329
1.18 Resets ..................................................................................................................... 330
2 DMM/TILER ..................................................................................................................... 331
2.1 Introduction ............................................................................................................... 332
2.1.1 Overview ......................................................................................................... 332
2.1.2 Features .......................................................................................................... 333
2.1.3 Functional Block Diagram ...................................................................................... 333
2.1.4 Terminologies and Acronyms Used in this Document ..................................................... 334
2.2 Architecture ............................................................................................................... 335
2.2.1 DMM Functional Description .................................................................................. 335
2.2.2 TILER Functional Description ................................................................................. 346
2.3 Use Case .................................................................................................................. 370
2.3.1 DMM Basic Register Setup .................................................................................... 370
2.3.2 Simple LUT Bypass Use Case: Arrangement of Video Buffers ........................................... 371
2.3.3 LUT Refill Using the PAT Refill Engines ..................................................................... 373
2.3.4 Address Management Using LISA Sections ................................................................ 380
2.4 Registers .................................................................................................................. 385
2.4.1 DMM Revision Register: DMM_REVISION .................................................................. 385
2.4.2 DMM Clock Management Configuration: DMM_SYSCONFIG ............................................ 386
2.4.3 LISA Configuration Locking Register: DMM_LISA_LOCK ................................................. 386
2.4.4 DMM LISA MAP Registers: DMM_LISA_MAP_0-DMM_LISA_MAP_3 .................................. 387
2.4.5 DMM TILER Orientation Registers: DMM_TILER_OR0-DMM_TILER_OR1 ............................ 388
2.4.6 DMM PAT Configuration Register: DMM_PAT_CONFIG .................................................. 388
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2.4.7 DMM PAT View Registers: DMM_PAT_VIEW_0-DMM_PAT_VIEW_2 ................................. 389
2.4.8 DMM View Map Registers: DMM_PAT_VIEW_MAP_0-DMM_PAT_VIEW_MAP_4 ................... 390
2.4.9 DMM PAT View Mapping Base Address Register: DMM_PAT_VIEW_MAP_BASE .................. 391
2.4.10 DMM PAT End of Interrupt Register: DMM_PAT_IRQ_EOI ............................................. 391
2.4.11 DMM PAT Raw Interrupt Status Register: DMM_PAT_IRQSTATUS_RAW ........................... 393
2.4.12 DMM PAT Interrupt Status Register: DMM_PAT_IRQSTATUS ......................................... 395
2.4.13 DMM PAT Interrupt Enable Register: DMM_PAT_IRQENABLE_SET .................................. 397
2.4.14 DMM PAT Interrupt Disable Register: DMM_PAT_IRQENABLE_CLR ................................. 399
2.4.15 DMM PAT Status Registers: DMM_PAT_STATUS_0-DMM_PAT_STATUS_3 ....................... 401
2.4.16 DMM PAT Descriptor Registers: DMM_PAT_DESCR_0-DMM_PAT_DESCR_3 ..................... 402
2.4.17 DMM PAT Area Geometry Registers: DMM_PAT_AREA_0-DMM_PAT_AREA_3 ................... 402
2.4.18 DMM PAT Control Registers: DMM_PAT_CTRL_0-DMM_PAT_CTRL_3 ............................. 403
2.4.19 DMM PAT Area Entry Data Registers: DMM_PAT_DATA_0-DMM_PAT_DATA_3 .................. 403
2.4.20 DMM PEG Priority Registers: DMM_PEG_PRIO_0-DMM_PEG_PRIO_1 ............................. 404
2.4.21 DMM PEG Priority Registers for PAT: DMM_PEG_PRIO_PAT ......................................... 404
3 EMAC/MDIO Module ......................................................................................................... 405
3.1 Introduction ............................................................................................................... 406
3.1.1 Overview ......................................................................................................... 406
3.1.2 Features .......................................................................................................... 406
3.1.3 Functional Block Diagram ...................................................................................... 407
3.1.4 EMAC and MDIO Block Diagram ............................................................................. 407
3.1.5 Industry Standard(s) Compliance Statement ................................................................ 408
3.1.6 List of Terms ..................................................................................................... 408
3.2 Architecture ............................................................................................................... 410
3.2.1 Clock Control .................................................................................................... 410
3.2.2 Memory Map ..................................................................................................... 410
3.2.3 Signal Descriptions ............................................................................................. 411
3.2.4 Ethernet Protocol Overview .................................................................................... 413
3.2.5 Programming Interface ......................................................................................... 414
3.2.6 EMAC Control Module .......................................................................................... 425
3.2.7 MDIO Module .................................................................................................... 428
3.2.8 EMAC Module ................................................................................................... 432
3.2.9 Media Independent Interface (MII) ............................................................................ 435
3.2.10 Packet Receive Operation .................................................................................... 439
3.2.11 Packet Transmit Operation ................................................................................... 444
3.2.12 Receive and Transmit Latency ............................................................................... 444
3.2.13 Transfer Node Priority ......................................................................................... 445
3.2.14 Reset Considerations .......................................................................................... 445
3.2.15 Initialization ..................................................................................................... 446
3.2.16 Interrupt Support ............................................................................................... 450
3.2.17 Power Management ........................................................................................... 454
3.2.18 Emulation Considerations ..................................................................................... 454
3.3 Registers .................................................................................................................. 455
3.3.1 EMAC Control Module Registers ............................................................................. 455
3.3.2 Ethernet Media Access Controller (EMAC) Registers ...................................................... 465
3.3.3 MDIO Registers ................................................................................................. 514
4 General-Purpose I/O (GPIO) Interface ................................................................................. 527
4.1 Introduction ............................................................................................................... 528
4.1.1 Purpose of the Peripheral ...................................................................................... 528
4.1.2 Features .......................................................................................................... 528
4.1.3 Block Diagram ................................................................................................... 529
4.2 Architecture ............................................................................................................... 530
4.2.1 Operating Modes ................................................................................................ 530
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4.2.2 Clocking and Reset Strategy .................................................................................. 530
4.2.3 Interrupt Features ............................................................................................... 531
4.2.4 General-Purpose Interface Basic Programming Model .................................................... 533
4.3 Registers .................................................................................................................. 537
4.3.1 GPIO_REVISION Register .................................................................................... 538
4.3.2 GPIO_SYSCONFIG Register ................................................................................. 539
4.3.3 GPIO_EOI Register ............................................................................................. 540
4.3.4 GPIO_IRQSTATUS_RAW_n Register ....................................................................... 541
4.3.5 GPIO_IRQSTATUS_n Register ............................................................................... 541
4.3.6 GPIO_IRQSTATUS_SET_n Register ........................................................................ 542
4.3.7 GPIO_IRQSTATUS_CLR_n Register ........................................................................ 542
4.3.8 GPIO_SYSSTATUS Register ................................................................................. 543
4.3.9 GPIO_CTRL Register .......................................................................................... 544
4.3.10 GPIO_OE Register ............................................................................................ 544
4.3.11 GPIO_DATAIN Register ...................................................................................... 545
4.3.12 GPIO_DATAOUT Register ................................................................................... 545
4.3.13 GPIO_LEVELDETECT0 Register ............................................................................ 546
4.3.14 GPIO_LEVELDETECT1 Register ............................................................................ 546
4.3.15 GPIO_RISINGDETECT Register ............................................................................ 547
4.3.16 GPIO_FALLINGDETECT Register .......................................................................... 547
4.3.17 GPIO_DEBOUNCENABLE Register ........................................................................ 548
4.3.18 GPIO_DEBOUNCINGTIME Register ........................................................................ 548
4.3.19 GPIO_CLEARDATAOUT Register .......................................................................... 549
4.3.20 GPIO_SETDATAOUT Register .............................................................................. 549
5 General-Purpose Memory Controller (GPMC) ...................................................................... 551
5.1 Introduction ............................................................................................................... 552
5.1.1 Overview ......................................................................................................... 552
5.1.2 Block Diagram ................................................................................................... 552
5.2 Architecture ............................................................................................................... 554
5.2.1 GPMC Signals ................................................................................................... 554
5.2.2 GPMC Modes ................................................................................................... 556
5.2.3 GPMC Integration ............................................................................................... 558
5.2.4 GPMC Functional Description ................................................................................. 559
5.3 Basic Programming Model .............................................................................................. 633
5.3.1 GPMC High-Level Programming Model Overview ......................................................... 633
5.3.2 GPMC Initialization ............................................................................................. 635
5.3.3 GPMC Configuration in NOR Mode .......................................................................... 636
5.3.4 GPMC Configuration in NAND Mode ......................................................................... 637
5.3.5 Set Memory Access ............................................................................................ 639
5.3.6 GPMC Timing Parameters ..................................................................................... 640
5.4 Use Cases And Tips ..................................................................................................... 651
5.4.1 How to Set GPMC Timing Parameters for Typical Accesses ............................................. 651
5.4.2 How to Choose a Suitable Memory to Use With the GPMC .............................................. 659
5.5 Registers .................................................................................................................. 663
5.5.1 GPMC_REVISION .............................................................................................. 664
5.5.2 GPMC_SYSCONFIG ........................................................................................... 664
5.5.3 GPMC_SYSSTATUS ........................................................................................... 665
5.5.4 GPMC_IRQSTATUS ........................................................................................... 666
5.5.5 GPMC_IRQENABLE ........................................................................................... 667
5.5.6 GPMC_TIMEOUT_CONTROL ................................................................................ 668
5.5.7 GPMC_ERR_ADDRESS ....................................................................................... 668
5.5.8 GPMC_ERR_TYPE ............................................................................................. 669
5.5.9 GPMC_CONFIG ................................................................................................ 670
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5.5.10 GPMC_STATUS ............................................................................................... 671
5.5.11 GPMC_CONFIG1_i ............................................................................................ 672
5.5.12 GPMC_CONFIG2_i ............................................................................................ 675
5.5.13 GPMC_CONFIG3_i ............................................................................................ 676
5.5.14 GPMC_CONFIG4_i ............................................................................................ 678
5.5.15 GPMC_CONFIG5_i ............................................................................................ 680
5.5.16 GPMC_CONFIG6_i ............................................................................................ 681
5.5.17 GPMC_CONFIG7_i ............................................................................................ 682
5.5.18 GPMC_NAND_COMMAND_i ................................................................................ 683
5.5.19 GPMC_NAND_ADDRESS_i .................................................................................. 683
5.5.20 GPMC_NAND_DATA_i ....................................................................................... 683
5.5.21 GPMC_PREFETCH_CONFIG1 .............................................................................. 684
5.5.22 GPMC_PREFETCH_CONFIG2 .............................................................................. 686
5.5.23 GPMC_PREFETCH_CONTROL ............................................................................. 686
5.5.24 GPMC_PREFETCH_STATUS ............................................................................... 687
5.5.25 GPMC_ECC_CONFIG ........................................................................................ 688
5.5.26 GPMC_ECC_CONTROL ..................................................................................... 689
5.5.27 GPMC_ECC_SIZE_CONFIG ................................................................................. 690
5.5.28 GPMC_ECCj_RESULT ....................................................................................... 692
5.5.29 GPMC_BCH_RESULT0_i .................................................................................... 693
5.5.30 GPMC_BCH_RESULT1_i .................................................................................... 693
5.5.31 GPMC_BCH_RESULT2_i .................................................................................... 693
5.5.32 GPMC_BCH_RESULT3_i .................................................................................... 694
5.5.33 GPMC_BCH_SWDATA ....................................................................................... 694
5.5.34 GPMC_BCH_RESULT4_i .................................................................................... 694
5.5.35 GPMC_BCH_RESULT5_i .................................................................................... 695
5.5.36 GPMC_BCH_RESULT6_i .................................................................................... 695
6 High-Definition Multimedia Interface (HDMI) ........................................................................ 697
6.1 Introduction ............................................................................................................... 698
6.1.1 Overview ......................................................................................................... 698
6.1.2 Main Features ................................................................................................... 698
6.1.3 Functional Block Diagram ...................................................................................... 699
6.1.4 Video Formats and Timings ................................................................................... 699
6.1.5 Environment ..................................................................................................... 701
6.2 Architecture ............................................................................................................... 702
6.2.1 Clock Configuration ............................................................................................. 702
6.2.2 Signals ............................................................................................................ 703
6.2.3 Integration ........................................................................................................ 703
6.2.4 Software Reset .................................................................................................. 703
6.2.5 Power Management ............................................................................................ 705
6.2.6 Interrupt Requests .............................................................................................. 706
6.2.7 DMA Requests .................................................................................................. 706
6.2.8 HDCP Key Interface ............................................................................................ 706
6.2.9 Wrapper Functions .............................................................................................. 706
6.2.10 TXPHY Functions .............................................................................................. 716
6.2.11 Programming Video Input Mode and Video Output Mode ................................................ 717
6.3 Registers .................................................................................................................. 718
6.3.1 HDMI_WP Register Descriptions ............................................................................. 718
6.3.2 HDMI_IP_CORE_SYSTEM Register Descriptions ......................................................... 734
6.3.3 HDMI_IP_CORE_GAMUT Register Descriptions .......................................................... 808
6.3.4 HDMI_IP_CORE_AUDIO_VIDEO Register Descriptions .................................................. 811
6.3.5 HDMI_IP_CORE_CEC Register Descriptions ............................................................... 834
6.3.6 HDMI_PHY Register Descriptions ............................................................................ 843
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7 Inter-Integrated Circuit (I2C) Controller Module ................................................................... 845
7.1 Introduction ............................................................................................................... 846
7.1.1 Overview ......................................................................................................... 846
7.1.2 Functional Block Diagram ...................................................................................... 846
7.1.3 Features .......................................................................................................... 846
7.2 Architecture ............................................................................................................... 847
7.2.1 I2C Master/Slave Contoller Signals .......................................................................... 847
7.2.2 I2C Reset ........................................................................................................ 848
7.2.3 Data Validity ..................................................................................................... 848
7.2.4 START & STOP Conditions ................................................................................... 849
7.2.5 I2C Operation .................................................................................................... 849
7.2.6 Arbitration ........................................................................................................ 851
7.2.7 I2C Clock Generation and I2C Clock Synchronization ..................................................... 851
7.2.8 Prescaler (SCLK/ICLK) ......................................................................................... 852
7.2.9 Noise Filter ....................................................................................................... 852
7.2.10 I2C Interrupts ................................................................................................... 852
7.2.11 DMA Events .................................................................................................... 853
7.2.12 Interrupt and DMA Events .................................................................................... 853
7.2.13 FIFO Management ............................................................................................. 853
7.2.14 How to Program I2C ........................................................................................... 857
7.3 Registers .................................................................................................................. 858
7.3.1 Module Revision Register (LOW BYTES) (I2C_REVNB_LO) ............................................. 859
7.3.2 Module Revision Register (HIGH BYTES) (I2C_REVNB_HI) ............................................. 860
7.3.3 System Configuration Register (I2C_SYSC) ................................................................ 861
7.3.4 I2C End of Interrupt Register (I2C_EOI) ..................................................................... 862
7.3.5 I2C Status Raw Register (I2C_IRQSTATUS_RAW) ....................................................... 862
7.3.6 I2C Status Register (I2C_IRQSTATUS) ..................................................................... 867
7.3.7 I2C Interrupt Enable Set Register (I2C_IRQENABLE_SET) .............................................. 869
7.3.8 I2C Interrupt Enable Clear Register (I2C_IRQENABLE_CLR) ........................................... 871
7.3.9 I2C Wakeup Enable Register (I2C_WE) ..................................................................... 873
7.3.10 Receive DMA Enable Set Register (I2C_DMARXENABLE_SET) ...................................... 876
7.3.11 Transmit DMA Enable Set Register (I2C_DMATXENABLE_SET) ...................................... 876
7.3.12 Receive DMA Enable Clear Register (I2C_DMARXENABLE_CLR) .................................... 877
7.3.13 Transmit DMA Enable Clear Register (I2C_DMATXENABLE_CLR) ................................... 877
7.3.14 Receive DMA Wakeup Register (I2C_DMARXWAKE_EN) .............................................. 878
7.3.15 Transmit DMA Wakeup Register (I2C_DMATXWAKE_EN) .............................................. 880
7.3.16 System Status Register (I2C_SYSS) ........................................................................ 882
7.3.17 Buffer Configuration Register (I2C_BUF) ................................................................... 882
7.3.18 Data Counter Register (I2C_CNT) ........................................................................... 884
7.3.19 Data Access Register (I2C_DATA) .......................................................................... 885
7.3.20 I2C Configuration Register (I2C_CON) ..................................................................... 886
7.3.21 I2C Own Address Register (I2C_OA) ....................................................................... 888
7.3.22 I2C Slave Address Register (I2C_SA) ...................................................................... 889
7.3.23 I2C Clock Prescaler Register (I2C_PSC) ................................................................... 890
7.3.24 I2C SCL Low Time Register (I2C_SCLL) ................................................................... 891
7.3.25 I2C SCL High Time Register (I2C_SCLH) .................................................................. 891
7.3.26 System Test Register (I2C_SYSTEST) ..................................................................... 892
7.3.27 I2C Buffer Status Register (I2C_BUFSTAT) ............................................................... 895
7.3.28 Own Address 1 (OA1) (I2C_OA1) ........................................................................... 896
7.3.29 I2C Own Address 2 Register (I2C_OA2) ................................................................... 897
7.3.30 I2C Own Address 3 Register (I2C_OA3) ................................................................... 898
7.3.31 Active Own Address Register (I2C_ACTOA) ............................................................... 899
7.3.32 I2C Clock Blocking Enable Register (I2C_SBLOCK) ..................................................... 900
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8 Interrupt Controller .......................................................................................................... 901
8.1 Introduction ............................................................................................................... 902
8.1.1 Overview ......................................................................................................... 902
8.1.2 Functional Block Diagram ...................................................................................... 902
8.1.3 Environment ..................................................................................................... 902
8.1.4 ARM A8—Interrupt Controller Integration .................................................................... 904
8.2 Architecture ............................................................................................................... 905
8.2.1 Clocking and Reset ............................................................................................. 905
8.2.2 Interrupt Request Lines ........................................................................................ 905
8.2.3 Interrupt Processing ............................................................................................ 905
8.2.4 Module Power Saving .......................................................................................... 907
8.2.5 Error Handling ................................................................................................... 907
8.2.6 Interrupt Latency ................................................................................................ 907
8.3 Basic Programming Model .............................................................................................. 908
8.3.1 Initialization Sequence ......................................................................................... 908
8.3.2 INTC Processing Sequence ................................................................................... 908
8.3.3 INTC Preemptive Processing Sequence ..................................................................... 912
8.3.4 Interrupt Preemption ............................................................................................ 916
8.3.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. 916
8.4 Registers .................................................................................................................. 917
8.4.1 INTCPS_REVISION Register ................................................................................. 918
8.4.2 INTCPS_SYSCONFIG Register .............................................................................. 918
8.4.3 INTCPS_SYSSTATUS Register .............................................................................. 919
8.4.4 INTCPS_SIR_IRQ Register ................................................................................... 919
8.4.5 INTCPS_SIR_FIQ Register .................................................................................... 920
8.4.6 INTCPS_CONTROL Register ................................................................................. 920
8.4.7 INTCPS_PROTECTION Register ............................................................................. 921
8.4.8 INTCPS_IDLE Register ........................................................................................ 921
8.4.9 INTCPS_IRQ_PRIORITY Register ........................................................................... 922
8.4.10 INTCPS_FIQ_PRIORITY Register .......................................................................... 922
8.4.11 INTCPS_THRESHOLD Register ............................................................................ 923
8.4.12 INTCPS_ITR0-3 Registers .................................................................................... 923
8.4.13 INTCPS_MIR0-3 Registers ................................................................................... 924
8.4.14 INTCPS_MIR_CLEAR0-3 Registers ........................................................................ 924
8.4.15 INTCPS_MIR_SET0-3 Registers ............................................................................ 924
8.4.16 INTCPS_ISR_SET0-3 Registers ............................................................................. 925
8.4.17 INTCPS_ISR_CLEAR0-3 Registers ......................................................................... 925
8.4.18 INTCPS_PENDING_IRQ0-3 Registers ..................................................................... 925
8.4.19 INTCPS_PENDING_FIQ0-3 Registers ...................................................................... 926
8.4.20 INTCPS_ILR0-127 Registers ................................................................................. 926
9 Secure Digital (SD)/Secure Digital I/O (SDIO) Card Interface .................................................. 927
9.1 Introduction ............................................................................................................... 928
9.1.1 Overview ......................................................................................................... 928
9.1.2 Features .......................................................................................................... 929
9.2 Architecture ............................................................................................................... 929
9.2.1 SD/SDIO Functional Modes ................................................................................... 929
9.2.2 Resets ............................................................................................................ 933
9.2.3 Power Management ............................................................................................ 934
9.2.4 Interrupt Requests .............................................................................................. 937
9.2.5 DMA Modes ...................................................................................................... 939
9.2.6 Buffer Management ............................................................................................. 942
9.2.7 Transfer Process ................................................................................................ 945
9.2.8 Transfer or Command Status and Error Reporting ......................................................... 946
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9.2.9 Auto Command 12 Timings .................................................................................... 950
9.2.10 Transfer Stop ................................................................................................... 952
9.2.11 Output Signals Generation ................................................................................... 953
9.2.12 Card Boot Mode Management ............................................................................... 954
9.2.13 CE-ATA Command Completion Disable Management ................................................... 955
9.2.14 Test Registers .................................................................................................. 955
9.2.15 SD/SDIO Hardware Status Features ........................................................................ 956
9.3 Low-Level Programming Models ....................................................................................... 957
9.3.1 Surrounding Modules Global Initialization ................................................................... 957
9.3.2 SD/SDIO Controller Initialization Flow ....................................................................... 957
9.3.3 Operational Modes Configuration ............................................................................. 960
9.4 Registers .................................................................................................................. 962
9.4.1 IP Revision Identifier Register (SD_HL_REV) .............................................................. 963
9.4.2 IP Module Hardware Configuration Register (SD_HL_HWINFO) ........................................ 963
9.4.3 Clock Management Configuration (SD_HL_SYSCONFIG) ................................................ 963
9.4.4 System Configuration Register (SD_SYSCONFIG) ........................................................ 964
9.4.5 System Status Register (SD_SYSSTATUS) ................................................................ 966
9.4.6 Card Status Response Error (SD_CSRE) ................................................................... 966
9.4.7 System Test Register (SD_SYSTEST) ...................................................................... 967
9.4.8 Configuration Register (SD_CON) ............................................................................ 970
9.4.9 Power Counter Register (SD_PWCNT) ...................................................................... 973
9.4.10 SDMA System Address (SD_SDMASA) .................................................................... 973
9.4.11 Transfer Length Configuration Register (SD_BLK) ........................................................ 974
9.4.12 Command Argument Register (SD_ARG) .................................................................. 975
9.4.13 Command and Transfer Mode Register (SD_CMD) ...................................................... 975
9.4.14 Command Response[31:0] Register (SD_RSP10) ........................................................ 979
9.4.15 Command Response[63:32] Register (SD_RSP32) ...................................................... 979
9.4.16 Command Response[95:64] Register (SD_RSP54) ...................................................... 980
9.4.17 Command Response[127:96] Register (SD_RSP76) ..................................................... 980
9.4.18 Data Register (SD_DATA) .................................................................................... 981
9.4.19 Present State Register (SD_PSTATE) ...................................................................... 982
9.4.20 Control Register (SD_HCTL) ................................................................................. 985
9.4.21 SD System Control Register (SD_SYSCTL) ............................................................... 988
9.4.22 Interrupt Status Register (SD_STAT) ....................................................................... 990
9.4.23 Interrupt SD Enable Register (SD_IE) ...................................................................... 995
9.4.24 Interrupt Signal Enable Register (SD_ISE) ................................................................. 998
9.4.25 Auto CMD12 Error Status Register (SD_AC12) .......................................................... 1001
9.4.26 Capabilities Register (SD_CAPA) .......................................................................... 1002
9.4.27 Maximum Current Capabilities Register (SD_CUR_CAPA) ............................................ 1004
9.4.28 Force Event Register for Error Interrupt Status (SD_FE) ............................................... 1005
9.4.29 ADMA Error Status Register (SD_ADMAES) ............................................................. 1007
9.4.30 ADMA System Address Low Bits Register (SD_ADMASAL) ........................................... 1008
9.4.31 ADMA System Address High Bits Register (SD_ADMASAH) .......................................... 1008
9.4.32 Versions Register (SD_REV) ............................................................................... 1009
10 Multichannel Audio Serial Port (McASP) ........................................................................... 1011
10.1 Introduction .............................................................................................................. 1012
10.1.1 Purpose of the Peripheral ................................................................................... 1012
10.1.2 Features ....................................................................................................... 1012
10.1.3 Protocols Supported ......................................................................................... 1012
10.1.4 Functional Block Diagram ................................................................................... 1014
10.1.5 Supported Use Case Statement ............................................................................ 1017
10.1.6 Industry Standard Compliance Statement ................................................................ 1017
10.1.7 Definition of Terms ........................................................................................... 1021
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10.2 Architecture .............................................................................................................. 1024
10.2.1 Overview ....................................................................................................... 1024
10.2.2 Clock and Frame Sync Generators ........................................................................ 1024
10.2.3 Memory Map .................................................................................................. 1028
10.2.4 Signal Descriptions ........................................................................................... 1028
10.2.5 Pin Multiplexing ............................................................................................... 1028
10.2.6 Transfer Modes ............................................................................................... 1029
10.2.7 General Architecture ......................................................................................... 1036
10.2.8 Operation ...................................................................................................... 1040
10.2.9 Reset Considerations ........................................................................................ 1058
10.2.10 Setup and Initialization ..................................................................................... 1058
10.2.11 Interrupts ..................................................................................................... 1062
10.2.12 EDMA Event Support ....................................................................................... 1064
10.2.13 Power Management ........................................................................................ 1066
10.2.14 Emulation Considerations .................................................................................. 1066
10.3 Registers ................................................................................................................. 1067
10.3.1 Revision Identification Register (REV) ..................................................................... 1070
10.3.2 Pin Function Register (PFUNC) ............................................................................ 1071
10.3.3 Pin Direction Register (PDIR) ............................................................................... 1073
10.3.4 Pin Data Output Register (PDOUT) ........................................................................ 1075
10.3.5 Pin Data Input Register (PDIN) ............................................................................. 1077
10.3.6 Pin Data Set Register (PDSET) ............................................................................ 1079
10.3.7 Pin Data Clear Register (PDCLR) .......................................................................... 1081
10.3.8 Global Control Register (GBLCTL) ......................................................................... 1083
10.3.9 Audio Mute Control Register (AMUTE) .................................................................... 1085
10.3.10 Digital Loopback Control Register (DLBCTL) ........................................................... 1087
10.3.11 Digital Mode Control Register (DITCTL) ................................................................. 1088
10.3.12 Receiver Global Control Register (RGBLCTL) .......................................................... 1089
10.3.13 Receive Format Unit Bit Mask Register (RMASK) ..................................................... 1090
10.3.14 Receive Bit Stream Format Register (RFMT) ........................................................... 1091
10.3.15 Receive Frame Sync Control Register (AFSRCTL) .................................................... 1093
10.3.16 Receive Clock Control Register (ACLKRCTL) .......................................................... 1094
10.3.17 Receive High-Frequency Clock Control Register (AHCLKRCTL) .................................... 1095
10.3.18 Receive TDM Time Slot Register (RTDM) .............................................................. 1096
10.3.19 Receiver Interrupt Control Register (RINTCTL) ......................................................... 1097
10.3.20 Receiver Status Register (RSTAT) ....................................................................... 1098
10.3.21 Current Receive TDM Time Slot Registers (RSLOT) .................................................. 1099
10.3.22 Receive Clock Check Control Register (RCLKCHK) ................................................... 1100
10.3.23 Receiver DMA Event Control Register (REVTCTL) .................................................... 1101
10.3.24 Transmitter Global Control Register (XGBLCTL) ....................................................... 1102
10.3.25 Transmit Format Unit Bit Mask Register (XMASK) ..................................................... 1103
10.3.26 Transmit Bit Stream Format Register (XFMT) .......................................................... 1104
10.3.27 Transmit Frame Sync Control Register (AFSXCTL) ................................................... 1106
10.3.28 Transmit Clock Control Register (ACLKXCTL) ......................................................... 1107
10.3.29 Transmit High-Frequency Clock Control Register (AHCLKXCTL) ................................... 1108
10.3.30 Transmit TDM Time Slot Register (XTDM) .............................................................. 1109
10.3.31 Transmitter Interrupt Control Register (XINTCTL) ...................................................... 1110
10.3.32 Transmitter Status Register (XSTAT) .................................................................... 1111
10.3.33 Current Transmit TDM Time Slot Register (XSLOT) ................................................... 1112
10.3.34 Transmit Clock Check Control Register (XCLKCHK) .................................................. 1113
10.3.35 Transmitter DMA Event Control Register (XEVTCTL) ................................................. 1114
10.3.36 Serializer Control Registers (SRCTLn).................................................................. 1115
10.3.37 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ......................................... 1116
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10.3.38 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ....................................... 1116
10.3.39 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) .................................... 1116
10.3.40 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) .................................. 1116
10.3.41 Transmit Buffer Registers (XBUFn)...................................................................... 1117
10.3.42 Receive Buffer Registers (RBUFn)....................................................................... 1117
10.3.43 Write FIFO Control Register (WFIFOCTL) .............................................................. 1118
10.3.44 Write FIFO Status Register (WFIFOSTS) ............................................................... 1119
10.3.45 Read FIFO Control Register (RFIFOCTL) ............................................................... 1120
10.3.46 Read FIFO Status Register (RFIFOSTS) ................................................................ 1121
11 Multichannel Buffered Serial Port (McBSP) ....................................................................... 1123
11.1 Introduction .............................................................................................................. 1124
11.1.1 Overview ....................................................................................................... 1124
11.1.2 Features ....................................................................................................... 1124
11.1.3 Block Diagram ................................................................................................ 1125
11.2 Architecture .............................................................................................................. 1126
11.2.1 McBSP Data Transfer Process ............................................................................. 1126
11.2.2 McBSP Sample Rate Generator ........................................................................... 1133
11.2.3 McBSP Exception/Error Conditions ........................................................................ 1138
11.2.4 McBSP DMA Configuration ................................................................................. 1143
11.2.5 Multichannel Selection Modes .............................................................................. 1144
11.2.6 McBSP Full/Half Cycle Modes .............................................................................. 1151
11.2.7 Power Management .......................................................................................... 1153
11.2.8 Programming Model .......................................................................................... 1155
11.3 Registers ................................................................................................................. 1176
11.3.1 McBSP Data Receive Register (DRR_REG) ............................................................. 1177
11.3.2 McBSP Data Transmit Register (DXR_REG) ............................................................. 1177
11.3.3 McBSP Serial Port Control Register 2 (SPCR2_REG) .................................................. 1178
11.3.4 McBSP Serial Port Control Register 1 (SPCR1_REG) .................................................. 1180
11.3.5 McBSP Receive Control Register 2 (RCR2_REG) ...................................................... 1181
11.3.6 McBSP Receive Control Register 1 (RCR1_REG ....................................................... 1182
11.3.7 McBSP Transmit Control Register 2 (XCR2_REG) ...................................................... 1183
11.3.8 McBSP Transmit Control Register 1 (XCR1_REG) ...................................................... 1184
11.3.9 McBSP Sample Rate Generator Register 2 (SRGR2_REG) ........................................... 1185
11.3.10 McBSP Sample Rate Generator Register 1 (SRGR1_REG) .......................................... 1186
11.3.11 McBSP Multichannel Register 2 (MCR2_REG) ......................................................... 1187
11.3.12 McBSP Multichannel Register 1 (MCR1_REG) ......................................................... 1189
11.3.13 McBSP Receive Channel Enable Register Partition A (RCERA_REG) ............................. 1190
11.3.14 McBSP Receive Channel Enable Register Partition B (RCERB_REG) ............................. 1190
11.3.15 McBSP Transmit Channel Enable Register Partition A (XCERA_REG) ............................. 1191
11.3.16 McBSP Transmit Channel Enable Register Partition B (XCERB_REG) ............................. 1191
11.3.17 McBSP Pin Control Register (PCR_REG) ............................................................... 1192
11.3.18 McBSP Receive Channel Enable Register Partition C (RCERC_REG) ............................. 1194
11.3.19 McBSP Receive Channel Enable Register Partition D (RCERD_REG) ............................. 1194
11.3.20 McBSP Transmit Channel Enable Register Partition C (XCERC_REG) ............................ 1195
11.3.21 McBSP Transmit Channel Enable Register Partition D (XCERD_REG) ............................ 1195
11.3.22 McBSP Receive Channel Enable Register Partition E (RCERE_REG) ............................. 1196
11.3.23 McBSP Receive Channel Enable Register Partition F (RCERF_REG) .............................. 1196
11.3.24 McBSP Transmit Channel Enable Register Partition E (XCERE_REG) ............................. 1197
11.3.25 McBSP Transmit Channel Enable Register Partition F (XCERF_REG) ............................. 1197
11.3.26 McBSP Receive Channel Enable Register Partition G (RCERG_REG) ............................. 1198
11.3.27 McBSP Receive Channel Enable Register Partition H (RCERH_REG) ............................. 1198
11.3.28 McBSP Transmit Channel Enable Register Partition G (XCERG_REG) ............................ 1199
11.3.29 McBSP Transmit Channel Enable Register Partition H (XCERH_REG) ............................ 1199
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11.3.30 McBSP Revision Number Register (REV_REG) ....................................................... 1199
11.3.31 McBSP Receive Interrupt Clear Register (RINTCLR_REG) .......................................... 1200
11.3.32 McBSP Transmit Interrupt Clear Register (XINTCLR_REG) .......................................... 1200
11.3.33 McBSP Receive Overflow Interrupt Clear Register (ROVFLCLR_REG) ............................ 1200
11.3.34 McBSP System Configuration Register (SYSCONFIG_REG) ........................................ 1201
11.3.35 McBSP Transmit Buffer Threshold Register (DMA or IRQ trigger) (THRSH2_REG) .............. 1202
11.3.36 McBSP Receive Buffer Threshold Register (DMA or IRQ trigger) (THRSH1_REG) ............... 1202
11.3.37 McBSP Interrupt Status Register (OCP compliant IRQ line) (IRQSTATATUS) .................... 1203
11.3.38 McBSP Interrupt Enable Register (OCP compliant IRQ line) (IRQENABLE) ....................... 1205
11.3.39 McBSP Wakeup Enable Register (WAKEUPEN) ....................................................... 1207
11.3.40 McBSP Transmit Configuration Control Register (XCCR_REG) ..................................... 1208
11.3.41 McBSP Receive Configuration Control Register (RCCR_REG) ...................................... 1209
11.3.42 McBSP Transmit Buffer Status Registers (XBUFFSTAT_REG) ...................................... 1210
11.3.43 McBSP Receive Buffer Status Registers (RBUFFSTAT_REG) ...................................... 1211
11.3.44 McBSP_STATUS_REG .................................................................................... 1212
12 Multichannel Serial Port Interface (McSPI) ......................................................................... 1213
12.1 Introduction .............................................................................................................. 1214
12.1.1 Overview ....................................................................................................... 1214
12.1.2 Features ....................................................................................................... 1214
12.2 Architecture .............................................................................................................. 1215
12.2.1 SPI Interface .................................................................................................. 1215
12.2.2 SPI Transmission ............................................................................................. 1215
12.2.3 Master Mode .................................................................................................. 1222
12.2.4 Slave Mode .................................................................................................... 1240
12.2.5 Interrupts ...................................................................................................... 1244
12.2.6 DMA Requests ................................................................................................ 1245
12.2.7 Emulation Mode .............................................................................................. 1246
12.2.8 Power Saving Management ................................................................................. 1247
12.2.9 System Test Mode ........................................................................................... 1248
12.2.10 Reset ......................................................................................................... 1248
12.2.11 Access to Data Registers .................................................................................. 1249
12.2.12 Programming Aid ........................................................................................... 1249
12.2.13 Interrupt and DMA Events ................................................................................. 1250
12.3 Registers ................................................................................................................. 1251
12.3.1 McSPI System Configuration Register (MCSPI_SYSCONFIG) ........................................ 1252
12.3.2 McSPI System Status Register (MCSPI_SYSSTATUS) ................................................ 1253
12.3.3 McSPI Interrupt Status Register (MCSPI_IRQSTATUS) ................................................ 1254
12.3.4 McSPI Interrupt Enable Register (MCSPI_IRQENABLE) ............................................... 1257
12.3.5 McSPI System Register (MCSPI_SYST) .................................................................. 1259
12.3.6 McSPI Module Control Register (MCSPI_MODULCTRL) .............................................. 1261
12.3.7 McSPI Channel (i) Configuration Register (MCSPI_CH(i)CONF) ...................................... 1263
12.3.8 McSPI Channel (i) Status Register (MCSPI_CH(i)STAT) ............................................... 1267
12.3.9 McSPI Channel (i) Control Register (MCSPI_CH(I)CTRL) ............................................. 1268
12.3.10 McSPI Channel (i) Transmit Register (MCSPI_TX(i)).................................................. 1269
12.3.11 McSPI Channel (i) Receive Register (MCSPI_RX(i)).................................................. 1269
12.3.12 McSPI Transfer Levels Register (MCSPI_XFERLEVEL) .............................................. 1270
13 Peripheral Component Interconnect Express (PCIe) ........................................................... 1271
13.1 Introduction .............................................................................................................. 1272
13.1.1 Overview ....................................................................................................... 1272
13.1.2 Features ....................................................................................................... 1272
13.1.3 Features Not Supported ..................................................................................... 1273
13.1.4 Functional Block Diagram ................................................................................... 1273
13.1.5 Supported Use Case Statement ............................................................................ 1275
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13.1.6 Industry Standard(s) Compliance Statement ............................................................. 1275
13.1.7 Terminology Used in this Document ....................................................................... 1275
13.2 Architecture .............................................................................................................. 1276
13.2.1 Clock Control .................................................................................................. 1276
13.2.2 Supported PCIe Transactions .............................................................................. 1276
13.2.3 Address Translations ........................................................................................ 1276
13.2.4 Address Spaces .............................................................................................. 1283
13.2.5 Bus Mastering ................................................................................................. 1284
13.2.6 PCIe Loopback ............................................................................................... 1285
13.2.7 L3 Memory Map .............................................................................................. 1286
13.2.8 Reset Considerations ........................................................................................ 1286
13.2.9 Interrupt Support .............................................................................................. 1293
13.2.10 Firewall ....................................................................................................... 1296
13.2.11 DMA Support ................................................................................................ 1296
13.2.12 Power Management ........................................................................................ 1298
13.2.13 Relationship Between Device and Link Power States ................................................. 1300
13.3 Use Case ................................................................................................................ 1303
13.3.1 PCIe Root Complex .......................................................................................... 1303
13.3.2 PCIe End Point ............................................................................................... 1304
13.4 Registers ................................................................................................................. 1305
13.4.1 Accessing Read-only Registers in Configuration Space ................................................ 1305
13.4.2 Accessing EP Application Registers from PCIe RC ..................................................... 1305
13.4.3 Encoding of LTSSM State in DEBUG Registers ......................................................... 1306
13.4.4 Application Registers ........................................................................................ 1307
13.4.5 Configuration Registers Common to Type 0 and Type 1 Headers .................................... 1343
13.4.6 Configuration Type 0 Registers ............................................................................. 1346
13.4.7 Configuration Type 1 Registers ............................................................................. 1355
13.4.8 PCIe Capability Registers ................................................................................... 1363
13.4.9 PCIe Extended Capability Registers ....................................................................... 1373
13.4.10 Message Signaled Interrupts Registers .................................................................. 1382
13.4.11 Power Management Capability Registers ............................................................... 1384
13.4.12 Port Logic Registers ........................................................................................ 1386
14 Power, Reset, and Clock Management (PRCM) Module ....................................................... 1395
14.1 Introduction .............................................................................................................. 1396
14.1.1 Device Power-Management Architecture Building Blocks .............................................. 1396
14.1.2 Module-Level Clock Management .......................................................................... 1397
14.1.3 Clock Domain ................................................................................................. 1400
14.1.4 Power Management .......................................................................................... 1402
14.2 Power Reset Clock Management Overview ........................................................................ 1404
14.2.1 Introduction .................................................................................................... 1404
14.2.2 Interfaces Description ........................................................................................ 1404
14.2.3 Power Control Interface ..................................................................................... 1404
14.2.4 FAPLL interface .............................................................................................. 1405
14.2.5 Device Control Interface ..................................................................................... 1405
14.2.6 Clocks Interface .............................................................................................. 1405
14.2.7 Resets Interface .............................................................................................. 1405
14.2.8 Modules Power Management Control Interface .......................................................... 1406
14.3 Device Modules and Power-Management Attributes List ......................................................... 1406
14.3.1 Active Power Domain Modules Attribute .................................................................. 1406
14.3.2 AlwaysOn Power Domain Modules Attribute ............................................................. 1406
14.3.3 Default Power Domain Modules Attribute ................................................................. 1408
14.3.4 SGX Power Domain Modules Attribute .................................................................... 1408
14.4 Clock Management ..................................................................................................... 1409
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14.4.1 Terminology ................................................................................................... 1409
14.4.2 External Clock Sources to PRCM .......................................................................... 1409
14.4.3 Internal Clock Sources ....................................................................................... 1410
14.4.4 Clock Generation ............................................................................................. 1411
14.5 Reset Management .................................................................................................... 1416
14.5.1 Overview ....................................................................................................... 1416
14.5.2 Reset Concepts and Definitions ............................................................................ 1416
14.5.3 Global Power-On (Cold) Reset ............................................................................. 1418
14.5.4 Global Warm Reset .......................................................................................... 1418
14.5.5 MPU Subsystem POR Sequence .......................................................................... 1419
14.5.6 MPU Subsystem Warm Sequence ......................................................................... 1420
14.5.7 C674x DSP Power-On Reset Sequence .................................................................. 1420
14.5.8 C674x DSP Warm Reset Sequence ....................................................................... 1420
14.6 Power Management .................................................................................................... 1421
14.6.1 Overview ....................................................................................................... 1421
14.6.2 Power Domains Management .............................................................................. 1421
14.6.3 Power Domain Transition Control .......................................................................... 1423
14.7 Registers ................................................................................................................. 1424
14.7.1 PRM_DEVICE ................................................................................................ 1427
14.7.2 CM_Device .................................................................................................... 1429
14.7.3 OCP_SOCKET_PRM Device ............................................................................... 1430
14.7.4 CM_DPLL Device ............................................................................................ 1431
14.7.5 CM_ACTIVE Device ......................................................................................... 1448
14.7.6 CM_DEFAULT Device ....................................................................................... 1453
14.7.7 CM_SGX Device ............................................................................................. 1466
14.7.8 PRM_ACTIVE Device ........................................................................................ 1468
14.7.9 PRM_DEFAULT Device ..................................................................................... 1471
14.7.10 PRM_SGX Device .......................................................................................... 1475
14.7.11 CM_ALWON Device ........................................................................................ 1477
15 Real-Time Clock (RTC) .................................................................................................... 1535
15.1 Introduction .............................................................................................................. 1536
15.1.1 Overview ....................................................................................................... 1536
15.1.2 Features ....................................................................................................... 1536
15.1.3 Functional Block Diagram ................................................................................... 1536
15.2 Architecture .............................................................................................................. 1537
15.2.1 Clock Source .................................................................................................. 1537
15.2.2 Signal Descriptions ........................................................................................... 1537
15.2.3 Interrupt Support .............................................................................................. 1538
15.2.4 Programming/Usage Guide ................................................................................. 1539
15.2.5 Scratch Registers ............................................................................................. 1543
15.2.6 Power Management .......................................................................................... 1543
15.2.7 Reset Considerations ........................................................................................ 1543
15.3 Registers ................................................................................................................. 1544
15.3.1 Seconds Register (SECONDS_REG) ..................................................................... 1545
15.3.2 Minutes Register (MINUTES_REG) ....................................................................... 1545
15.3.3 Hours Register (HOURS_REG) ............................................................................ 1546
15.3.4 Days of the Month Register (DAYS_REG) ................................................................ 1546
15.3.5 Month Register (MONTHS_REG) .......................................................................... 1547
15.3.6 Year Register (YEARS_REG) .............................................................................. 1547
15.3.7 Day of the Week Register (WEEKS_REG) ............................................................... 1548
15.3.8 Alarm Second Register (ALARM_SECONDS_REG) .................................................... 1548
15.3.9 Alarm Minute Register (ALARM_MINUTES_REG) ...................................................... 1549
15.3.10 Alarm Hour Register (ALARM_HOURS_REG) ......................................................... 1549
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15.3.11 Alarm Day of the Month Register (ALARM_DAYS_REG) ............................................. 1550
15.3.12 Alarm Month Register (ALARM_MONTHS_REG) ...................................................... 1550
15.3.13 Alarm Year Register (ALARM_YEARS_REG) .......................................................... 1551
15.3.14 Control Register (CTRL_REG) ............................................................................ 1552
15.3.15 Status Register (STATUS_REG) ......................................................................... 1554
15.3.16 Interrupt Register (INTERRUPTS_REG) ................................................................ 1555
15.3.17 Compensation (LSB) Register (COMP_LSB_REG) .................................................... 1556
15.3.18 Compensation (MSB) Register (COMP_MSB_REG) .................................................. 1557
15.3.19 Oscillator Register (OSC_REG) .......................................................................... 1558
15.3.20 Scratch Registers (SCRATCHx_REG) ................................................................... 1558
15.3.21 Kick Registers (KICK0R, KICK1R) ....................................................................... 1559
15.3.22 RTC Revision Register (RTC_REVISION) .............................................................. 1560
15.3.23 System Configuration Register (RTC_SYSCONFIG) .................................................. 1560
15.3.24 Wakeup Enable Register (RTC_IRQWAKEEN) ........................................................ 1561
16 Serial ATA (SATA) Controller ........................................................................................... 1563
16.1 Introduction .............................................................................................................. 1564
16.1.1 Purpose of the Peripheral ................................................................................... 1564
16.1.2 Features Supported .......................................................................................... 1565
16.1.3 Features Not Supported ..................................................................................... 1565
16.1.4 Functional Block Diagram ................................................................................... 1566
16.1.5 Industry Standard(s) Compliance .......................................................................... 1566
16.1.6 Non-Industry Standard(s) Compliance .................................................................... 1566
16.1.7 Terminology Used in this Document ....................................................................... 1567
16.2 Architecture .............................................................................................................. 1568
16.2.1 Clock Control .................................................................................................. 1568
16.2.2 Signal Description ............................................................................................ 1569
16.2.3 DMA ............................................................................................................ 1569
16.2.4 Transport Layer ............................................................................................... 1570
16.2.5 FIFOs .......................................................................................................... 1570
16.2.6 Link Layer ..................................................................................................... 1570
16.2.7 PHY ............................................................................................................ 1570
16.2.8 Pin Multiplexing ............................................................................................... 1570
16.2.9 Power Management .......................................................................................... 1570
16.2.10 Reset ......................................................................................................... 1571
16.2.11 Interfacing to Single and Multiple Devices ............................................................... 1571
16.2.12 Initialization .................................................................................................. 1571
16.2.13 Interrupt Support ............................................................................................ 1573
16.2.14 EDMA Event Support ....................................................................................... 1574
16.3 Use Cases ............................................................................................................... 1574
16.3.1 General Utilities: Structures and Subroutines Sample Program Uses ................................ 1575
16.3.2 Example on Initialization and Spinning Up Device ....................................................... 1587
16.3.3 Example of DMA Write Transfer ............................................................................ 1589
16.3.4 Example of DMA Read Transfer ........................................................................... 1591
16.4 Registers ................................................................................................................. 1592
16.4.1 HBA Capabilities Register (CAP) ........................................................................... 1594
16.4.2 Global HBA Control Register (GHC) ....................................................................... 1595
16.4.3 Interrupt Status Register (IS) ............................................................................... 1596
16.4.4 Ports Implemented Register (PI) ........................................................................... 1597
16.4.5 AHCI Version Register (VS) ................................................................................ 1597
16.4.6 Command Completion Coalescing Control Register (CCC_CTL) ..................................... 1598
16.4.7 Command Completion Coalescing Ports Register (CCC_PORTS) .................................... 1599
16.4.8 BIST Active FIS Register (BISTAFR) ...................................................................... 1600
16.4.9 BIST Control Register (BISTCR) ........................................................................... 1601
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16.4.10 BIST FIS Count Register (BISTFCTR) ................................................................... 1603
16.4.11 BIST Status Register (BISTSR) ........................................................................... 1603
16.4.12 BIST DWORD Error Count Register (BISTDECR) ..................................................... 1604
16.4.13 BIST DWORD Error Count Register (TIMER1MS) ..................................................... 1604
16.4.14 Global Parameter 1 Register (GPARAM1R) ............................................................ 1605
16.4.15 Global Parameter 2 Register (GPARAM2R) ............................................................ 1606
16.4.16 Port Parameter Register (PPARAMR) ................................................................... 1607
16.4.17 Test Register (TESTR) ..................................................................................... 1608
16.4.18 Version Register (VERSIONR) ............................................................................ 1609
16.4.19 ID Register (IDR) ............................................................................................ 1609
16.4.20 Port Command List Base Address Register (P#CLB) (# = 0 or 1) ................................... 1610
16.4.21 Port FIS Base Address Register (P#FB) (# = 0 or 1) .................................................. 1610
16.4.22 Port Interrupt Status Register (P#IS) (# = 0 or 1) ...................................................... 1611
16.4.23 Port Interrupt Enable Register (P#IE) (# = 0 or 1) ...................................................... 1613
16.4.24 Port Command Register (P#CMD) (# = 0 or 1) ......................................................... 1614
16.4.25 Port Task File Data Register (P#TFD) (# = 0 or 1) ..................................................... 1617
16.4.26 Port Signature Register (P#SIG) (# = 0 or 1) ........................................................... 1617
16.4.27 Port Serial ATA Status Register (P#SSTS) (# = 0 or 1) ............................................... 1618
16.4.28 Port Serial ATA Control Register (P#SCTL) (# = 0 or 1) .............................................. 1619
16.4.29 Port Serial ATA Error Register (P#SERR) (# = 0 or 1) ................................................ 1620
16.4.30 Port Serial ATA Active Register (P#SACT) (# = 0 or 1) ............................................... 1622
16.4.31 Port Command Issue Register (P#CI) (# = 0 or 1) ..................................................... 1622
16.4.32 Port Serial ATA Notification Register (P#SNTF) (# = 0 or 1) ......................................... 1623
16.4.33 Port DMA Control Register (P#DMACR) (# = 0 or 1) .................................................. 1624
16.4.34 Port PHY Control Register (P#PHYCR) (# = 0 or 1) ................................................... 1626
16.4.35 Port PHY Status Register (P#PHYSR) (# = 0 or 1) .................................................... 1630
16.4.36 Idle Register (IDLE) ......................................................................................... 1631
16.4.37 PHY Configuration Register 2 (PHYCFGR2) ............................................................ 1632
17 Timers .......................................................................................................................... 1633
17.1 Introduction .............................................................................................................. 1634
17.1.1 Overview ....................................................................................................... 1634
17.1.2 Features ....................................................................................................... 1634
17.1.3 Functional Block Diagram ................................................................................... 1635
17.2 Architecture .............................................................................................................. 1635
17.2.1 Functional Description ....................................................................................... 1635
17.2.2 Accessing Registers ......................................................................................... 1641
17.2.3 Posted Mode Selection ...................................................................................... 1641
17.2.4 Write Registers Access ...................................................................................... 1642
17.2.5 Read Registers Access ...................................................................................... 1643
17.3 Registers ................................................................................................................. 1644
17.3.1 Identification Register (TIDR) ............................................................................... 1645
17.3.2 Timer OCP Configuration Register (TIOCP_CFG) ....................................................... 1646
17.3.3 Timer IRQ EOI Register (IRQ_EOI) ........................................................................ 1647
17.3.4 Timer IRQSTATUS Raw Register (IRQSTATUS_RAW) ................................................ 1648
17.3.5 Timer IRQSTATUS Register (IRQSTATUS) .............................................................. 1649
17.3.6 Timer IRQENABLE Set Register (IRQENABLE_SET) .................................................. 1650
17.3.7 Timer IRQENABLE Clear Register (IRQENABLE_CLR) ................................................ 1651
17.3.8 Timer IRQ Wakeup Enable Register (IRQWAKEEN) .................................................... 1652
17.3.9 Timer Control Register (TCLR) ............................................................................. 1652
17.3.10 Timer Counter Register (TCRR) .......................................................................... 1654
17.3.11 Timer Load Register (TLDR) .............................................................................. 1654
17.3.12 Timer Trigger Register (TTGR) ........................................................................... 1655
17.3.13 Timer Write Posted Status Register (TWPS) ........................................................... 1655
17
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17.3.14 Timer Match Register (TMAR) ............................................................................ 1656
17.3.15 Timer Capture Register (TCAR1) ......................................................................... 1656
17.3.16 Timer Synchronous Interface Control Register (TSICR) ............................................... 1657
17.3.17 Timer Capture Register (TCAR2) ......................................................................... 1657
18 Watchdog Timer ............................................................................................................. 1659
18.1 Introduction .............................................................................................................. 1660
18.1.1 Overview ....................................................................................................... 1660
18.1.2 Functional Block Diagram ................................................................................... 1660
18.1.3 Features ....................................................................................................... 1660
18.1.4 Watchdog Timer Environment .............................................................................. 1660
18.2 Architecture .............................................................................................................. 1661
18.2.1 Power Management .......................................................................................... 1661
18.2.2 Interrupts ...................................................................................................... 1661
18.2.3 General Watchdog Timer Operation ....................................................................... 1661
18.2.4 Reset Context ................................................................................................. 1662
18.2.5 Overflow/Reset Generation ................................................................................. 1662
18.2.6 Prescaler Value/Timer Reset Frequency .................................................................. 1662
18.2.7 Triggering a Timer Reload .................................................................................. 1664
18.2.8 Start/Stop Sequence for Watchdog Timers (Using the WDT_WSPR Register) ...................... 1664
18.2.9 Modifying Timer Count/Load Values and Prescaler Setting ............................................ 1664
18.2.10 Watchdog Counter Register Access Restriction (WDT_WCRR Register) .......................... 1664
18.2.11 Watchdog Timer Interrupt Generation .................................................................... 1665
18.2.12 Watchdog Timers Under Emulation ...................................................................... 1666
18.2.13 Accessing Watchdog Timer Registers ................................................................... 1666
18.3 Low-Level Programming Model ....................................................................................... 1667
18.3.1 Global Initialization ........................................................................................... 1667
18.3.2 Operational Mode Configuration ............................................................................ 1667
18.4 Registers ................................................................................................................. 1668
18.4.1 WDT_WIDR Register ........................................................................................ 1669
18.4.2 WDT_WDSC Register ....................................................................................... 1669
18.4.3 WDT_WDST Register ....................................................................................... 1670
18.4.4 WDT_WISR Register ........................................................................................ 1670
18.4.5 WDT_WIER Register ........................................................................................ 1671
18.4.6 WDT_WCLR Register ....................................................................................... 1671
18.4.7 WDT_WCRR Register ....................................................................................... 1672
18.4.8 WDT_WLDR Register ....................................................................................... 1672
18.4.9 WDT_WTGR Register ....................................................................................... 1672
18.4.10 WDT_WWPS Register ..................................................................................... 1673
18.4.11 WDT_WDLY Register ...................................................................................... 1674
18.4.12 WDT_WSPR Register ...................................................................................... 1674
18.4.13 WDT_WIRQSTATRAW Register ......................................................................... 1675
18.4.14 WDT_WIRQSTAT Register ................................................................................ 1676
18.4.15 WDT_WIRQENSET Register .............................................................................. 1677
18.4.16 WDT_WIRQENCLR Register ............................................................................. 1678
19 UART/IrDA/CIR Module ................................................................................................... 1679
19.1 Introduction .............................................................................................................. 1680
19.1.1 Overview ....................................................................................................... 1680
19.1.2 Main Features ................................................................................................. 1680
19.1.3 UART/Modem Functions .................................................................................... 1681
19.1.4 IrDA Functions ................................................................................................ 1681
19.1.5 CIR Features .................................................................................................. 1681
19.2 Architecture .............................................................................................................. 1682
19.2.1 UART Signal Descriptions ................................................................................... 1682
18 Contents SPRUGX9–15 April 2011
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19.2.2 UART/IrDA/CIR Mode Selection ............................................................................ 1682
19.2.3 UART Mode ................................................................................................... 1683
19.2.4 IrDA Mode ..................................................................................................... 1687
19.2.5 CIR Mode ...................................................................................................... 1695
19.2.6 FIFO Management ........................................................................................... 1700
19.2.7 Interrupts ...................................................................................................... 1707
19.2.8 Sleep Modes .................................................................................................. 1709
19.2.9 Idle Modes ..................................................................................................... 1709
19.2.10 Programmable Baud Rate Generator .................................................................... 1710
19.3 Registers ................................................................................................................. 1713
19.3.1 Receiver Holding Register (RHR) .......................................................................... 1714
19.3.2 Transmit Holding Register (THR) .......................................................................... 1714
19.3.3 Interrupt Enable Register (IER) - UART Mode ........................................................... 1715
19.3.4 Interrupt Enable Register (IER) - IrDA Mode ............................................................. 1716
19.3.5 Interrupt Enable Register (IER) - CIR Mode .............................................................. 1717
19.3.6 Interrupt Identification Register (IIR) - UART Mode ...................................................... 1718
19.3.7 Interrupt Identification Register (IIR) - IrDA Mode ........................................................ 1719
19.3.8 Interrupt Identification Register (IIR) - CIR Mode ........................................................ 1720
19.3.9 FIFO Control Register (FCR) ............................................................................... 1721
19.3.10 Line Control Register (LCR) ............................................................................... 1722
19.3.11 Modem Control Register (MCR) .......................................................................... 1723
19.3.12 Line Status Register (LSR) - UART Mode ............................................................... 1724
19.3.13 Line Status Register (LSR) - IrDA Mode ................................................................. 1725
19.3.14 Line Status Register (LSR) - CIR Mode ................................................................. 1726
19.3.15 Modem Status Register (MSR) ........................................................................... 1727
19.3.16 Transmission Control Register (TCR) .................................................................... 1728
19.3.17 Scratchpad Register (SPR) ................................................................................ 1728
19.3.18 Trigger Level Register (TLR) .............................................................................. 1729
19.3.19 Mode Definition Register 1 (MDR1) ...................................................................... 1730
19.3.20 Mode Definition Register 2 (MDR2) ...................................................................... 1731
19.3.21 Status FIFO Line Status Register (SFLSR) ............................................................. 1732
19.3.22 RESUME Register .......................................................................................... 1732
19.3.23 Status FIFO Register Low (SFREGL) .................................................................... 1733
19.3.24 Status FIFO Register High (SFREGH) ................................................................... 1733
19.3.25 BOF Control Register (BLR) ............................................................................... 1734
19.3.26 Auxiliary Control Register (ACREG) ...................................................................... 1735
19.3.27 Supplementary Control Register (SCR) .................................................................. 1736
19.3.28 Supplementary Status Register (SSR) ................................................................... 1737
19.3.29 BOF Length Register (EBLR) ............................................................................. 1738
19.3.30 Module Version Register (MVR) .......................................................................... 1739
19.3.31 System Configuration Register (SYSC) .................................................................. 1740
19.3.32 System Status Register (SYSS) .......................................................................... 1740
19.3.33 Wake-Up Enable Register (WER) ....................................................................... 1741
19.3.34 Carrier Frequency Prescaler Register (CFPS) .......................................................... 1742
19.3.35 Divisor Latches Low Register (DLL) ...................................................................... 1743
19.3.36 Divisor Latches High Register (DLH) ..................................................................... 1743
19.3.37 Enhanced Feature Register (EFR) ....................................................................... 1744
19.3.38 XON1/ADDR1 Register .................................................................................... 1745
19.3.39 XON2/ADDR2 Register .................................................................................... 1745
19.3.40 XOFF1 Register ............................................................................................. 1746
19.3.41 XOFF2 Register ............................................................................................. 1746
19.3.42 Transmit Frame Length Low Register (TXFLL) ......................................................... 1747
19.3.43 Transmit Frame Length High Register (TXFLH) ........................................................ 1747
19
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19.3.44 Received Frame Length Low Register (RXFLL) ........................................................ 1748
19.3.45 Received Frame Length High Register (RXFLH) ....................................................... 1748
19.3.46 UART Autobauding Status Register (UASR) ............................................................ 1749
20 Universal Serial Bus (USB) .............................................................................................. 1751
20.1 Introduction .............................................................................................................. 1752
20.1.1 Overview ....................................................................................................... 1752
20.1.2 Acronyms, Abbreviations, and Definitions ................................................................. 1752
20.1.3 Features Supported .......................................................................................... 1753
20.1.4 Features Not Supported ..................................................................................... 1754
20.1.5 Functional Block Diagram ................................................................................... 1754
20.1.6 Supported Use Case(s) ...................................................................................... 1755
20.1.7 Industry Standard(s) Compliance .......................................................................... 1755
20.1.8 Non-Industry Standard(s) .................................................................................... 1755
20.2 Architecture .............................................................................................................. 1756
20.2.1 Clock Control .................................................................................................. 1756
20.2.2 Signal Descriptions ........................................................................................... 1756
20.2.3 VBUS Voltage Sourcing Control ............................................................................ 1757
20.2.4 Pull-up/Pull-Down Resistors ................................................................................ 1757
20.2.5 Role Assuming Method ...................................................................................... 1757
20.2.6 USB Signal Conditioning .................................................................................... 1757
20.2.7 USB PHY Initialization ....................................................................................... 1757
20.2.8 Indexed and Non-Indexed Register Spaces .............................................................. 1758
20.2.9 Dynamic FIFO Sizing ........................................................................................ 1758
20.2.10 USB Controller Host and Peripheral Modes Operation ................................................ 1759
20.3 Protocol Description(s) ................................................................................................. 1760
20.3.1 USB Controller Peripheral Mode Operation ............................................................... 1760
20.3.2 USB Controller Host Mode Operation ..................................................................... 1777
20.4 Communications Port Programming Interface (CPPI) 4.1 DMA .................................................. 1795
20.4.1 CPPI Terminology ............................................................................................ 1795
20.4.2 Data Structures ............................................................................................... 1796
20.4.3 Queue Manager .............................................................................................. 1803
20.4.4 Memory Regions and Linking RAM ........................................................................ 1806
20.4.5 Zero Length Packets ......................................................................................... 1808
20.4.6 CPPI DMA Scheduler ........................................................................................ 1808
20.4.7 CPPI DMA State Registers ................................................................................. 1809
20.4.8 CPPI DMA Protocols Supported ........................................................................... 1810
20.4.9 USB Data Flow Using DMA ................................................................................. 1812
20.5 USB 2.0 Test Modes ................................................................................................... 1819
20.5.1 TEST_SE0_NAK ............................................................................................. 1819
20.5.2 TEST_J ........................................................................................................ 1819
20.5.3 TEST_K ........................................................................................................ 1819
20.5.4 TEST_PACKET ............................................................................................... 1819
20.5.5 FIFO_ACCESS ............................................................................................... 1820
20.5.6 FORCE_HOST ............................................................................................... 1820
20.6 Reset Considerations .................................................................................................. 1820
20.6.1 Software Reset Considerations ............................................................................. 1820
20.6.2 Hardware Reset Considerations ............................................................................ 1820
20.7 Interrupt Support ........................................................................................................ 1821
20.7.1 CPU Interrupts ................................................................................................ 1821
20.7.2 Interrupt Description .......................................................................................... 1825
20.7.3 Interrupt Condition Control .................................................................................. 1826
20.8 Supported Use Cases ................................................................................................. 1826
20.9 Registers ................................................................................................................. 1827
20 Contents SPRUGX9–15 April 2011
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