Texas Instruments TMS320C6A816 Series Product manual

Preliminary
TMS320C6A816x C6-Integra
DSP+ARM Processors
Technical Reference Manual
Literature Number: SPRUGX9
15 April 2011

Preliminary
2SPRUGX9–15 April 2011
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Contents
Preface ...................................................................................................................................... 91
1 Chip Level Resources ........................................................................................................ 93
1.1 Introduction ................................................................................................................. 94
1.2 MPU Subsystem ........................................................................................................... 94
1.2.1 Introduction ........................................................................................................ 94
1.2.2 Features ........................................................................................................... 95
1.2.3 MPU Subsystem Integration .................................................................................... 96
1.2.4 MPU Subsystem Clock and Reset Distribution ............................................................... 98
1.2.5 ARM Subchip .................................................................................................... 101
1.2.6 AXI2OCP and I2Async Bridges ............................................................................... 102
1.2.7 Interrupt Controller .............................................................................................. 104
1.2.8 Power Management ............................................................................................ 104
1.2.9 Host ARM Address Map ....................................................................................... 107
1.2.10 ARM Programming Model .................................................................................... 107
1.3 C674x DSP Subsystem ................................................................................................. 109
1.3.1 Introduction ...................................................................................................... 109
1.3.2 Key Features .................................................................................................... 110
1.3.3 DSP Subsystem Functional Description ..................................................................... 111
1.3.4 TMS320C674x Megamodule .................................................................................. 112
1.3.5 Advanced Event Triggering (AET) ............................................................................ 116
1.4 System MMU ............................................................................................................. 117
1.4.1 MMU Overview .................................................................................................. 117
1.4.2 MMU Intergration ................................................................................................ 117
1.4.3 MMU Functional Description .................................................................................. 118
1.4.4 MMU Low-level Programming Models ....................................................................... 130
1.4.5 MMU Registers .................................................................................................. 133
1.5 SGX530 Graphics Subsystem .......................................................................................... 145
1.5.1 SGX Overview ................................................................................................... 145
1.5.2 SGX Integration ................................................................................................. 148
1.5.3 SGX Functional Description ................................................................................... 150
1.5.4 SGX Registers ................................................................................................... 152
1.6 HD Video Processing Subsystem (HDVPSS) ........................................................................ 167
1.6.1 Features Supported ............................................................................................. 167
1.7 System Memory Map .................................................................................................... 170
1.8 Device Interrupts ......................................................................................................... 171
1.8.1 Interrupt Requests to Cortex-A8 MPU INTC ................................................................ 171
1.8.2 Interrupt Requests to Media Controller INTC ............................................................... 174
1.8.3 Interrupt Requests to DSP INTC .............................................................................. 176
1.9 EDMA and EDMA Events ............................................................................................... 179
1.9.1 Overview ......................................................................................................... 179
1.9.2 EDMA Regions .................................................................................................. 179
1.9.3 Synchronization Events ........................................................................................ 179
1.10 Device Clocking and Flying Adder PLL ............................................................................... 182
1.10.1 Overview ........................................................................................................ 182
1.10.2 I/O Domains .................................................................................................... 186
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1.10.3 Flying Adder PLL ............................................................................................... 187
1.10.4 Clock Out ....................................................................................................... 198
1.11 Bus Interconnect ......................................................................................................... 199
1.11.1 Terminology ..................................................................................................... 199
1.11.2 L3 Interconnect ................................................................................................. 199
1.12 Inter-Processor Communication ....................................................................................... 205
1.12.1 Reset Requirements ........................................................................................... 205
1.12.2 Features ......................................................................................................... 205
1.12.3 Overview and Strategy ........................................................................................ 206
1.12.4 IPC Component Configuration ............................................................................... 208
1.13 Mailbox .................................................................................................................... 209
1.13.1 Overview ........................................................................................................ 209
1.13.2 System Mailbox Integration ................................................................................... 209
1.13.3 Functional Description ......................................................................................... 210
1.13.4 Programming Guide ........................................................................................... 214
1.13.5 Mailbox Registers .............................................................................................. 217
1.14 Spinlock ................................................................................................................... 237
1.14.1 Overview ........................................................................................................ 237
1.14.2 Integration ....................................................................................................... 238
1.14.3 Functional Description ......................................................................................... 239
1.14.4 Programming Guide ........................................................................................... 241
1.14.5 Spinlock Registers ............................................................................................. 243
1.15 Error Location Module ................................................................................................... 247
1.15.1 Error Location Module Overview ............................................................................. 247
1.15.2 ELM Integration ................................................................................................ 248
1.15.3 ELM Functional Description .................................................................................. 249
1.15.4 ELM Basic Programming Model ............................................................................. 252
1.15.5 ELM Registers .................................................................................................. 258
1.16 Control Module ........................................................................................................... 270
1.16.1 Registers ........................................................................................................ 270
1.17 Interrupt Controller ....................................................................................................... 329
1.18 Resets ..................................................................................................................... 330
2 DMM/TILER ..................................................................................................................... 331
2.1 Introduction ............................................................................................................... 332
2.1.1 Overview ......................................................................................................... 332
2.1.2 Features .......................................................................................................... 333
2.1.3 Functional Block Diagram ...................................................................................... 333
2.1.4 Terminologies and Acronyms Used in this Document ..................................................... 334
2.2 Architecture ............................................................................................................... 335
2.2.1 DMM Functional Description .................................................................................. 335
2.2.2 TILER Functional Description ................................................................................. 346
2.3 Use Case .................................................................................................................. 370
2.3.1 DMM Basic Register Setup .................................................................................... 370
2.3.2 Simple LUT Bypass Use Case: Arrangement of Video Buffers ........................................... 371
2.3.3 LUT Refill Using the PAT Refill Engines ..................................................................... 373
2.3.4 Address Management Using LISA Sections ................................................................ 380
2.4 Registers .................................................................................................................. 385
2.4.1 DMM Revision Register: DMM_REVISION .................................................................. 385
2.4.2 DMM Clock Management Configuration: DMM_SYSCONFIG ............................................ 386
2.4.3 LISA Configuration Locking Register: DMM_LISA_LOCK ................................................. 386
2.4.4 DMM LISA MAP Registers: DMM_LISA_MAP_0-DMM_LISA_MAP_3 .................................. 387
2.4.5 DMM TILER Orientation Registers: DMM_TILER_OR0-DMM_TILER_OR1 ............................ 388
2.4.6 DMM PAT Configuration Register: DMM_PAT_CONFIG .................................................. 388
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2.4.7 DMM PAT View Registers: DMM_PAT_VIEW_0-DMM_PAT_VIEW_2 ................................. 389
2.4.8 DMM View Map Registers: DMM_PAT_VIEW_MAP_0-DMM_PAT_VIEW_MAP_4 ................... 390
2.4.9 DMM PAT View Mapping Base Address Register: DMM_PAT_VIEW_MAP_BASE .................. 391
2.4.10 DMM PAT End of Interrupt Register: DMM_PAT_IRQ_EOI ............................................. 391
2.4.11 DMM PAT Raw Interrupt Status Register: DMM_PAT_IRQSTATUS_RAW ........................... 393
2.4.12 DMM PAT Interrupt Status Register: DMM_PAT_IRQSTATUS ......................................... 395
2.4.13 DMM PAT Interrupt Enable Register: DMM_PAT_IRQENABLE_SET .................................. 397
2.4.14 DMM PAT Interrupt Disable Register: DMM_PAT_IRQENABLE_CLR ................................. 399
2.4.15 DMM PAT Status Registers: DMM_PAT_STATUS_0-DMM_PAT_STATUS_3 ....................... 401
2.4.16 DMM PAT Descriptor Registers: DMM_PAT_DESCR_0-DMM_PAT_DESCR_3 ..................... 402
2.4.17 DMM PAT Area Geometry Registers: DMM_PAT_AREA_0-DMM_PAT_AREA_3 ................... 402
2.4.18 DMM PAT Control Registers: DMM_PAT_CTRL_0-DMM_PAT_CTRL_3 ............................. 403
2.4.19 DMM PAT Area Entry Data Registers: DMM_PAT_DATA_0-DMM_PAT_DATA_3 .................. 403
2.4.20 DMM PEG Priority Registers: DMM_PEG_PRIO_0-DMM_PEG_PRIO_1 ............................. 404
2.4.21 DMM PEG Priority Registers for PAT: DMM_PEG_PRIO_PAT ......................................... 404
3 EMAC/MDIO Module ......................................................................................................... 405
3.1 Introduction ............................................................................................................... 406
3.1.1 Overview ......................................................................................................... 406
3.1.2 Features .......................................................................................................... 406
3.1.3 Functional Block Diagram ...................................................................................... 407
3.1.4 EMAC and MDIO Block Diagram ............................................................................. 407
3.1.5 Industry Standard(s) Compliance Statement ................................................................ 408
3.1.6 List of Terms ..................................................................................................... 408
3.2 Architecture ............................................................................................................... 410
3.2.1 Clock Control .................................................................................................... 410
3.2.2 Memory Map ..................................................................................................... 410
3.2.3 Signal Descriptions ............................................................................................. 411
3.2.4 Ethernet Protocol Overview .................................................................................... 413
3.2.5 Programming Interface ......................................................................................... 414
3.2.6 EMAC Control Module .......................................................................................... 425
3.2.7 MDIO Module .................................................................................................... 428
3.2.8 EMAC Module ................................................................................................... 432
3.2.9 Media Independent Interface (MII) ............................................................................ 435
3.2.10 Packet Receive Operation .................................................................................... 439
3.2.11 Packet Transmit Operation ................................................................................... 444
3.2.12 Receive and Transmit Latency ............................................................................... 444
3.2.13 Transfer Node Priority ......................................................................................... 445
3.2.14 Reset Considerations .......................................................................................... 445
3.2.15 Initialization ..................................................................................................... 446
3.2.16 Interrupt Support ............................................................................................... 450
3.2.17 Power Management ........................................................................................... 454
3.2.18 Emulation Considerations ..................................................................................... 454
3.3 Registers .................................................................................................................. 455
3.3.1 EMAC Control Module Registers ............................................................................. 455
3.3.2 Ethernet Media Access Controller (EMAC) Registers ...................................................... 465
3.3.3 MDIO Registers ................................................................................................. 514
4 General-Purpose I/O (GPIO) Interface ................................................................................. 527
4.1 Introduction ............................................................................................................... 528
4.1.1 Purpose of the Peripheral ...................................................................................... 528
4.1.2 Features .......................................................................................................... 528
4.1.3 Block Diagram ................................................................................................... 529
4.2 Architecture ............................................................................................................... 530
4.2.1 Operating Modes ................................................................................................ 530
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4.2.2 Clocking and Reset Strategy .................................................................................. 530
4.2.3 Interrupt Features ............................................................................................... 531
4.2.4 General-Purpose Interface Basic Programming Model .................................................... 533
4.3 Registers .................................................................................................................. 537
4.3.1 GPIO_REVISION Register .................................................................................... 538
4.3.2 GPIO_SYSCONFIG Register ................................................................................. 539
4.3.3 GPIO_EOI Register ............................................................................................. 540
4.3.4 GPIO_IRQSTATUS_RAW_n Register ....................................................................... 541
4.3.5 GPIO_IRQSTATUS_n Register ............................................................................... 541
4.3.6 GPIO_IRQSTATUS_SET_n Register ........................................................................ 542
4.3.7 GPIO_IRQSTATUS_CLR_n Register ........................................................................ 542
4.3.8 GPIO_SYSSTATUS Register ................................................................................. 543
4.3.9 GPIO_CTRL Register .......................................................................................... 544
4.3.10 GPIO_OE Register ............................................................................................ 544
4.3.11 GPIO_DATAIN Register ...................................................................................... 545
4.3.12 GPIO_DATAOUT Register ................................................................................... 545
4.3.13 GPIO_LEVELDETECT0 Register ............................................................................ 546
4.3.14 GPIO_LEVELDETECT1 Register ............................................................................ 546
4.3.15 GPIO_RISINGDETECT Register ............................................................................ 547
4.3.16 GPIO_FALLINGDETECT Register .......................................................................... 547
4.3.17 GPIO_DEBOUNCENABLE Register ........................................................................ 548
4.3.18 GPIO_DEBOUNCINGTIME Register ........................................................................ 548
4.3.19 GPIO_CLEARDATAOUT Register .......................................................................... 549
4.3.20 GPIO_SETDATAOUT Register .............................................................................. 549
5 General-Purpose Memory Controller (GPMC) ...................................................................... 551
5.1 Introduction ............................................................................................................... 552
5.1.1 Overview ......................................................................................................... 552
5.1.2 Block Diagram ................................................................................................... 552
5.2 Architecture ............................................................................................................... 554
5.2.1 GPMC Signals ................................................................................................... 554
5.2.2 GPMC Modes ................................................................................................... 556
5.2.3 GPMC Integration ............................................................................................... 558
5.2.4 GPMC Functional Description ................................................................................. 559
5.3 Basic Programming Model .............................................................................................. 633
5.3.1 GPMC High-Level Programming Model Overview ......................................................... 633
5.3.2 GPMC Initialization ............................................................................................. 635
5.3.3 GPMC Configuration in NOR Mode .......................................................................... 636
5.3.4 GPMC Configuration in NAND Mode ......................................................................... 637
5.3.5 Set Memory Access ............................................................................................ 639
5.3.6 GPMC Timing Parameters ..................................................................................... 640
5.4 Use Cases And Tips ..................................................................................................... 651
5.4.1 How to Set GPMC Timing Parameters for Typical Accesses ............................................. 651
5.4.2 How to Choose a Suitable Memory to Use With the GPMC .............................................. 659
5.5 Registers .................................................................................................................. 663
5.5.1 GPMC_REVISION .............................................................................................. 664
5.5.2 GPMC_SYSCONFIG ........................................................................................... 664
5.5.3 GPMC_SYSSTATUS ........................................................................................... 665
5.5.4 GPMC_IRQSTATUS ........................................................................................... 666
5.5.5 GPMC_IRQENABLE ........................................................................................... 667
5.5.6 GPMC_TIMEOUT_CONTROL ................................................................................ 668
5.5.7 GPMC_ERR_ADDRESS ....................................................................................... 668
5.5.8 GPMC_ERR_TYPE ............................................................................................. 669
5.5.9 GPMC_CONFIG ................................................................................................ 670
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5.5.10 GPMC_STATUS ............................................................................................... 671
5.5.11 GPMC_CONFIG1_i ............................................................................................ 672
5.5.12 GPMC_CONFIG2_i ............................................................................................ 675
5.5.13 GPMC_CONFIG3_i ............................................................................................ 676
5.5.14 GPMC_CONFIG4_i ............................................................................................ 678
5.5.15 GPMC_CONFIG5_i ............................................................................................ 680
5.5.16 GPMC_CONFIG6_i ............................................................................................ 681
5.5.17 GPMC_CONFIG7_i ............................................................................................ 682
5.5.18 GPMC_NAND_COMMAND_i ................................................................................ 683
5.5.19 GPMC_NAND_ADDRESS_i .................................................................................. 683
5.5.20 GPMC_NAND_DATA_i ....................................................................................... 683
5.5.21 GPMC_PREFETCH_CONFIG1 .............................................................................. 684
5.5.22 GPMC_PREFETCH_CONFIG2 .............................................................................. 686
5.5.23 GPMC_PREFETCH_CONTROL ............................................................................. 686
5.5.24 GPMC_PREFETCH_STATUS ............................................................................... 687
5.5.25 GPMC_ECC_CONFIG ........................................................................................ 688
5.5.26 GPMC_ECC_CONTROL ..................................................................................... 689
5.5.27 GPMC_ECC_SIZE_CONFIG ................................................................................. 690
5.5.28 GPMC_ECCj_RESULT ....................................................................................... 692
5.5.29 GPMC_BCH_RESULT0_i .................................................................................... 693
5.5.30 GPMC_BCH_RESULT1_i .................................................................................... 693
5.5.31 GPMC_BCH_RESULT2_i .................................................................................... 693
5.5.32 GPMC_BCH_RESULT3_i .................................................................................... 694
5.5.33 GPMC_BCH_SWDATA ....................................................................................... 694
5.5.34 GPMC_BCH_RESULT4_i .................................................................................... 694
5.5.35 GPMC_BCH_RESULT5_i .................................................................................... 695
5.5.36 GPMC_BCH_RESULT6_i .................................................................................... 695
6 High-Definition Multimedia Interface (HDMI) ........................................................................ 697
6.1 Introduction ............................................................................................................... 698
6.1.1 Overview ......................................................................................................... 698
6.1.2 Main Features ................................................................................................... 698
6.1.3 Functional Block Diagram ...................................................................................... 699
6.1.4 Video Formats and Timings ................................................................................... 699
6.1.5 Environment ..................................................................................................... 701
6.2 Architecture ............................................................................................................... 702
6.2.1 Clock Configuration ............................................................................................. 702
6.2.2 Signals ............................................................................................................ 703
6.2.3 Integration ........................................................................................................ 703
6.2.4 Software Reset .................................................................................................. 703
6.2.5 Power Management ............................................................................................ 705
6.2.6 Interrupt Requests .............................................................................................. 706
6.2.7 DMA Requests .................................................................................................. 706
6.2.8 HDCP Key Interface ............................................................................................ 706
6.2.9 Wrapper Functions .............................................................................................. 706
6.2.10 TXPHY Functions .............................................................................................. 716
6.2.11 Programming Video Input Mode and Video Output Mode ................................................ 717
6.3 Registers .................................................................................................................. 718
6.3.1 HDMI_WP Register Descriptions ............................................................................. 718
6.3.2 HDMI_IP_CORE_SYSTEM Register Descriptions ......................................................... 734
6.3.3 HDMI_IP_CORE_GAMUT Register Descriptions .......................................................... 808
6.3.4 HDMI_IP_CORE_AUDIO_VIDEO Register Descriptions .................................................. 811
6.3.5 HDMI_IP_CORE_CEC Register Descriptions ............................................................... 834
6.3.6 HDMI_PHY Register Descriptions ............................................................................ 843
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7 Inter-Integrated Circuit (I2C) Controller Module ................................................................... 845
7.1 Introduction ............................................................................................................... 846
7.1.1 Overview ......................................................................................................... 846
7.1.2 Functional Block Diagram ...................................................................................... 846
7.1.3 Features .......................................................................................................... 846
7.2 Architecture ............................................................................................................... 847
7.2.1 I2C Master/Slave Contoller Signals .......................................................................... 847
7.2.2 I2C Reset ........................................................................................................ 848
7.2.3 Data Validity ..................................................................................................... 848
7.2.4 START & STOP Conditions ................................................................................... 849
7.2.5 I2C Operation .................................................................................................... 849
7.2.6 Arbitration ........................................................................................................ 851
7.2.7 I2C Clock Generation and I2C Clock Synchronization ..................................................... 851
7.2.8 Prescaler (SCLK/ICLK) ......................................................................................... 852
7.2.9 Noise Filter ....................................................................................................... 852
7.2.10 I2C Interrupts ................................................................................................... 852
7.2.11 DMA Events .................................................................................................... 853
7.2.12 Interrupt and DMA Events .................................................................................... 853
7.2.13 FIFO Management ............................................................................................. 853
7.2.14 How to Program I2C ........................................................................................... 857
7.3 Registers .................................................................................................................. 858
7.3.1 Module Revision Register (LOW BYTES) (I2C_REVNB_LO) ............................................. 859
7.3.2 Module Revision Register (HIGH BYTES) (I2C_REVNB_HI) ............................................. 860
7.3.3 System Configuration Register (I2C_SYSC) ................................................................ 861
7.3.4 I2C End of Interrupt Register (I2C_EOI) ..................................................................... 862
7.3.5 I2C Status Raw Register (I2C_IRQSTATUS_RAW) ....................................................... 862
7.3.6 I2C Status Register (I2C_IRQSTATUS) ..................................................................... 867
7.3.7 I2C Interrupt Enable Set Register (I2C_IRQENABLE_SET) .............................................. 869
7.3.8 I2C Interrupt Enable Clear Register (I2C_IRQENABLE_CLR) ........................................... 871
7.3.9 I2C Wakeup Enable Register (I2C_WE) ..................................................................... 873
7.3.10 Receive DMA Enable Set Register (I2C_DMARXENABLE_SET) ...................................... 876
7.3.11 Transmit DMA Enable Set Register (I2C_DMATXENABLE_SET) ...................................... 876
7.3.12 Receive DMA Enable Clear Register (I2C_DMARXENABLE_CLR) .................................... 877
7.3.13 Transmit DMA Enable Clear Register (I2C_DMATXENABLE_CLR) ................................... 877
7.3.14 Receive DMA Wakeup Register (I2C_DMARXWAKE_EN) .............................................. 878
7.3.15 Transmit DMA Wakeup Register (I2C_DMATXWAKE_EN) .............................................. 880
7.3.16 System Status Register (I2C_SYSS) ........................................................................ 882
7.3.17 Buffer Configuration Register (I2C_BUF) ................................................................... 882
7.3.18 Data Counter Register (I2C_CNT) ........................................................................... 884
7.3.19 Data Access Register (I2C_DATA) .......................................................................... 885
7.3.20 I2C Configuration Register (I2C_CON) ..................................................................... 886
7.3.21 I2C Own Address Register (I2C_OA) ....................................................................... 888
7.3.22 I2C Slave Address Register (I2C_SA) ...................................................................... 889
7.3.23 I2C Clock Prescaler Register (I2C_PSC) ................................................................... 890
7.3.24 I2C SCL Low Time Register (I2C_SCLL) ................................................................... 891
7.3.25 I2C SCL High Time Register (I2C_SCLH) .................................................................. 891
7.3.26 System Test Register (I2C_SYSTEST) ..................................................................... 892
7.3.27 I2C Buffer Status Register (I2C_BUFSTAT) ............................................................... 895
7.3.28 Own Address 1 (OA1) (I2C_OA1) ........................................................................... 896
7.3.29 I2C Own Address 2 Register (I2C_OA2) ................................................................... 897
7.3.30 I2C Own Address 3 Register (I2C_OA3) ................................................................... 898
7.3.31 Active Own Address Register (I2C_ACTOA) ............................................................... 899
7.3.32 I2C Clock Blocking Enable Register (I2C_SBLOCK) ..................................................... 900
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8 Interrupt Controller .......................................................................................................... 901
8.1 Introduction ............................................................................................................... 902
8.1.1 Overview ......................................................................................................... 902
8.1.2 Functional Block Diagram ...................................................................................... 902
8.1.3 Environment ..................................................................................................... 902
8.1.4 ARM A8—Interrupt Controller Integration .................................................................... 904
8.2 Architecture ............................................................................................................... 905
8.2.1 Clocking and Reset ............................................................................................. 905
8.2.2 Interrupt Request Lines ........................................................................................ 905
8.2.3 Interrupt Processing ............................................................................................ 905
8.2.4 Module Power Saving .......................................................................................... 907
8.2.5 Error Handling ................................................................................................... 907
8.2.6 Interrupt Latency ................................................................................................ 907
8.3 Basic Programming Model .............................................................................................. 908
8.3.1 Initialization Sequence ......................................................................................... 908
8.3.2 INTC Processing Sequence ................................................................................... 908
8.3.3 INTC Preemptive Processing Sequence ..................................................................... 912
8.3.4 Interrupt Preemption ............................................................................................ 916
8.3.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. 916
8.4 Registers .................................................................................................................. 917
8.4.1 INTCPS_REVISION Register ................................................................................. 918
8.4.2 INTCPS_SYSCONFIG Register .............................................................................. 918
8.4.3 INTCPS_SYSSTATUS Register .............................................................................. 919
8.4.4 INTCPS_SIR_IRQ Register ................................................................................... 919
8.4.5 INTCPS_SIR_FIQ Register .................................................................................... 920
8.4.6 INTCPS_CONTROL Register ................................................................................. 920
8.4.7 INTCPS_PROTECTION Register ............................................................................. 921
8.4.8 INTCPS_IDLE Register ........................................................................................ 921
8.4.9 INTCPS_IRQ_PRIORITY Register ........................................................................... 922
8.4.10 INTCPS_FIQ_PRIORITY Register .......................................................................... 922
8.4.11 INTCPS_THRESHOLD Register ............................................................................ 923
8.4.12 INTCPS_ITR0-3 Registers .................................................................................... 923
8.4.13 INTCPS_MIR0-3 Registers ................................................................................... 924
8.4.14 INTCPS_MIR_CLEAR0-3 Registers ........................................................................ 924
8.4.15 INTCPS_MIR_SET0-3 Registers ............................................................................ 924
8.4.16 INTCPS_ISR_SET0-3 Registers ............................................................................. 925
8.4.17 INTCPS_ISR_CLEAR0-3 Registers ......................................................................... 925
8.4.18 INTCPS_PENDING_IRQ0-3 Registers ..................................................................... 925
8.4.19 INTCPS_PENDING_FIQ0-3 Registers ...................................................................... 926
8.4.20 INTCPS_ILR0-127 Registers ................................................................................. 926
9 Secure Digital (SD)/Secure Digital I/O (SDIO) Card Interface .................................................. 927
9.1 Introduction ............................................................................................................... 928
9.1.1 Overview ......................................................................................................... 928
9.1.2 Features .......................................................................................................... 929
9.2 Architecture ............................................................................................................... 929
9.2.1 SD/SDIO Functional Modes ................................................................................... 929
9.2.2 Resets ............................................................................................................ 933
9.2.3 Power Management ............................................................................................ 934
9.2.4 Interrupt Requests .............................................................................................. 937
9.2.5 DMA Modes ...................................................................................................... 939
9.2.6 Buffer Management ............................................................................................. 942
9.2.7 Transfer Process ................................................................................................ 945
9.2.8 Transfer or Command Status and Error Reporting ......................................................... 946
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9.2.9 Auto Command 12 Timings .................................................................................... 950
9.2.10 Transfer Stop ................................................................................................... 952
9.2.11 Output Signals Generation ................................................................................... 953
9.2.12 Card Boot Mode Management ............................................................................... 954
9.2.13 CE-ATA Command Completion Disable Management ................................................... 955
9.2.14 Test Registers .................................................................................................. 955
9.2.15 SD/SDIO Hardware Status Features ........................................................................ 956
9.3 Low-Level Programming Models ....................................................................................... 957
9.3.1 Surrounding Modules Global Initialization ................................................................... 957
9.3.2 SD/SDIO Controller Initialization Flow ....................................................................... 957
9.3.3 Operational Modes Configuration ............................................................................. 960
9.4 Registers .................................................................................................................. 962
9.4.1 IP Revision Identifier Register (SD_HL_REV) .............................................................. 963
9.4.2 IP Module Hardware Configuration Register (SD_HL_HWINFO) ........................................ 963
9.4.3 Clock Management Configuration (SD_HL_SYSCONFIG) ................................................ 963
9.4.4 System Configuration Register (SD_SYSCONFIG) ........................................................ 964
9.4.5 System Status Register (SD_SYSSTATUS) ................................................................ 966
9.4.6 Card Status Response Error (SD_CSRE) ................................................................... 966
9.4.7 System Test Register (SD_SYSTEST) ...................................................................... 967
9.4.8 Configuration Register (SD_CON) ............................................................................ 970
9.4.9 Power Counter Register (SD_PWCNT) ...................................................................... 973
9.4.10 SDMA System Address (SD_SDMASA) .................................................................... 973
9.4.11 Transfer Length Configuration Register (SD_BLK) ........................................................ 974
9.4.12 Command Argument Register (SD_ARG) .................................................................. 975
9.4.13 Command and Transfer Mode Register (SD_CMD) ...................................................... 975
9.4.14 Command Response[31:0] Register (SD_RSP10) ........................................................ 979
9.4.15 Command Response[63:32] Register (SD_RSP32) ...................................................... 979
9.4.16 Command Response[95:64] Register (SD_RSP54) ...................................................... 980
9.4.17 Command Response[127:96] Register (SD_RSP76) ..................................................... 980
9.4.18 Data Register (SD_DATA) .................................................................................... 981
9.4.19 Present State Register (SD_PSTATE) ...................................................................... 982
9.4.20 Control Register (SD_HCTL) ................................................................................. 985
9.4.21 SD System Control Register (SD_SYSCTL) ............................................................... 988
9.4.22 Interrupt Status Register (SD_STAT) ....................................................................... 990
9.4.23 Interrupt SD Enable Register (SD_IE) ...................................................................... 995
9.4.24 Interrupt Signal Enable Register (SD_ISE) ................................................................. 998
9.4.25 Auto CMD12 Error Status Register (SD_AC12) .......................................................... 1001
9.4.26 Capabilities Register (SD_CAPA) .......................................................................... 1002
9.4.27 Maximum Current Capabilities Register (SD_CUR_CAPA) ............................................ 1004
9.4.28 Force Event Register for Error Interrupt Status (SD_FE) ............................................... 1005
9.4.29 ADMA Error Status Register (SD_ADMAES) ............................................................. 1007
9.4.30 ADMA System Address Low Bits Register (SD_ADMASAL) ........................................... 1008
9.4.31 ADMA System Address High Bits Register (SD_ADMASAH) .......................................... 1008
9.4.32 Versions Register (SD_REV) ............................................................................... 1009
10 Multichannel Audio Serial Port (McASP) ........................................................................... 1011
10.1 Introduction .............................................................................................................. 1012
10.1.1 Purpose of the Peripheral ................................................................................... 1012
10.1.2 Features ....................................................................................................... 1012
10.1.3 Protocols Supported ......................................................................................... 1012
10.1.4 Functional Block Diagram ................................................................................... 1014
10.1.5 Supported Use Case Statement ............................................................................ 1017
10.1.6 Industry Standard Compliance Statement ................................................................ 1017
10.1.7 Definition of Terms ........................................................................................... 1021
10 Contents SPRUGX9–15 April 2011
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