Texas Instruments TPS25948EVM User manual

User's Guide
TPS25948EVM Evaluation Module for TPS25948 eFuse
ABSTRACT
This user’s guide describes the evaluation module (EVM) for the TPS25948 eFuse. The TPS25948 device is
a 3.5-V to 23-V, 8-A eFuse with integrated 13-mΩ FET with reverse current protection, overcurrent protection,
inrush current protection, adjustable overcurrent transient blanking timer, and programmable undervoltage and
overvoltage protection.
Caution
Hot surface.
Contact can cause burns.
Do not touch!
Note
TP1(VIN1), TP14(VIN2), TP2(VOUT1), TP15(VOUT2) are Kelvin-sense test points and not a good
choice for carrying high current. Do not apply power to these test points. Use connectors present on
EVM for applying power.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 EVM Features.................................................................................................................................................................... 3
1.2 EVM Applications............................................................................................................................................................... 3
2 Description.............................................................................................................................................................................. 3
3 Schematic................................................................................................................................................................................4
4 General Configurations..........................................................................................................................................................5
4.1 Physical Access................................................................................................................................................................. 5
4.2 Test Equipment and Setup................................................................................................................................................. 7
5 Test Setup and Procedures....................................................................................................................................................8
5.1 Hot-Plug Test......................................................................................................................................................................9
5.2 Overcurrent Test...............................................................................................................................................................10
5.3 Output Hot-Short Test.......................................................................................................................................................11
5.4 Wakeup into Short Test.................................................................................................................................................... 12
5.5 Overvoltage Test.............................................................................................................................................................. 13
5.6 Priority Power Mux Test................................................................................................................................................... 14
6 EVAL Board Assembly Drawings and Layout Guidelines................................................................................................ 15
6.1 PCB Drawings..................................................................................................................................................................15
7 Bill Of Materials (BOM).........................................................................................................................................................17
8 Revision History................................................................................................................................................................... 20
List of Figures
Figure 3-1. TPS25948EVM eFuse Evaluation Board Schematic................................................................................................ 4
Figure 5-1. TPS25948EVM Setup with Test Equipment.............................................................................................................. 8
Figure 5-2. TPS25948 Output Rise Profile (VIN = 12 V, Cout = 220 µF, CdVdT = OPEN, RILM = 536 Ω, No Load)................... 9
Figure 5-3. Overcurrent Response of TPS25948 for 9-A Current Limit Setting.........................................................................10
Figure 5-4. Output Hot-Short Response of the TPS25948 Device at Vin = 12 V, Cout = Open, RILM = 536 Ω..........................11
Figure 5-5. Test Waveform of Wakeup Into Output Short for the TPS25948 Device at Vin = 12 V, Cout = Open, RILM =
536 Ω......................................................................................................................................................................................12
Figure 5-6. Overvoltage Protection Response of the TPS25948 Device...................................................................................13
Figure 5-7. Priority PowerMux Test on TPS25948.....................................................................................................................14
Figure 6-1. TPS25948EVM Board (a) Top Assembly (b) Bottom Assembly..............................................................................15
www.ti.com Table of Contents
SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
TPS25948EVM Evaluation Module for TPS25948 eFuse 1
Copyright © 2023 Texas Instruments Incorporated

Figure 6-2. TPS25948EVM Board (a) Top Layer (b) Bottom Layer........................................................................................... 16
List of Tables
Table 2-1. TPS25948EVM eFuse Evaluation Board Options and Setting................................................................................... 3
Table 4-1. Input and Output Connector Functionality.................................................................................................................. 5
Table 4-2. Test Points Description............................................................................................................................................... 5
Table 4-3. Jumper Descriptions and Default Positions................................................................................................................ 6
Table 4-4. LED Descriptions........................................................................................................................................................ 7
Table 5-1. Default Jumper Setting for TPS25948EVM eFuse Evaluation Board......................................................................... 8
Table 7-1. Bill of Materials..........................................................................................................................................................17
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
2TPS25948EVM Evaluation Module for TPS25948 eFuse SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

1 Introduction
The TPS25948EVM eFuse evaluation board allows reference circuit evaluation of the Texas Instruments
TPS25948 eFuse. The TPS25948 device is a 3.5-V to 23-V, 8-A eFuse with integrated 13-mΩ FET with reverse
current protection, overcurrent protection, inrush current protection, adjustable over current transient blanking
timer, and programmable undervoltage and overvoltage protection.
1.1 EVM Features
General TPS25948EVM eFuse evaluation board features include:
• 3.5-V to 23-V (typical) operation
• 1-A to 9-A programmable current limit using onboard jumpers
• Programmable output voltage slew rate control
• Programmable transient current blanking timer
• Programmable current limit
• Power mux configuration
• TVS diode for input transient protection
• Onboard Schottky diode at output prevents negative spike during overcurrent faults
• LED status for Power Good and fault indication
1.2 EVM Applications
This EVM can be used for the following applications:
• Smartphone and tablet
• PC and notebook
• USB port protection
• Power MUXing/ORing
• Adapter and charger input protection
2 Description
The TPS25948EVM eFuse evaluation board has two channels and enables evaluation of TPS259480A and
TPS259482L eFuses from TPS25948 family. Channels 1 and 2 share a common ground plane and provide
option to evaluate power muxing and paralleling capabilities of TPS25948 eFuse. The channels provide
programmable OVLO, ITIMER, dVdt, and ILM settings. The input power is applied at connectors J2 and J12,
while J1 and J11 provide the output connection for channels 1 and 2 respectively. Refer to the schematic in
Figure 3-1 and the EVM test setup in Figure 5-1.
TVS diodes U2 and U5 provide input protection from transient overvoltages, while Schottky diode D2 and D8
provide output protection for the TPS25948 eFuses in channels 1 and 2 respectively. S1 and S2 allows U1 and
U2 to be RESET or disabled. A supply good (SPLYGD) indicator is provided by D1 and D7.
Table 2-1. TPS25948EVM eFuse Evaluation Board Options and Setting
EVM Function Channel Vin UVLO
Threshold
Vin OVLO
Threshold ITimer Output Slew Rate,
dVdt
Current Limit
Low Setting Hi Setting
3.5-V to 23-V, 8-A eFuse
CH1 10.84 V
Selectable OVLO – 13.8
V, 16.4 V, 21.5 V
Note: Adjust UVLO
resistor divider to keep
UVLO threshold below
OVLO
Selectable – 170
us, 1.7 ms, 17
ms
Selectable – 1.5
mV/us, 0.5 mV/us,
0.23 mV/us
1 A 9 A
CH2 10.84V
Selectable OVLO – 13.8
V, 16.4 V, 21.5 V
Note: Adjust UVLO
resistor divider to keep
UVLO threshold below
OVLO
Selectable – 170
us, 1.7 ms, 17
ms
Selectable – 1.5
mV/us, 0.5 mV/us,
0.23 mV/us
1 A 9 A
www.ti.com Introduction
SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
TPS25948EVM Evaluation Module for TPS25948 eFuse 3
Copyright © 2023 Texas Instruments Incorporated

3 Schematic
Figure 3-1 illustrates the EVM schematic.
Figure 3-1. TPS25948EVM eFuse Evaluation Board Schematic
Schematic www.ti.com
4TPS25948EVM Evaluation Module for TPS25948 eFuse SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

4 General Configurations
4.1 Physical Access
Table 4-1 lists the TPS25948EVM eFuse evaluation board input and output connector functionality. Table 4-2
and Table 4-3 describe the test point availability and the jumper functionality. Table 4-4 describes the function of
signal LEDs.
Table 4-1. Input and Output Connector Functionality
Channel Connector Label Description
CH1 J2 VIN1(+), PGND(–) Input of CH1
J1 VOUT1(+), PGND(–) Output of CH1
CH2 J12 VIN2(+), PGND(–) Input of CH2
J11 VOUT2(+), PGND(–) Output of CH2
Table 4-2. Test Points Description
Channel Test Points Label Description
CH1
TP1 VIN1 CH1 input voltage
TP2 VOUT1 CH1 output voltage
TP4 EN/UVLO1 CH1 EN/UVLO signal
TP5 OVLO1 CH1 OVLO signal
TP6 ITIMER1 CH1 ITIMER signal
TP7 dVdt1 CH1 output voltage ramp control
TP8 ILM1 CH1 current limit and monitor signal
TP10 FLTb1 CH1 fault signal
TP9 SPLYGD1 CH1 supply good signal
TP13 GND1 CH1 IC GND signal
CH2
TP14 VIN2 CH2 input voltage
TP15 VOUT2 CH2 output voltage
TP16 EN/UVLO2 CH2 EN/UVLO signal
TP17 OVLO2 CH2 OVLO signal
TP18 ITIMER2 CH2 ITIMER signal
TP19 dVdt2 CH2 output voltage ramp control
TP20 ILM2 CH2 current limit and monitor signal
TP22 RCBCTRL2 CH2 reverse current blocking control signal
TP21 SPLYGD2 CH2 supply good signal
TP25 GND2 CH2 IC GND signal
CH1 & CH2
TP3 VCC_EXT External VCC voltage point for CH1 and CH2
TP11,TP12,TP23,
TP24 PGND Common Power GND for CH1 and CH1
www.ti.com General Configurations
SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
TPS25948EVM Evaluation Module for TPS25948 eFuse 5
Copyright © 2023 Texas Instruments Incorporated

Table 4-3. Jumper Descriptions and Default Positions
Channel Jumper Label Description Default Jumper Position
CH1
J5 dVdt1
1-2 position sets the output slew rate to 1.5 mV/us
3-43-4 position sets the output slew rate to 0.5 mV/us
5-6 position sets the output slew rate to 0.23 mV/us
J6 ILM1
1-2 position sets the current limit to 1 A
7-8
3-4 position sets the current limit to 3 A
5-6 position sets the current limit to 4.5 A
7-8 position sets the current limit to 9 A
J8 ITIMER1
1-2 position sets the transient current blanking period to 170 us
3-43-4 position sets the transient current blanking period to 1.7 ms
5-6 position sets the transient current blanking period to 17 ms
J7 OVLO1
1-2 position sets input OVLO threshold at 13.8 V
3-43-4 position sets input OVLO threshold at 16.4 V
5-6 position sets input OVLO threshold at 21.5 V
J4 OVLO1_VIN1 Connects OVLO pin to VIN resistor ladder 1-2
J3 UVLO1_VIN1 Connects UVLO pin to VIN resistor ladder 1-2
J15 dVdt2
1-2 position sets the output slew rate to 1.5 mV/us
3-43-4 position sets the output slew rate to 0.5 mV/us
5-6 position sets the output slew rate to 0.23 mV/us
J16 ILM2
1-2 position sets the current limit to 1 A
7-8
3-4 position sets the current limit to 3 A
5-6 position sets the current limit to 4.5 A
CH2
7-8 position sets the current limit to 9 A
J19 ITIMER2
1-2 position sets the transient current blanking period to 170 us
3-43-4 position sets the transient current blanking period to 1.7 ms
5-6 position sets the transient current blanking period to 17 ms
J18 OVLO2
1-2 position sets input OVLO threshold at 13.8 V
3-43-4 position sets input OVLO threshold at 16.4 V
5-6 position sets input OVLO threshold at 21.5 V
J20 OVLO2_SPLYG
D1
1-2 Position connects the SPLYGD1 with OVLO2. Use this setting
for Power Muxing operation of U1 and U2 2-3
2-3 position connects OVLO2 to VIN resistor ladder
J21 UVLO2_SPLYG
D1
1-2 Position connects the SPLYGD1 with EN/UVLO2. Use this
setting for parallel operation of U1 and U2 2-3
2-3 position connects EN/UVLO2 to VIN resistor ladder
J14 OVLO2_VIN2 Connects OVLO pin to VIN resistor ladder 1-2
J13 UVLO2_VIN2 Connects UVLO pin to VIN resistor ladder 1-2
J17 RCBCTRL2 Connects RCBCTRL to GND to disable reverse current blocking Open
CH1 &
CH2 J9 VCC connection CH-1,2
2-3 position connects onboard generated voltage, VCC as
reference for digital signals of U1 and U2 2-3
General Configurations www.ti.com
6TPS25948EVM Evaluation Module for TPS25948 eFuse SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

Table 4-4. LED Descriptions
LED Description
D1 When ON, indicates that SPLYGD is asserted for channel 1
D3 When ON, indicates that FLTb is asserted for channel 1
D7 When ON, indicates that SPLYGD is asserted for channel 2
4.2 Test Equipment and Setup
4.2.1 Power Supplies
One adjustable power supply with 0-V to 23-V output and current limit greater than 9 A.
4.2.2 Meters
One DMM minimum needed.
4.2.3 Oscilloscope
A DPO2024 or equivalent, three 10x voltage probes, and a DC current probe.
4.2.4 Loads
One resistive load or equivalent that can tolerate up to 8-A DC load at 23 V and capable of the output short.
www.ti.com General Configurations
SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
TPS25948EVM Evaluation Module for TPS25948 eFuse 7
Copyright © 2023 Texas Instruments Incorporated

5 Test Setup and Procedures
In this user's guide section, the test procedure is described for TPS25948EVM testing.
Make sure the evaluation board has default jumper settings as shown in Table 5-1.
Table 5-1. Default Jumper Setting for TPS25948EVM eFuse Evaluation Board
J7 J4 J3 J8 J5 J6 J9 J14 J18 J20 J19 J15 J16 J17
3-4 1-2 1-2 3-4 3-4 7-8 2-3 1-2 3-4 2-3 3-4 3-4 7-8 open
Negative
Positive
Negative
Power Supply
Positive
Load
Voltmeter
PRINT
HELP
ALPHA
SHIFT
ENTER
RUN
D
GE RF I
A
JB KC L
7
M8 N9 O
D
GD GD G
D
G T 3 U
0
V. WXYZ
TAB
% UTILIZATION
HUB/MAU NIC
2
BNC
4Mb/s
---
Oscilloscope
Figure 5-1. TPS25948EVM Setup with Test Equipment
Follow these instructions before starting any test and repeat again before moving to the next test:
1. Set the power supply output (VIN) to zero volts.
2. Turn ON the power supply and set the power supply output (VIN) to 12 V, current limit = 9 A.
3. Turn OFF the power supply.
4. Set the jumper setting on EVM to default position as shown in Table 5-1.
Test Setup and Procedures www.ti.com
8TPS25948EVM Evaluation Module for TPS25948 eFuse SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

5.1 Hot-Plug Test
Use the following instructions to measure the inrush current during the Hot-Plug event on channel 1:
1. Set jumper J5 position to the desired slew rate as mentioned in Table 4-3.
2. Set the input supply voltage VIN to 12 V and current limit of 9 A. Enable the power supply.
3. Hot-plug the supply between VIN1 and PGND1 points of connector J2.
4. Observe the waveform at VOUT1 (TP2) and input current with an oscilloscope to measure the slew rate and
rise time of the eFuse with a given input voltage of 12 V.
Figure 5-2 shows an example of inrush current captured on the TPS25948EVM eFuse evaluation board.
Figure 5-2. TPS25948 Output Rise Profile (VIN = 12 V, Cout = 220 µF, CdVdT = OPEN, RILM = 536 Ω, No
Load)
www.ti.com Test Setup and Procedures
SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
TPS25948EVM Evaluation Module for TPS25948 eFuse 9
Copyright © 2023 Texas Instruments Incorporated

5.2 Overcurrent Test
Use the following instructions to perform the overcurrent test on the current limit TPS25948 eFuse on channel 1:
1. Place jumper J8 to the appropriate position to obtain required blanking period as per Table 4-3.
2. Set the input supply voltage VIN to 12 V and current limit of 9 A and enable the power supply.
3. Place jumper J6 in good position to set the required current limit as per Table 4-3.
4. Apply an overload greater than the set current limit between VOUT1 and GND.
5. The device allows the overload current for the programmed ITIMER period and then starts limiting current.
Figure 5-3 shows an example of the circuit breaker test on the TPS25948EVM.
Figure 5-3. Overcurrent Response of TPS25948 for 9-A Current Limit Setting
Test Setup and Procedures www.ti.com
10 TPS25948EVM Evaluation Module for TPS25948 eFuse SLVUCK4A – MARCH 2023 – REVISED JULY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated