Texas Instruments bq24725A User manual

RSR
Adapter
4.5-24V
HOST
bq24725A
Hybrid Power
Boost Charge
Controller
SYS
Battery
Pack
N-FET Driver
N-FET Driver
1S-4S
SMBus
SMBus Controls V & I
with high accuracy
Adapter Detection
Enhanced Safety:
OCP, OVP, FET Short
Integration:
Loop Compensation; Soft-Start
Comparator
RAC
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bq24725A
SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014
bq24725A 1-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET
Selector and Advanced Circuit Protection
1 Features 3 Description
The bq24725A is a high-efficiency, synchronous
1• SMBus Host-Controlled NMOS-NMOS battery charger, offering low component count for
Synchronous Buck Converter with Programmable space-constraint, multi-chemistry battery charging
615kHz, 750kHz, and 885kHz Switching applications.
Frequencies The bq24725A utilizes two charge pumps to
• Automatic N-channel MOSFET Selection of separately drive n-channel MOSFETs (ACFET,
System Power Source from Adapter or Battery RBFET and BATFET) for automatic system power
Driven by Internal Charge Pumps source selection.
• Enhanced Safety Features for Over Voltage SMBus controlled input current, charge current, and
Protection, Over Current Protection, Battery, charge voltage DACs allow for very high regulation
Inductor and MOSFET Short Circuit Protection accuracies that can be easily programmed by the
• Programmable Input Current, Charge Voltage, system power management micro-controller.
Charge Current Limits The bq24725A uses internal input current register or
– ±0.5% Charge Voltage Accuracy up to 19.2V external ILIM pin to throttle down PWM modulation to
– ±3% Charge Current Accuracy up to 8.128A reduce the charge current.
– ±3% Input Current Accuracy up to 8.064A The bq24725A charges one, two, three or four series
– ±2% 20x Adapter Current or Charge Current Li+ cells.
Amplifier Output Accuracy Device Information(1)
• Programmable Battery Depletion Threshold, and PART NUMBER PACKAGE BODY SIZE (NOM)
Battery LEARN Function bq24725A VQFN (20) 3.50mm x 3.50mm
• Programmable Adapter Detection and Indicator (1) For all available packages, see the orderable addendum at
• Integrated Soft Start the end of the datasheet.
• Integrated Loop Compensation
• Real Time System Control on ILIM pin to Limit
Charge Current
• AC Adapter Operating Range 4.5V-24V
• 5µA Off-State Battery Discharge Current
• 0.65mA (0.8mA max) Adapter Standby Quiescent
Current
• 20-pin 3.5 x 3.5 mm2VQFN Package
2 Applications
• Portable Notebook Computers, UMPC, Ultra-Thin
Notebook, and Netbook
• Handheld Terminal
• Industrial and Medical Equipment
• Portable Equipment
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

bq24725A
SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014 www.ti.com
Table of Contents
8.4 Device Functional Modes........................................ 16
1 Features.................................................................. 18.5 Register Maps......................................................... 22
2 Applications ........................................................... 19 Application and Implementation ........................ 28
3 Description............................................................. 19.1 Application Information............................................ 28
4 Revision History..................................................... 29.2 Typical Application.................................................. 28
5 Pin Configuration and Functions......................... 39.3 Application Curves.................................................. 35
6 Specifications......................................................... 49.4 System Examples .................................................. 35
6.1 Absolute Maximum Ratings ...................................... 410 Power Supply Recommendations ..................... 36
6.2 Handling Ratings....................................................... 511 Layout................................................................... 37
6.3 Recommended Operating Conditions....................... 511.1 Layout Guidelines ................................................. 37
6.4 Thermal Information.................................................. 511.2 Layout Example ................................................... 38
6.5 Electrical Characteristics........................................... 612 Device and Documentation Support................. 39
6.6 Timing Characteristics............................................. 10 12.1 Third-Party Products Disclaimer ........................... 39
6.7 Typical Characteristics............................................ 10 12.2 Trademarks........................................................... 39
7 Parameter Measurement Information ................ 12 12.3 Electrostatic Discharge Caution............................ 39
8 Detailed Description............................................ 13 12.4 Glossary................................................................ 39
8.1 Overview................................................................. 13 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram....................................... 14 Information ........................................................... 39
8.3 Feature Description................................................. 15
4 Revision History
Changes from Original (September 2011) to Revision A Page
• Changed the format to the new TI standard .......................................................................................................................... 1
• Added the Device Information table ...................................................................................................................................... 1
• Added LODRV, HIDRV, and PHASE (2% duty cycle) to the Abs Max Table........................................................................ 4
• Added the Handling Ratings table.......................................................................................................................................... 5
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1
2
3
4
5
6 7 8 9 10
15
14
13
12
11
20 19 18 17 16
ACN
ACP
CMSRC
ACDRV
ACOK
ACDET
IOUT
SDA
SCL
ILIM
BATDRV
SRN
SRP
GND
LODRV
REGN
BTST
HIDRV
PHASE
VCC
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5 Pin Configuration and Functions
RGR Package
Top View
Pin Functions
PIN DESCRIPTION
NO. NAME
1 ACN Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for common-
mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2 ACP Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode
filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3 CMSRC ACDRV charge pump source input. Place a 4kΩresistor from CMSRC to the common source of ACFET (Q1) and
RBFET (Q2) limits the in-rush current on CMSRC pin.
4 ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET
(RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC
pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be
turned on to power the system by AC adapter. Place a 4kΩresistor from ACDRV to the gate of ACFET and RBFET
limits the in-rush current on ACDRV pin.
5 ACOK AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when
voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is
275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above
conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩpull up resistor from ACOK to
the pull-up supply rail.
6 ACDET Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK
comparator and IOUT are both active.
7 IOUT Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times
the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to
GND.
8 SDA SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩpull-
up resistor according to SMBus specifications.
9 SCL SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
10 ILIM Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM
pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the
control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled
when ILIM pin rises above 105mV.
11 BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to
turn on BATFET to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power
system from AC adapter. Place a 4kΩresistor from BATDRV to the gate of BATFET limits the in-rush current on
BATDRV pin.
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Pin Functions (continued)
PIN DESCRIPTION
NO. NAME
12 SRN Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin to a 7.5
Ωresistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode filtering
and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide
differential mode filtering. See application information about negative output voltage protection for hard shorts on battery
to ground or battery reverse connection by adding small resistor.
13 SRP Charge current sense resistor positive input. Connect SRP pin to a 10 Ωresistor first then from resistor another terminal
connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide
differential mode filtering. See application information about negative output voltage protection for hard shorts on battery
to ground or battery reverse connection by adding small resistor.
14 GND IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power
pad underneath IC.
15 LODRV Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
16 REGN Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when
voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from
REGN to GND.
17 BTST High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap
Schottky diode from REGN to BTST.
18 HIDRV High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
19 PHASE High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
20 VCC Input supply, diode OR from adapter or battery voltage. Use 10Ωresistor and 1µF capacitor to ground as low pass filter
to limit inrush current.
PowerPAD™ Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always
solder PowerPad to the board, and have vias on the PowerPAD plane connecting to analog ground and power ground
planes. It also serves as a thermal pad to dissipate the heat.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
VALUE UNIT
MIN MAX
SRN, SRP, ACN, ACP, CMSRC, VCC –0.3 30
PHASE –2 30
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK –0.3 7
Voltage range BTST, HIDRV, ACDRV, BATDRV –0.3 36 V
LODRV (2% duty cycle) –4 7
HIDVR (2% duty cycle) –4 36
PHASE (2% duty cycle) –4 30
Maximum difference SRP–SRN, ACP–ACN –0.5 0.5
voltage
Junction temperature range, TJ–40 155 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
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6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –55 155 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification –500 500
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC 0 24
PHASE -2 24
Voltage range V
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK 0 6.5
BTST, HIDRV, ACDRV, BATDRV 0 30
Maximum difference voltage SRP–SRN, ACP–ACN –0.2 0.2 V
Junction temperature range, TJ0 125 °C
6.4 Thermal Information bq24725A
THERMAL METRIC(1) UNIT
RGR (20 PIN)
RθJA Junction-to-ambient thermal resistance 46.8
RθJCtop Junction-to-case (top) thermal resistance 56.9
RθJB Junction-to-board thermal resistance 46.6 °C/W
ψJT Junction-to-top characterization parameter 0.6
ψJB Junction-to-board characterization parameter 15.3
RθJCbot Junction-to-case (bottom) thermal resistanc 4.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
4.5 V ≤VVCC ≤24 V, 0°C ≤TJ≤125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VVCC_OP VCC Input voltage operating range 4.5 24 V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG Battery voltage range 1.024 19.2 V
16.716 16.8 16.884 V
ChargeVoltage() = 0x41A0H -0.5% 0.5%
12.529 12.592 12.655 V
ChargeVoltage() = 0x3130H –0.5% 0.5%
VBAT_REG_ACC Charge voltage regulation accuracy 8.350 8.4 8.45 V
ChargeVoltage() = 0x20D0H –0.6% 0.6%
4.163 4.192 4.221 V
ChargeVoltage() = 0x1060H –0.7% 0.7%
CHARGE CURRENT REGULATION
Charge current regulation differential
VIREG_CHG_RNG VIREG_CHG = VSRP - VSRN 0 81.28 mV
voltage range
3973 4096 4219 mA
ChargeCurrent() = 0x1000H –3% 3%
1946 2048 2150 mA
ChargeCurrent() = 0x0800H –5% 5%
410 512 614 mA
Charge current regulation accuracy 10mΩ
ICHRG_REG_ACC ChargeCurrent() = 0x0200H
current sensing resistor –20% 20%
172 256 340 mA
ChargeCurrent() = 0x0100H –33% 33%
64 128 192 mA
ChargeCurrent() = 0x0080H –50% 50%
INPUT CURRENT REGULATION
Input current regulation differential voltage
VIREG_DPM_RNG VIREG_DPM = VACP – VACN 0 80.64 mV
range
3973 4096 4219 mA
InputCurrent() = 0x1000H –3% 3%
1946 2048 2150 mA
InputCurrent() = 0x0800H –5% 5%
Input current regulation accuracy 10mΩ
IDPM_REG_ACC current sensing resistor 870 1024 1178 mA
InputCurrent() = 0x0400H –15% 15%
384 512 640 mA
InputCurrent() = 0x0200H –25% 25%
INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER
VACP/N_OP Input common mode range Voltage on ACP/ACN 4.5 24 V
VSRP/N_OP Output common mode range Voltage on SRP/SRN 0 19.2 V
VIOUT IOUT output voltage range 0 3.3 V
IIOUT IOUT output current 0 1 mA
AIOUT Current sense amplifier gain V(ICOUT)/V(SRP-SRN) or V(ACP-ACN) 20 V/V
V(SRP-SRN) or V(ACP-ACN) = 40.96mV –2% 2%
V(SRP-SRN) or V(ACP-ACN) = 20.48mV –4% 4%
V(SRP-SRN) or V(ACP-ACN) = 10.24mV –15% 15%
VIOUT_ACC Current sense output accuracy V(SRP-SRN) or V(ACP-ACN) = 5.12mV –20% 20%
V(SRP-SRN) or V(ACP-ACN) = 2.56mV –33% 33%
V(SRP-SRN) or V(ACP-ACN) = 1.28mV –50% 50%
CIOUT_MAX Maximum output load capacitance For stability with 0 to 1mA load 100 pF
REGN REGULATOR
VREGN_REG REGN regulator voltage VVCC > 6.5V, VACDET > 0.6V (0-45mA load) 5.5 6 6.5 V
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Electrical Characteristics (continued)
4.5 V ≤VVCC ≤24 V, 0°C ≤TJ≤125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREGN = 0V, VVCC > UVLO charge enabled and not in 50 75 mA
TSHUT
IREGN_LIM REGN current limit VREGN = 0V, VVCC > UVLO charge disabled or in 7 14 mA
TSHUT
REGN output capacitor required for ILOAD = 100µA to 50mA 1
CREGN µF
stability
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
Under voltage rising threshold VVCC rising 3.5 3.75 4 V
UVLO Under voltage hysteresis, falling VVCC falling 340 mV
FAST DPM COMPARATOR (FAST_DPM)
Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage
VFAST_DPM 103% 107% 111%
across input sense resistor rising edge
QUIESCENT CURRENT
Battery BATFET OFF STATE Current, VVBAT = 16.8V, VCC disconnect from battery, BATFET
BATFET off,
IBAT_BATFET_OFF 5 µA
charge pump off, BATFET turns off, TJ= 0 to 85°C
ISRP + ISRN + IPHASE + IACP + IACN
Battery BATFET ON STATE Current, VVBAT = 16.8V, VCC connect from battery, BATFET
BATFET on,
IBAT_BATFET_ON 25 µA
charge pump on, BATFET turns on, TJ= 0 to 85°C
ISRP + ISRN + IPHASE + IVCC + IACP + IACN
Standby quiescent current, IVCC + IACP + VVCC > UVLO, VACDET > 0.6V, charge disabled,
ISTANDBY 0.65 0.8 mA
IACN TJ= 0 to 85°C
Adapter bias current during charge, VVCC > UVLO, 2.4V < VACDET < 3.15V,
IAC_NOSW 1.5 3 mA
IVCC + IACP + IACN charge enabled, no switching, TJ= 0 to 85°C
Adapter bias current during charge, VVCC > UVLO, 2.4V < VACDET < 3.15V,
IAC_SW 10 mA
IVCC + IACP + IACN charge enabled, switching, MOSFET Sis412DN
ACOK COMPARATOR
VACOK_RISE ACOK rising threshold VVCC > UVLO, VACDET rising 2.376 2.4 2.424 V
VACOK_FALL_HYS ACOK falling hysteresis VVCC> UVLO, VACDET falling 35 55 75 mV
VVCC> UVLO, VACDET rising above 2.4V, 100 150 200 ms
First time OR ChargeOption() bit [15] = 0
VACOK_RISE_DEG ACOK rising deglitch (Specified by design) VVCC> UVLO, VACDET rising above 2.4V,
(NOT First time) AND ChargeOption() bit [15] = 1 0.9 1.3 1.7 s
(Default)
VWAKEUP_RISE WAKEUP detect rising threshold VVCC> UVLO, VACDET rising 0.57 0.8 V
VWAKEUP_FALL WAKEUP detect falling threshold VVCC> UVLO, VACDET falling 0.3 0.51 V
VCC to SRN COMPARATOR (VCC_SRN)
VVCC-SRN_FALL VCC-SRN falling threshold VVCC falling towards VSRN 70 125 200 mV
VVCC-SRN _RHYS VCC-SRN rising hysteresis VVCC rising above VSRN 100 150 200 mV
ACN to SRN COMPARATOR (ACN_SRN)
VACN-SRN_FALL ACN to BAT falling threshold VACN falling towards VSRN 120 200 280 mV
VACN-SRN_RHYS ACN to BAT rising hysteresis VACN rising above VSRN 40 80 120 mV
HIGH SIDE IFAULT COMPARATOR (IFAULT_HI)(1)
ChargeOption() bit [8] = 1 (Default) 450 750 1200
VIFAULT_HI_RISE ACP to PHASE rising threshold mV
ChargeOption() bit [8] = 0 Disable function
LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)(1)
ChargeOption() bit [7] = 0 (Default) 70 135 220
VIFAULT_LOW_RISE PHASE to GND rising threshold mV
ChargeOption() bit [7] = 1 140 230 340
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV ACDET over voltage rising threshold VACDET rising 3.05 3.15 3.25 V
VACOV_HYS ACDET over voltage falling hysteresis VACDET falling 50 75 100 mV
INPUT OVER-CURRENT COMPARATOR (ACOC)(1)
Adapter over current rising threshold with ChargeOption() bit [1] = 1 (Default) 300% 333% 366%
VACOC respect to input current limit, voltage ChargeOption() bit [1] = 0 Disable function
across input sense resistor rising edge
(1) User can adjust threshold via SMBus ChargeOption() REG0x12.
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Electrical Characteristics (continued)
4.5 V ≤VVCC ≤24 V, 0°C ≤TJ≤125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ChargeOption() Bit [1] = 1 (333%),
VACOC_min Min ACOC threshold clamp voltage 40 45 50 mV
InputCurrent () = 0x0400H (10.24mV)
ChargeOption() Bit [1] = 1 (333%),
VACOC_max Max ACOC threshold clamp voltage 135 150 165 mV
InputCurrent () = 0x1F80H (80.64mV)
Voltage across input sense resistor rising to disable
tACOC_DEG ACOC deglitch time (Specified by design) 2.3 4.2 6.6 ms
charge
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
VOVP_RISE Over voltage rising threshold as VSRN rising 103% 104% 106%
percentage of VBAT_REG
VOVP_FALL Over voltage falling threshold as VSRN falling 102%
percentage of VBAT_REG
CHARGE OVER-CURRENT COMPARATOR (CHG_OCP)
ChargeCurrent()=0x0xxxH 54 60 66 mV
Charge over current rising threshold,
VOCP_RISE measure voltage drop across current ChargeCurrent()=0x1000H – 0x17C0H 80 90 100 mV
sensing resistor ChargeCurrent()=0x1800 H– 0x1FC0H 110 120 130 mV
CHARGE UNDER-CURRENT COMPARATOR (CHG_UCP)
VUCP_FALL Charge under-current falling threshold VSRP falling towards VSRN 1 5 9 mV
LIGHT LOAD COMPARATOR (LIGHT_LOAD)
VLL_FALL Light load falling threshold 1.25 mV
Measure the voltage drop across current sensing
resistor
VLL_RISE_HYST Light load rising hysteresis 1.25 mV
BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1]
ChargeOption() bit [12:11] = 00 55.53% 59.19% 63.5%
Battery depletion falling threshold, ChargeOption() bit [12:11] = 01 58.68% 62.65% 67.5%
VBATDEPL_FALL percentage of voltage regulation limit, VSRN ChargeOption() bit [12:11] = 10 62.17% 66.55% 71.5%
falling ChargeOption() bit [12:11] = 11 (Default) 66.06% 70.97% 77%
ChargeOption() bit [12:11] = 00 225 305 400 mV
ChargeOption() bit [12:11] = 01 240 325 430 mV
Battery depletion rising hysteresis, VSRN
VBATDEPL_RHYST rising ChargeOption() bit [12:11] = 10 255 345 450 mV
ChargeOption() bit [12:11] = 11 (Default) 280 370 490 mV
Battery Depletion Rising Deglitch Delay to turn off ACFET and turn on BATFET during
tBATDEPL_RDEG 600 ms
(Specified by design) LEARN cycle
BATTERY LOWV COMPARATOR (BAT_LOWV)
VBATLV_FALL Battery LOWV falling threshold VSRN falling 2.4 2.5 2.6 V
VBATLV_RHYST Battery LOWV rising hysteresis VSRN rising 200 mV
IBATLV Battery LOWV charge current limit 10 mΩcurrent sensing resistor 0.5 A
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT Thermal shutdown rising temperature Temperature rising 155 °C
TSHUT_HYS Thermal shutdown hysteresis, falling Temperature falling 20 °C
ILIM COMPARATOR
VILIM_FALL ILIM as CE falling threshold VILIM falling 60 75 90 mV
VILIM_RISE ILIM as CE rising threshold VILIM rising 90 105 120 mV
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold 0.8 V
VIN_ HI Input high threshold 2.1 V
IIN_ LEAK Input bias current V = 7 V –1 1 μA
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)
VOUT_ LO Output saturation voltage 5 mA drain current 500 mV
IOUT_ LEAK Leakage current V = 7 V –1 1 μA
ANALOG INPUT (ACDET, ILIM)
IIN_ LEAK Input bias current V = 7 V –1 1 μA
PWM OSCILLATOR
FSW PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz
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Electrical Characteristics (continued)
4.5 V ≤VVCC ≤24 V, 0°C ≤TJ≤125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSW+ PWM increase frequency ChargeOption() bit [10:9] = 11 665 885 1100 kHz
FSW– PWM decrease frequency ChargeOption() bit [10:9] = 01 465 615 765 kHz
BATFET GATE DRIVER (BATDRV)
IBATFET BATDRV charge pump current limit 40 60 µA
VBATFET Gate drive voltage on BATFET VBATDRV - VSRN when VSRN > UVLO 5.5 6.1 6.5 V
Minimum load resistance between
RBATDRV_LOAD 500 kΩ
BATDRV and SRN
RBATDRV_OFF BATDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ
ACFET GATE DRIVER (ACDRV)
IACFET ACDRV charge pump current limit 40 60 μA
VACFET Gate drive voltage on ACFET VACDRV–VCMSRC when VVCC> UVLO 5.5 6.1 6.5 V
Minimum load resistance between ACDRV
RACDRV_LOAD 500 kΩ
and CMSRC
RACDRV_OFF ACDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ
ACDRV Turn-Off when Vgs voltage is low
VACFET_LOW 5.9 V
(Specified by design)
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON High side driver turn-on resistance VBTST – VPH = 5.5 V, I = 10 mA 6 10 Ω
RDS_HI_OFF High side driver turn-off resistance VBTST – VPH = 5.5 V, I = 10 mA 0.65 1.3 Ω
Bootstrap refresh comparator threshold VBTST – VPH when low side refresh pulse is requested
VBTST_REFRESH 3.85 4.3 4.7 V
voltage
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON Low side driver turn-on resistance VREGN = 6 V, I = 10 mA 7.5 12 Ω
RDS_LO_OFF Low side driver turn-off resistance VREGN = 6 V, I = 10 mA 0.9 1.4 Ω
PWM DRIVER TIMING
tLOW_HIGH Driver dead time from low side to high side 20 ns
tHIGH_LOW Driver dead time from high side to low side 20 ns
INTERNAL SOFT START
ISTEP Soft start current step 64 mA
In CCM mode 10mΩcurrent sensing resistor
tSTEP Soft start current step time 240 μs
SMBus TIMING CHARACTERISTICS
tRSCLK/SDATA rise time 1 μs
tFSCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 μs
tW(L) SCLK Pulse Width Low 4.7 μs
tSU(STA) Setup time for START condition 4.7 μs
tH(STA) START condition hold time after which first clock pulse is generated 4 μs
tSU(DAT) Data setup time 250 ns
tH(DAT) Data hold time 300 ns
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 μs
FS(CL) Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
ttimeout SMBus bus release timeout(2) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
Watchdog timeout period, ChargeOption() bit [14:13] = 01(3) 35 44 53 s
tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 10(3) 70 88 105 s
Watchdog timeout period, ChargeOption() bit [14:13] = 11(3) (Default) 140 175 210 s
(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(3) User can adjust threshold via SMBus ChargeOption() REG0x12.
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6.6 Timing Characteristics
4.5 V ≤VVCC ≤24 V, 0°C ≤TJ≤125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SMBus TIMING CHARACTERISTICS
tRSCLK/SDATA rise time 1 μs
tFSCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 μs
tW(L) SCLK Pulse Width Low 4.7 μs
tSU(STA) Setup time for START condition 4.7 μs
tH(STA) START condition hold time after which first clock pulse is generated 4 μs
tSU(DAT) Data setup time 250 ns
tH(DAT) Data hold time 300 ns
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 μs
FS(CL) Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
ttimeout SMBus bus release timeout(1) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
Watchdog timeout period, ChargeOption() bit [14:13] = 01(2) 35 44 53 s
tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 10(2) 70 88 105 s
Watchdog timeout period, ChargeOption() bit [14:13] = 11(2) (Default) 140 175 210 s
(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(2) User can adjust threshold via SMBus ChargeOption() REG0x12.
6.7 Typical Characteristics
,CH1: ILIM, 1V/div
CH1: VCC, 10V/div, CH2: ACDET 2V/div, CH3: ACOK, 5V/div CH4: inductor current 1A/div, 20ms/div
CH4: REGN, 5V/div, 40ms/div Figure 2. Charge Enable by ILIM
Figure 1. VCC, ACDET, REGN and ACOK Power Up
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Typical Characteristics (continued)
,
CH1: Vin, 10V/div , CH2: LODRV, 5V/div, CH3: PHASE, 10V/div CH1: ILIM, 1V/div
CH4: inductor current, 2A/div, 2ms/div CH4: inductor current, 1A/div, 4us/div
Figure 3. Current Soft-Start Figure 4. Charge Disable by ILIM
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH1: PHASE, 10V/div, CH2: LODRV, 5V/div
CH3: HIDRV, 10V/div CH3: HIDRV, 10V/div
CH4: inductor current, 2A/div, 400ns/div CH4: inductor current, 1A/div, 400ns/div
Figure 5. Continuous Conduction Mode Switching Figure 6. Cycle-by-Cycle Synchronous to Non-synchronous
Waveforms
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH2: battery current, 2A/div, CH3: adapter current, 2A/div
CH4: inductor current, 2A/div, 4us/div CH4: system load current, 2A/div, 100us/div
Figure 7. 100% Duty and Refresh Pulse Figure 8. System Load Transient (Input DPM)
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7 Parameter Measurement Information
Figure 9. SMBus Communication Timing Waveforms
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8 Detailed Description
8.1 Overview
The bq24725A is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry
portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources
from 4.5V to 24V, and 1-4 cell battery for a versatile solution.
The bq24725A supports automatic system power source selection with separate drivers for n-channel MOSFETS
on the adapter side and battery side.
The bq24725A features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter over-
loading. During battery charging, as the system power increases, the charging current will reduce to maintain
total input current below adapter rating.
The SMBus controls input current, charge current and charge voltage registers with high resolution, high
accuracy regulation limits.
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8.2 Functional Block Diagram
Figure 10. Functional Block Diagram for bq24725A
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SSLAVE
ADDRESS W ACK COMMAND BYTE ACK LOW DATA BYTE ACK HIGH DATA BYTE ACK P
7 BITS 1b 1b 8 BITS 1b 8 BITS 1b 8 BITS 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 0 MSB LSB 0
a) Write-Word Format
SSLAVE
ADDRESS W ACK COMMAND BYTE ACK S SLAVE ADDRESS R ACK LOW DATA
BYTE ACK HIGH DATA BYTE NACK P
7 BITS 1b 1b 8 BITS 1b 7 BITS 1b 1b 8 BITS 1b 8 BITS 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB 0 MSB LSB 1
Preset to 0b0001001 DeviceID() = 0xFFH Preset to D7 D0 D15 D8
ManufactureID() = 0xFEH 0b0001001
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
ChargeOption() = 0x12H LEGEND:
S = START CONDITION OR REPEATED START CONDITION P = STOP CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW) NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
W = WRITE BIT (LOGIC-LOW) R = READ BIT (LOGIC-HIGH)
b) Read-Word Format
MASTER TO SLAVE
SLAVE TO MASTER
Preset to 0b0001001
ChargeOption() = 0x12H
D7 D0 D15 D8
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
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8.3 Feature Description
8.3.1 SMBus Interface
The bq24725A operates as a slave, receiving control inputs from the embedded controller host through the
SMBus interface. The bq24725A uses a simplified subset of the commands documented in System Management
Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24725A uses the SMBus Read-
Word and Write-Word protocols (see Figure 11) to communicate with the smart battery. The bq24725A performs
only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the
bus. In addition, the bq24725A has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit
manufacturer ID register (0xFEH).
SMBus communication is enabled with the following conditions:
• VVCC is above UVLO;
• VACDET is above 0.6V;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 12 and
Figure 13 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24725A because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24725A
supports the charger commands as described in Table 2.
Figure 11. SMBus Write-Word and Read-Word Protocols
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A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE
B = MSB OF ADDRESS CLOCKED INTO SLAVE F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = STOP CONDITION
C = LSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO MASTER K = NEW START CONDITION
D = R/W BIT CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO MASTER
A B C D E F G H I J K
tLOW tHIGH
SMBCLK
SMBDATA
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Feature Description (continued)
Figure 12. SMBus Write Timing
Figure 13. SMBus Read Timing
8.4 Device Functional Modes
8.4.1 Adapter Detect and ACOK Output
The bq24725A uses an ACOK comparator to determine the source of power on VCC pin, either from the battery
or adapter. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The
adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage,
but lower than the maximum allowed adapter voltage.
The open drain ACOK output requires external pull up resistor to system digital rail for a high level. It can be
pulled to external rail under the following conditions:
• VVCC > UVLO;
• 2.4V < VACDET < 3.15V (not in ACOVP condition, nor in low input voltage condition);
• VVCC–VSRN > 275mV (not in sleep mode);
The first time after IC POR always gives 150ms ACOK rising edge delay no matter what the ChargeOption
register value is. Only after the ACDET pin voltage is pulled below 2.4V (but not below 0.6V, which resets the IC
and forces the next ACOK rising edge deglitch time to be 1.3s) and the ACFET has been turned off at least one
time, the 1.3s (or 150ms) delay time is effective for the next time the ACDET pin voltage goes above 2.4V. To
change this option, the VCC pin voltage must above UVLO, and the ACDET pin voltage must be above 0.6V
which enables the IC SMBus communication and sets ChargeOption() bit[15] to 0 which sets the next ACOK
rising deglitch time to be 150ms. The purpose of the default 1.3s rising edge deglitch time is to turn off the
ACFET long enough when the ACDET pin is pulled below 2.4V by excessive system current, such as over
current or short circuit.
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Device Functional Modes (continued)
8.4.2 Adapter Over Voltage (ACOVP)
When the ACDET pin voltage is higher than 3.15V, it is considered as adapter over voltage. ACOK will be pulled
low, and charge will be disabled. ACFET will be turned off to disconnect the high voltage adapter to system
during ACOVP. BATFET will be turned on if turns on conditions are valid. See the System Power Selection
section for details.
When ACDET pin voltage falls below 3.15V and above 2.4V, it is considered as adapter voltage returns back to
normal voltage. ACOK will be pulled high by external pull up resistor. BATFET will be turned off and ACFET and
RBFET will be turned on to power the system from adapter. The charge can be resumed if enable charge
conditions are valid. See the Enable and Disable Charging section for details.
8.4.3 System Power Selection
The bq24725A automatically switches adapter or battery power to system. The battery is connected to system at
POR if battery exists. The battery is disconnected from system and the adapter is connected to system after
default 150ms delay (first time, the next time default is 1.3s and can be changed to 150ms) if ACOK goes HIGH.
An automatic break-before-make logic prevents shoot-through currents when the selectors switch.
The ACDRV drives a pair of common-source (CMSRC) n-channel power MOSFETs (ACFET and RBFET)
between adapter and ACP (see Figure 18 for details). The ACFET separates adapter from battery or system, and
provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. Meanwhile it protects
adapter when system or battery is shorted. The RBFET provides negative input voltage protection and battery
discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low
RDS(on) compared to a Schottky diode.
When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting
adapter from system. BATDRV stays at VSRN + 6V to connect battery to system if all the following conditions are
valid:
• VVCC > UVLO;
• VSRN > UVLO;
• VACN < 200mV above VSRN (ACN_SRN comparator);
Approximately 150ms (first time; the next time default is 1.3s and can be changed to 150ms) after the adapter is
detected (ACDET pin voltage between 2.4V and 3.15V), the system power source begins to switch from battery
to adapter if all the following conditions are valid:
• Not in LEARN mode or in LEARN mode and VSRN is lower than battery depletion threshold;
• ACOK high
The gate drive voltage on ACFET and RBFET is VCMSRC + 6V. If the ACFET/RBFET have been turned on for
20ms, and the voltage across gate and source is still less than 5.9V, ACFET and RBFET will be turned off. After
1.3s delay, it resumes turning on ACFET and RBFET. If such a failure is detected seven times within 90
seconds, ACFET/RBFET will be latched off and an adapter removal and system shut down is required to force
ACDET < 0.6V to reset the IC. After IC reset from latch off, ACFET/RBFET can be turned on again. After 90
seconds, the failure counter will be reset to zero to prevent latch off. With ACFET/RBFET off, charge is disabled.
To turn off ACFET/RBFET, one of the following conditions must be valid:
• In LEARN mode and VSRN is above battery depletion threshold;
• ACOK low
To limit the in-rush current on ACDRV pin, CMSRC pin and BATDRV pin, a 4kΩresistor is recommended on
each of the three pins.
To limit the adapter inrush current when ACFET is turned on to power system from adapter, the Cgs and Cgd
external capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance, the slower turn
on of ACFET will be and less inrush current of adapter. However, if Cgs or Cgd is too large, the ACDRV-CMSRC
voltage may still go low after the 20ms turn on time window is expired. To make sure ACFET will not be turned
on when adapter is hot plugged in, the Cgs value should be 20 times or higher than Cgd. The most cost effective
way to reduce adapter in-rush current is to minimize system total capacitance.
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Device Functional Modes (continued)
8.4.4 Battery LEARN Cycle
A battery LEARN cycle can be activated via SMBus command (ChargeOption() bit[6]=1 enable LEARN cycle,
bit[6]=0 disable LEARN cycle). When LEARN is enabled with ACFET/RBFET connected, the system power
selector logic is over-driven to switch to battery by turning off ACFET/RBFET and turning on BATFET. LEARN
function allows the battery to discharge in order to calibrate the battery gas gauge over a complete
discharge/charge cycle. The controller automatically exits LEARN cycle when the battery voltage is below battery
depletion threshold, and the system switches back to adapter input by turning off BATFET and turning on
ACFET/RBFET. After LEARN cycle, the LEARN bit is automatically reset to 0. The battery depletion threshold
can be set to 59.19%, 62.65%, 66.55%, and 70.97% of voltage regulation level via SMBus command
(ChargeOption() bit[12:11]).
8.4.5 Enable and Disable Charging
In Charge mode, the following conditions have to be valid to start charge:
• Charge is enabled via SMBus (ChargeOption() bit [0]=0, default is 0, charge enabled);
• ILIM pin voltage higher than 105mV;
• All three regulation limit DACs have valid value programmed;
• ACOK is valid (See the Adapter Detect and ACOK Output section for details);
• ACFET and RBFET turns on and gate voltage is high enough (See the System Power Selection section for
details);
• VSRN does not exceed BATOVP threshold;
• IC Temperature does not exceed TSHUT threshold;
• Not in ACOC condition (See the Input Over Current Protection (ACOC) section for details);
One of the following conditions will stop on-going charging:
• Charge is inhibited via SMBus (ChargeOption() bit[0]=1);
• ILIM pin voltage lower than 75mV;
• One of three regulation limit DACs is set to 0 or out of range;
• ACOK is pulled low (See the Adapter Detect and ACOK Output section for details);
• ACFET turns off;
• VSRN exceeds BATOVP threshold;
• TSHUT IC temperature threshold is reached;
• ACOC is detected (See the Input Over Current Protection (ACOC) section for details);
• Short circuit is detected (See the Inductor Short, MOSFET Short Protection section for details);
• Watchdog timer expires if watchdog timer is enabled (See the Charger Timeout section for details);
8.4.6 Automatic Internal Soft-Start Charger Current
Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any
overshoot or stress on the output capacitors or the power converter. The charge current starts at 128mA, and the
step size is 64mA in CCM mode for a 10mΩcurrent sensing resistor. Each step lasts around 240µs in CCM
mode, till it reaches the programmed charge current limit. No external components are needed for this function.
During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to
the intrinsic slow response of DCM mode.
8.4.7 High Accuracy Current Sense Amplifier
As an industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current or the
charge current, selectable via SMBUS (ChargeOption() bit[5]=0 select the input current, bit[5]=1 select the
charge current) by host. The CSA senses voltage across the sense resistor by a factor of 20 through the IOUT
pin. Once VCC is above UVLO and ACDET is above 0.6V, CSA turns on and IOUT output becomes valid. To
lower the voltage on current monitoring, a resistor divider from IOUT to GND can be used and accuracy over
temperature can still be achieved.
A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay.
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o o
1
=
2 L Cp
¦
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Device Functional Modes (continued)
8.4.8 Charge Timeout
The bq24725A includes a watchdog timer to terminate charging if the charger does not receive a write
ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a
watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or
write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog
timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). After
watchdog timeout write ChargeOption() bit[14:13] to disable watchdog timer also resume charging.
8.4.9 Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage mode control scheme and internal type III
compensation network. The LC output filter gives a characteristic resonant frequency
(1)
The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin and
gain margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of
10–20 kHz nominal for the best performance. Suggest component value as charge current of 750kHz default
switching frequency is shown in Table 1.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Table 1. Suggest Component Value as Charge Current of Default 750kHz
Switching Frequency
Charge Current 2A 3A 4A 6A 8A
Output Inductor Lo (µH) 6.8 or 8.2 5.6 or 6.8 3.3 or 4.7 3.3 2.2
Output Capacitor Co (µF) 20 20 20 30 40
Sense Resistor (mΩ) 10 10 10 10 10
The bq24725A has three loops of regulation: input current, charge current and charge voltage. The three loops
are brought together internally at the error amplifier. The maximum voltage of the three loops appears at the
output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO
(see Figure 10) to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0% duty-
cycle.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth
ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh
cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve
duty cycle of up to 99.5%.
8.4.10 Continuous Conduction Mode (CCM)
With sufficient charge current the bq24725A’s inductor current never crosses zero, which is defined as
continuous conduction mode. The controller starts a new cycle with ramp coming up from 200mV. As long as
EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage
exceeds EAO voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp
gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during
transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the
body-diode of the low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turn-on keeps the power dissipation low, and allows safely charging at high currents.
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8.4.11 Discontinuous Conduction Mode (DCM)
During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the
converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls
below 5mV (0.5A on 10mΩ), the under current-protection comparator (UCP) turns off LSFET to avoid negative
inductor current, which may boost the system via the body diode of HSFET.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole
is proportional to the load current.
Both CCM and DCM are synchronous operation with LSFET turn-on every clock cycle. If the average charge
current goes below 125mA on 10mΩcurrent sensing resistor or the battery voltage falls below 2.5V, the LSFET
keeps turn-off. The battery charger operates in non-synchronous mode and the current flows through the LSFET
body diode. During non-synchronous operation, the LSFET turns on only for a refreshing pulse to charge the
BTST capacitor. If the average charge current goes above 250mA on 10mΩcurrent sensing resistor, the LSFET
exits non-synchronous mode and enters synchronous mode to reduce LSFET power loss.
8.4.12 Input Over Current Protection (ACOC)
The bq24725A cannot maintain the input current level if the charge current has been already reduced to zero.
After the system current continues increasing to the 3.33X of input current DAC set point (with 4.2ms blank out
time), ACFET/RBFET is latches off and an adapter removal and system shutdown is required to force ACDET <
0.6V to reset IC. After IC reset from latch off, ACFET/RBFET can be turned on again.
The ACOC function threshold can be set to 3.33x of input DPM current or disable this function via SMBus
command (ChargeOption() bit [1]).
8.4.13 Charge Over Current Protection (CHGOCP)
The bq24725A has a cycle-by-cycle peak over current protection. It monitors the voltage across SRP and SRN,
and prevents the current from exceeding of the threshold based on the DAC charge current set point. The high-
side gate drive turns off for the rest of the cycle when the over current is detected, and resumes when the next
cycle starts.
The charge OCP threshold is automatically set to 6A, 9A, and 12A on a 10mΩcurrent sensing resistor based on
charge current register value. This prevents the threshold to be too high which is not safe or too low which can
be triggered in normal operation. Proper inductance should be selected to prevent OCP triggered in normal
operation due to high inductor current ripple.
8.4.14 Battery Over Voltage Protection (BATOVP)
The bq24725A will not allow the high-side and low-side MOSFET to turn-on when the battery voltage at SRN
exceeds 104% of the regulation voltage set-point. If BATOVP last over 30ms, charger is completely disabled.
This allows quick response to an over-voltage condition – such as occurs when the load is removed or the
battery is disconnected. A 4mA current sink from SRP to GND is on only during BATOVP and allows discharging
the stored output inductor energy that is transferred to the output capacitors. Set ChargeVoltage() register value
to 0V will not trigger BATOVP function.
8.4.15 Battery Shorted to Ground (BATLOWV)
The bq24725A will limit inductor current if the battery voltage on SRN falls below 2.5V. After 1ms charge is reset.
After 4-5 ms the charge is resumed with soft-start if all the enable conditions in the “Enable and Disable
Charging” sections are satisfied. This prevents any overshoot current in inductor which can saturate inductor and
may damage the MOSFET. The charge current is limited to 0.5A on 10mΩcurrent sensing resistor when
BATLOWV condition persists and LSFET keeps off. The LSFET turns on only for a refreshing pulse to charge
BTST capacitor.
8.4.16 Thermal Shutdown Protection (TSHUT)
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for self-
protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction
temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16mA.
Once the temperature falls below 135°C, charge can be resumed with soft start.
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