Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
Software-Programmable
Phase-Locked Loop (PLL) Controller
Reference Guide
Literature Number: SPRU233A
April 2003

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3Title of DocSPRU233A
Preface
Read This First
About This Manual
Thisdocumentdescribestheoperation ofthe software-programmablephase-
locked loop (PLL) controller in the digital signal processors (DSPs) of the
TMS320C6000DSP family. This type of controller is used on the following
devices:
-TMS320C6711C
-TMS320C6712C
-TMS320C6713
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.

Trademarks
4Phase-Locked Loop (PLL) Controller SPRU233A
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301)introduces the CodeComposerStudiointegrateddevelop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
numberSPRU401)describes a set ofapplicationprogramminginterfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

5Phase-Locked Loop (PLL) ControllerSPRU233A
Contents
1 Overview 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Multiplier and Dividers 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reset Controller 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Configuration 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Initialization 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 PLL Mode (PLLEN = 1) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Bypass Mode (PLLEN = 0) 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Power Down 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Power Wake Up 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Registers 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PLL Controller Peripheral Identification Register (PLLPID) 15. . . . . . . . . . . . . . . . . . . . . . . .
4.2 PLL Control/Status Register (PLLCSR) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 PLL Multiplier Control Register (PLLM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 PLL Controller Divider Registers (PLLDIV0–3) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Oscillator Divider 1 Register (OSCDIV1) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6Phase-Locked Loop (PLL) Controller SPRU233A
Figures
1 PLL Controller Block Diagram 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Reset Controller Lengthening the Internal Reset Signal 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 PLL Controller Peripheral Identification Register (PLLPID) 15. . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PLL Control/Status Register (PLLCSR) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 PLL Multiplier Control Register (PLLM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 PLL Controller Divider Register (PLLDIV) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Oscillator Divider 1 Register (OSCDIV1) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1 PLL Controller Registers 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 PLL Controller Peripheral Identification Register (PLLPID) Field Descriptions 15. . . . . . . . . .
3 PLL Control/Status Register (PLLCSR) Field Descriptions 16. . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PLL Multiplier Control Register (PLLM) Field Descriptions 18. . . . . . . . . . . . . . . . . . . . . . . . . . .
5 PLL Controller Divider Register (PLLDIV) Field Descriptions 19. . . . . . . . . . . . . . . . . . . . . . . . .
6 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions 20. . . . . . . . . . . . . . . . . . . . . . . . . .

7Phase-Locked Loop (PLL) ControllerSPRU233A
Phase-Locked Loop (PLL) Controller
Thisdocumentdescribestheoperation ofthe software-programmablephase-
locked loop (PLL) controller in the digital signal processors (DSPs) of the
TMS320C6000DSP family. This type of controller is used on the following
devices:
-TMS320C6711C
-TMS320C6712C
-TMS320C6713
1 Overview
The PLL controller (Figure 1) features software-configurable PLL multiplier
controller, dividers (OSCDIV1, D0, D1, D2, and D3), and reset controller. The
PLL controller accepts an input clock, as determined by the logic state on the
CLKMODE0 pin, from the CLKIN pin or from the on-chip oscillator output
signal OSCIN. The PLL controller offers flexibility and convenience by way of
software-configurable multiplier and dividers to modify the input signal inter-
nally.TheresultingclockoutputsarepassedtotheDSPcore,peripherals,and
other modules inside the C6000DSP.
-The input reference clocks to the PLL controller:
JCLKIN: input signal from external oscillator (3.3V), CLKMODE0 = 1
JOSCIN: output signal from on-chip oscillator (1.2V), CLKMODE0 = 0
-The resulting output clocks from the PLL controller:
JAUXCLK: internal clock output signal directly from CLKIN or OSCIN.
JCLKOUT3: output of divider OSCDIV1.
JSYSCLK1: internal clock output of divider D1.
JSYSCLK2: internal clock output of divider D2.
JSYSCLK3: internal clock output of divider D3.
Refertoyourdevice-specificdatasheetonhowtheseinputsandoutputsofthe
PLL controller are used.

Overview
Phase-Locked Loop (PLL) Controller8SPRU233A
Figure 1. PLL Controller Block Diagram
1
0
CLKIN
OSCIN
CLKMODE0
Divider D0
÷1, ÷2,...÷32 PLL†
÷1, ÷2,...÷32
OSCDIV1
÷1, ÷2,...÷32
Divider D1 Divider D2
÷1, ÷2,...÷32 Divider D3
÷1, ÷2,...÷32
PLLEN
controller
Reset
PLL controller
AUXCLK SYSCLK1 SYSCLK2 SYSCLK3
CLKOUT3
10
PLLOUT
PLLM
×1, ×2,...×32
†See the device-specific datasheet for more details about the PLL.

Functional Description
9Phase-Locked Loop (PLL) ControllerSPRU233A
2 Functional Description
The following sections describe the multiplier, dividers, and reset controller in
the PLL controller.
2.1 Multiplier and Dividers
The PLL controller is capable of programming the PLL through the PLL multiplier
controlregister(PLLM)froma×1to×32multiplierrate(seethedevice-specific
datasheet for the PLL multiplier rates supported on your device). The clock
dividers (OSCDIV1, D0, D1, D2, and D3) are programmable from ÷1 to ÷32
divider ratio and may be disabled. The oscillator divider enable bit (OD1EN)
in the oscillator divider 1 register (OSCDIV1) determines the oscillator divider
output mode. When OD1EN = 0, theoscillator dividerisdisabled andno clock
isoutput; whenOD1EN =1,the oscillatordivider isenabledand aclockisout-
put. The divider enable bit (DnEN) in the PLL controller divider registers
(PLLDIVn) determines the divider output mode. When DnEN = 0, the divider
is disabled and no clock is output; when DnEN = 1, the divider is enabledand
a clock is output.
The input reference clock (either CLKIN or OSCIN) is directly output as the
auxiliaryclock(AUXCLK)forusebysomeperipherals.Forexample,themulti-
channelaudio serial port(McASP)uses AUXCLK togenerateaudio clocks.In
addition to AUXCLK, the input reference clock is directly input to the oscillator
divider (OSCDIV1). If OSCDIV1 is enabled, OD1EN = 1, the input reference
clock is divided down by the value in the oscillator divider ratio bits (RATIO) in
OSCDIV1. The output from OSCDIV1 is the output clock CLKOUT3.
The divider D0 and the PLL may also be bypassed. The PLL enable bit
(PLLEN) in the PLL control/status register (PLLCSR) determines the PLL
controller mode. When PLLEN = 1, PLL mode, D0 and PLL are used; when
PLLEN = 0, bypass mode, D0 and PLL are bypassed and the input reference
clock is directly input to dividers D1, D2, and D3.
Whenin PLL mode (PLLEN =1),the input reference clockissuppliedto divid-
erD0. If D0 is enabled, D0EN =1, theinput reference clock is divided down by
the value in the PLL divider ratio bits (RATIO) in PLLDIV0. The output from
divider D0 is input to the PLL. The PLL multiplies the clock by the value in the
PLL multiplier bits (PLLM) in the PLL multiplier control register (PLLM). The
output from the PLL (PLLOUT) is input to dividers D1, D2, and D3.
When enabled (DnEN = 1), the dividers D1, D2, and D3 divide down by the
value in RATIO in PLLDIVnthe output clock of the PLL. The output clocks of
dividers D1, D2, and D3 have 50% duty cycle and are SYSCLK1, SYSCLK2,
and SYSCLK3, respectively.

Functional Description
Phase-Locked Loop (PLL) Controller10 SPRU233A
2.2 Reset Controller
At power up, the device RESET signal may not be asserted long enough to
waitfortheon-chiporoff-chiposcillatortostabilize.Thismeanstheinputrefer-
enceclock(eitherCLKINorOSCIN)maybeabadclockwhenadeviceRESET
signal is deasserted high. After RESET is deasserted, the reset controller
lengthenstheasynchronousinternalresetsignaltoensurethattheinputclock
source is stable.
The reset controller resides within the PLL controller and the main function is
to internally lengthen the reset signal from the RESET input pin until the input
clock source is stable (after 512 CLKIN cycles or 4096 OSCIN cycles). This
istoensurethattherestofthedevicewillseetheinternalresetdeassertedonly
aftertheinputclockisstabilized.Figure2showsthelengtheningoftheinternal
reset signal.
ThePLLcontrollermultiplieranddividersarebypassedwhentheinternalreset
signalislow.ThefrequencyofallclockoutputsofthePLLcontroller(AUXCLK,
SYSCLK1, SYSCLK2, SYSCLK3, and CLKOUT3) are fixed to the input
reference clock (CLKIN or OSCIN) divided by 8. After 512 CLKIN cycles or
4096 OSCINcycles,theresetcontrollerbringsthedeviceoutofresetandsets
the oscillator input stable bit (STABLE) in the PLL control/status register
(PLLCSR). The dividers are used after this point and are set to their default
divide ratio.
Values are latched into the registers at the rising edge of RESET.

Functional Description
11Phase-Locked Loop (PLL) ControllerSPRU233A
Figure 2. Reset Controller Lengthening the Internal Reset Signal
Invalid
Ninput clock cycles†
Invalid
123
Clock may not stabilize yet
Clock now stable,
STABLE bit asserted
divide ratio. Output clocks are
Dividers now used with default
Output clocks are input reference clock/8†
with dividers in bypass mode
Core power stabilized Device released from reset
Input clock not yet
stabilized. Internal
reset stays asserted.
Register values latched.
1.2 V CVDD
RESET pin
Asynchronous
internal reset
Crystal
Input reference
Output clocks‡
divider output.
clock†
†N = 512 ×CLKIN cycles when CLKMODE = 1 (input reference clock is CLKIN);
N = 4096 ×OSCIN cycles when CLKMODE = 0 (input reference clock is OSCIN)
‡Output clocks include AUXCLK, SYSCLK1, SYSCLK2, SYSCLK3, and CLKOUT3

Configuration
Phase-Locked Loop (PLL) Controller12 SPRU233A
3 Configuration
The following sections provide procedures for initialization, power down, and
wake up of the PLL controller.
3.1 Initialization
The PLL and PLL controller are to be initialized by software after reset. The
PLL controller registers should be modified only by the CPU or via emulation.
TheHPIshouldnotbeusedtodirectlyaccessthePLLcontrollerregisters.The
initialization of the PLL controller should be performed as soon as possible at
the beginning of the program, before initializing any peripherals. Upon device
reset,one of thefollowingtwo softwareinitializationprocedures must bedone
to properly set up the PLL and PLL controller.
3.1.1 PLL Mode (PLLEN = 1)
If the system intends to use divider D0 and PLL, perform the following:
1) In PLLCSR, write PLLEN = 0 (bypass mode).
2) Wait 4 cycles of the slowest of PLLOUT, CLKIN (if CLKMODE = 1), and
OSCIN (if CLKMODE = 0).
3) In PLLCSR, write PLLRST = 1 (PLL is reset).
4) Program PLLDIV0, PLLM, and OSCDIV1.
5) Program PLLDIV1–3. Note that there must be wait states between
accesses to PLLDIV1–3. Each wait state is 8 cycles of the slowest of the
old and new SYSCLK1–3 clock rates. Some devices may also require
users to program the PLLDIV1–3 registers in a particular order, to ensure
no violation of system clock ratios. See PLL Controller section of the
device-specific datasheet for other restrictions.
6) WaitforPLLtoproperlyreset.Seedevice-specificdatasheetforPLLreset
time.
7) In PLLCSR, write PLLRST = 0 to bring PLL out of reset.
8) Wait for PLL to lock. See device-specific datasheet for PLL lock time.
9) In PLLCSR, write PLLEN = 1 to enable PLL mode.
Steps 1, 2, and 3 are required when PLLEN and PLLRST bits are not already
0and1, respectively.Thesestepsarenot required when the device is coming
out of reset (they are performed by hardware).

Configuration
13Phase-Locked Loop (PLL) ControllerSPRU233A
3.1.2 Bypass Mode (PLLEN = 0)
If the system intends to bypass divider D0 and PLL, perform the following:
1) In PLLCSR, write PLLEN = 0 (bypass mode).
2) Wait 4 cycles of the slowest of PLLOUT, CLKIN (if CLKMODE = 1), and
OSCIN (if CLKMODE = 0).
3) In PLLCSR, write PLLRST = 1 (PLL is reset).
4) Program OSCDIV1.
5) Program PLLDIV1–3. Note that there must be wait states between
accesses to PLLDIV1–3. Each wait state is 8 cycles of the slowest of the
old and new SYSCLK1–3 clock rates. See PLL Controller section of the
device-specific datasheet for other restrictions.
Steps 1, 2, and 3 are required when PLLEN and PLLRST bits are not already
0and1, respectively.Thesestepsarenot required when the device is coming
out of reset (they are performed by hardware).
3.2 Power Down
The PLL may be powered down, in which case the PLL controller is in bypass
modeandtheDSPruns from a divided down version of the input reference clock.
The DSP is still able to respond to events because it is still being clocked by the
bypass clock (directly from CLKIN or OSCIN), although at a lower frequency.
Perform the following procedure to power down the PLL:
1) In PLLCSR, write PLLEN = 0 (bypass mode).
2) Wait 4 cycles of the slowest of PLLOUT, CLKIN (if CLKMODE = 1), and
OSCIN (if CLKMODE = 0).
3) In PLLCSR, write PLLPWRDN = 1 to power down the PLL.

Registers
Phase-Locked Loop (PLL) Controller14 SPRU233A
3.3 Power Wake Up
PerformthefollowingproceduretowakeupthePLLfromitspower-downmode:
1) In PLLCSR, write PLLEN = 0 (bypass mode).
2) Wait 4 cycles of the slowest of PLLOUT, CLKIN (if CLKMODE = 1), and
OSCIN (if CLKMODE = 0).
3) In PLLCSR, write PLLPWRDN = 0 to wake up the PLL.
4) Follow the reset sequence described in section 3.1.
4 Registers
ThePLL controller registers configure the operation of the PLL controller.The
PLLcontrollerregisters arelistedinTable 1. Seethedevice-specificdatasheet
for the memory address of these registers.
Table 1. PLL Controller Registers
Acronym Register Name Section
PLLPID PLL controller peripheral identification register 4.1
PLLCSR PLL control/status register 4.2
PLLM PLL multiplier control register 4.3
PLLDIV0–3 PLL controller divider registers 4.4
OSCDIV1 Oscillator divider 1 register 4.5
Configuration / Registers

Registers
15Phase-Locked Loop (PLL) ControllerSPRU233A
4.1 PLL Controller Peripheral Identification Register (PLLPID)
ThePLLcontrollerperipheralidentificationregister(PLLPID)containsidentifi-
cation code for thePLL controller. PLLPID is shown in Figure 3 and described
in Table 2.
Figure 3. PLL Controller Peripheral Identification Register (PLLPID)
31 24 23 16
Reserved TYPE
R-0 R-0000 0001
15 8 7 0
CLASS REV
R-0000 1000 R-x†
Legend: R = Read only; -x = value after reset
†See the device-specific datasheet for the default value of this field.
Table 2. PLL Controller Peripheral Identification Register (PLLPID) Field Descriptions
Bit field†symval†Value Description
31–24 Reserved –0These reserved bit locations are always read as 0. A value written
to this field has no effect.
23–16 TYPE OF(value)Identifies type of peripheral.
10h PLL controller
15–8CLASS OF(value)Identifies class of peripheral.
1 Serial port
7–0REV OF(value)Identifies revision of peripheral.
xSee the device-specific datasheet for the value.
†For CSL implementation, use the notation PLL_PID_field_symval

Registers
Phase-Locked Loop (PLL) Controller16 SPRU233A
4.2 PLL Control/Status Register (PLLCSR)
The PLL control/status register (PLLCSR) is shown in Figure 4 and described
in Table 3.
Figure 4. PLL Control/Status Register (PLLCSR)
31 16
Reserved
R-0
15 7 6 5 4 3 2 1 0
Reserved STABLE Reserved PLLRST —PLLPWRDN PLLEN
R-0 R-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
Legend: R = Read only; R/W = Read/write; -n= value after reset
Table 3. PLL Control/Status Register (PLLCSR) Field Descriptions
Bit field†symval†Value Description
31–7 Reserved –0Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
6 STABLE OF(value)Oscillator input stable bit indicates if the OSCIN/CLKIN input
has stabilized. The STABLE bit is set to 1 after the reset
controller counts 4096 input clock cycles after the RESET
signal is asserted high.
0OSCIN/CLKIN input is not yet stable. Oscillator counter is not
finished counting.
1OSCIN/CLKIN input is stable.
5–4 Reserved –0Reserved. The reserved bit location is always read as 0.
Always write a 0 to this location.
3 PLLRST PLL reset bit.
0 0 PLL reset is released.
1 1 PLL reset is asserted.
2 Reserved –0Reserved. The reserved bit location is always read as 0.
Always write a 0 to this location.
†For CSL implementation, use the notation PLL_PLLCSR_field_symval

Registers
17Phase-Locked Loop (PLL) ControllerSPRU233A
Table 3. PLL Control/Status Register (PLLCSR) Field Descriptions (Continued)
DescriptionValuesymval† field† Bit
1 PLLPWRDN PLL power-down mode select bit.
NO 0 PLL is operational.
YES 1 PLL is placed in power-down state.
0 PLLEN PLL enable bit.
BYPASS 0 Bypass mode. Divider D0 and PLL are bypassed.
SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from
input reference clock.
ENABLE 1 PLL mode. PLL output path is enabled. Divider D0 and PLL are
not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided
down from PLL output.
†For CSL implementation, use the notation PLL_PLLCSR_field_symval

Registers
Phase-Locked Loop (PLL) Controller18 SPRU233A
4.3 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 5 and described
in Table 4. The PLLM defines the input reference clock frequency multiplier in
conjunction with the PLL divider ratio bits (RATIO) in the PLL controller divid-
er 0 register (PLLDIV0).
Figure 5. PLL Multiplier Control Register (PLLM)
31 16
Reserved
R-0
15 5 4 0
Reserved PLLM
R-0 R/W-0 0111
Legend: R = Read only; R/W = Read/write; -n= value after reset
Table 4. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit Field symval†Value Description
31–5 Reserved –0Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
4–0PLLM OF(value) 0–1Fh PLL multiplier bits. Defines the frequency multiplier of the input
reference clock in conjunction with the PLL divider ratio bits
(RATIO) in PLLDIV0. See the device-specific datasheet for the
PLL multiplier rates supported on your device.
†For CSL implementation, use the notation PLL_PLLM_PLLM_symval

Registers
19Phase-Locked Loop (PLL) ControllerSPRU233A
4.4 PLL Controller Divider Registers (PLLDIV0–3)
The PLL controllerdividerregister(PLLDIV)is shown inFigure6 and described
in Table 5.
Figure 6. PLL Controller Divider Register (PLLDIV)
31 16
Reserved
R-0
15 14 5 4 0
DnEN Reserved RATIO
R/W-1 R-0 R/W-0†
Legend: R = Read only; R/W = Read/write; -n= value after reset
†For PLLDIV0 and PLLDIV1; for PLLDIV2 and PLLDIV3, reset value is 0 0001.
Table 5. PLL Controller Divider Register (PLLDIV) Field Descriptions
Bit field†symval†Value Description
31–16 Reserved –0Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
15 DnEN Divider Dnenable bit.
DISABLE 0 Divider nis disabled. No clock output.
ENABLE 1 Divider nis enabled.
14–5 Reserved –0Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
4–0RATIO OF(value)PLL divider ratio bits. For PLLDIV0, defines the input reference
clock frequency multiplier in conjunction with the PLL multiplier
bits (PLLM) in PLLM. For PLLDIV1–3, defines the PLL output
clock frequency divider ratio.
0÷1. Divide frequency by 1.
1h ÷2. Divide frequency by 2.
2h–1Fh ÷3 to ÷32. Divide frequency by 3 to divide frequency by 32.
†For CSL implementation, use the notation PLL_PLLDIVn_field_symval

Registers
Phase-Locked Loop (PLL) Controller20 SPRU233A
4.5 Oscillator Divider 1 Register (OSCDIV1)
The oscillator divider 1 register (OSCDIV1) is shown in Figure 7 and described
in Table 6.
Figure 7. Oscillator Divider 1 Register (OSCDIV1)
31 16
Reserved
R-0
15 14 5 4 0
OD1EN Reserved RATIO
R/W-1 R-0 R/W-0 0111
Legend: R = Read only; R/W = Read/write; -n= value after reset
Table 6. Oscillator Divider 1 Register (OSCDIV1) Field Descriptions
Bit field†symval†Value Description
31–16 Reserved –0Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
15 OD1EN Oscillator divider 1 enable bit.
DISABLE 0 Oscillator divider 1 is disabled. No clock output.
ENABLE 1 Oscillator divider 1 is enabled.
14–5 Reserved –0Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
4–0RATIO OF(value)Oscillator divider 1 ratio bits. Defines the input reference clock
frequency divider ratio for output clock CLKOUT3.
0÷1. Divide input reference clock frequency by 1.
1h ÷2. Divide input reference clock frequency by 2.
2h–1Fh ÷3 to ÷32. Divide input reference clock frequency by 3 to divide
input reference clock frequency by 32.
†For CSL implementation, use the notation PLL_OSCDIV1_field_symval