Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
Software-Programmable
Phase-Locked Loop (PLL) Controller
Reference Guide
Literature Number: SPRU233A
April 2003

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3Title of DocSPRU233A
Preface
Read This First
About This Manual
Thisdocumentdescribestheoperation ofthe software-programmablephase-
locked loop (PLL) controller in the digital signal processors (DSPs) of the
TMS320C6000DSP family. This type of controller is used on the following
devices:
-TMS320C6711C
-TMS320C6712C
-TMS320C6713
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.

Trademarks
4Phase-Locked Loop (PLL) Controller SPRU233A
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301)introduces the CodeComposerStudiointegrateddevelop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
numberSPRU401)describes a set ofapplicationprogramminginterfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

5Phase-Locked Loop (PLL) ControllerSPRU233A
Contents
1 Overview 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Multiplier and Dividers 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reset Controller 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Configuration 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Initialization 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 PLL Mode (PLLEN = 1) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Bypass Mode (PLLEN = 0) 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Power Down 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Power Wake Up 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Registers 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PLL Controller Peripheral Identification Register (PLLPID) 15. . . . . . . . . . . . . . . . . . . . . . . .
4.2 PLL Control/Status Register (PLLCSR) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 PLL Multiplier Control Register (PLLM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 PLL Controller Divider Registers (PLLDIV0–3) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Oscillator Divider 1 Register (OSCDIV1) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6Phase-Locked Loop (PLL) Controller SPRU233A
Figures
1 PLL Controller Block Diagram 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Reset Controller Lengthening the Internal Reset Signal 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 PLL Controller Peripheral Identification Register (PLLPID) 15. . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PLL Control/Status Register (PLLCSR) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 PLL Multiplier Control Register (PLLM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 PLL Controller Divider Register (PLLDIV) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Oscillator Divider 1 Register (OSCDIV1) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1 PLL Controller Registers 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 PLL Controller Peripheral Identification Register (PLLPID) Field Descriptions 15. . . . . . . . . .
3 PLL Control/Status Register (PLLCSR) Field Descriptions 16. . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PLL Multiplier Control Register (PLLM) Field Descriptions 18. . . . . . . . . . . . . . . . . . . . . . . . . . .
5 PLL Controller Divider Register (PLLDIV) Field Descriptions 19. . . . . . . . . . . . . . . . . . . . . . . . .
6 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions 20. . . . . . . . . . . . . . . . . . . . . . . . . .

7Phase-Locked Loop (PLL) ControllerSPRU233A
Phase-Locked Loop (PLL) Controller
Thisdocumentdescribestheoperation ofthe software-programmablephase-
locked loop (PLL) controller in the digital signal processors (DSPs) of the
TMS320C6000DSP family. This type of controller is used on the following
devices:
-TMS320C6711C
-TMS320C6712C
-TMS320C6713
1 Overview
The PLL controller (Figure 1) features software-configurable PLL multiplier
controller, dividers (OSCDIV1, D0, D1, D2, and D3), and reset controller. The
PLL controller accepts an input clock, as determined by the logic state on the
CLKMODE0 pin, from the CLKIN pin or from the on-chip oscillator output
signal OSCIN. The PLL controller offers flexibility and convenience by way of
software-configurable multiplier and dividers to modify the input signal inter-
nally.TheresultingclockoutputsarepassedtotheDSPcore,peripherals,and
other modules inside the C6000DSP.
-The input reference clocks to the PLL controller:
JCLKIN: input signal from external oscillator (3.3V), CLKMODE0 = 1
JOSCIN: output signal from on-chip oscillator (1.2V), CLKMODE0 = 0
-The resulting output clocks from the PLL controller:
JAUXCLK: internal clock output signal directly from CLKIN or OSCIN.
JCLKOUT3: output of divider OSCDIV1.
JSYSCLK1: internal clock output of divider D1.
JSYSCLK2: internal clock output of divider D2.
JSYSCLK3: internal clock output of divider D3.
Refertoyourdevice-specificdatasheetonhowtheseinputsandoutputsofthe
PLL controller are used.

Overview
Phase-Locked Loop (PLL) Controller8SPRU233A
Figure 1. PLL Controller Block Diagram
1
0
CLKIN
OSCIN
CLKMODE0
Divider D0
÷1, ÷2,...÷32 PLL†
÷1, ÷2,...÷32
OSCDIV1
÷1, ÷2,...÷32
Divider D1 Divider D2
÷1, ÷2,...÷32 Divider D3
÷1, ÷2,...÷32
PLLEN
controller
Reset
PLL controller
AUXCLK SYSCLK1 SYSCLK2 SYSCLK3
CLKOUT3
10
PLLOUT
PLLM
×1, ×2,...×32
†See the device-specific datasheet for more details about the PLL.

Functional Description
9Phase-Locked Loop (PLL) ControllerSPRU233A
2 Functional Description
The following sections describe the multiplier, dividers, and reset controller in
the PLL controller.
2.1 Multiplier and Dividers
The PLL controller is capable of programming the PLL through the PLL multiplier
controlregister(PLLM)froma×1to×32multiplierrate(seethedevice-specific
datasheet for the PLL multiplier rates supported on your device). The clock
dividers (OSCDIV1, D0, D1, D2, and D3) are programmable from ÷1 to ÷32
divider ratio and may be disabled. The oscillator divider enable bit (OD1EN)
in the oscillator divider 1 register (OSCDIV1) determines the oscillator divider
output mode. When OD1EN = 0, theoscillator dividerisdisabled andno clock
isoutput; whenOD1EN =1,the oscillatordivider isenabledand aclockisout-
put. The divider enable bit (DnEN) in the PLL controller divider registers
(PLLDIVn) determines the divider output mode. When DnEN = 0, the divider
is disabled and no clock is output; when DnEN = 1, the divider is enabledand
a clock is output.
The input reference clock (either CLKIN or OSCIN) is directly output as the
auxiliaryclock(AUXCLK)forusebysomeperipherals.Forexample,themulti-
channelaudio serial port(McASP)uses AUXCLK togenerateaudio clocks.In
addition to AUXCLK, the input reference clock is directly input to the oscillator
divider (OSCDIV1). If OSCDIV1 is enabled, OD1EN = 1, the input reference
clock is divided down by the value in the oscillator divider ratio bits (RATIO) in
OSCDIV1. The output from OSCDIV1 is the output clock CLKOUT3.
The divider D0 and the PLL may also be bypassed. The PLL enable bit
(PLLEN) in the PLL control/status register (PLLCSR) determines the PLL
controller mode. When PLLEN = 1, PLL mode, D0 and PLL are used; when
PLLEN = 0, bypass mode, D0 and PLL are bypassed and the input reference
clock is directly input to dividers D1, D2, and D3.
Whenin PLL mode (PLLEN =1),the input reference clockissuppliedto divid-
erD0. If D0 is enabled, D0EN =1, theinput reference clock is divided down by
the value in the PLL divider ratio bits (RATIO) in PLLDIV0. The output from
divider D0 is input to the PLL. The PLL multiplies the clock by the value in the
PLL multiplier bits (PLLM) in the PLL multiplier control register (PLLM). The
output from the PLL (PLLOUT) is input to dividers D1, D2, and D3.
When enabled (DnEN = 1), the dividers D1, D2, and D3 divide down by the
value in RATIO in PLLDIVnthe output clock of the PLL. The output clocks of
dividers D1, D2, and D3 have 50% duty cycle and are SYSCLK1, SYSCLK2,
and SYSCLK3, respectively.

Functional Description
Phase-Locked Loop (PLL) Controller10 SPRU233A
2.2 Reset Controller
At power up, the device RESET signal may not be asserted long enough to
waitfortheon-chiporoff-chiposcillatortostabilize.Thismeanstheinputrefer-
enceclock(eitherCLKINorOSCIN)maybeabadclockwhenadeviceRESET
signal is deasserted high. After RESET is deasserted, the reset controller
lengthenstheasynchronousinternalresetsignaltoensurethattheinputclock
source is stable.
The reset controller resides within the PLL controller and the main function is
to internally lengthen the reset signal from the RESET input pin until the input
clock source is stable (after 512 CLKIN cycles or 4096 OSCIN cycles). This
istoensurethattherestofthedevicewillseetheinternalresetdeassertedonly
aftertheinputclockisstabilized.Figure2showsthelengtheningoftheinternal
reset signal.
ThePLLcontrollermultiplieranddividersarebypassedwhentheinternalreset
signalislow.ThefrequencyofallclockoutputsofthePLLcontroller(AUXCLK,
SYSCLK1, SYSCLK2, SYSCLK3, and CLKOUT3) are fixed to the input
reference clock (CLKIN or OSCIN) divided by 8. After 512 CLKIN cycles or
4096 OSCINcycles,theresetcontrollerbringsthedeviceoutofresetandsets
the oscillator input stable bit (STABLE) in the PLL control/status register
(PLLCSR). The dividers are used after this point and are set to their default
divide ratio.
Values are latched into the registers at the rising edge of RESET.