Texas Instruments TMS320x2833 series User manual

TMS320 x2833x, 2823x System Control andInterrupts
Reference Guide
Literature Number: SPRUFB0CSeptember 2007 – Revised May 2009

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Contents
Preface .............................................................................................................................. 11
1 Flash and OTP Memory Blocks .................................................................................. 151.1 Flash and OTP Memory ................................................................................................... 161.1.1 Flash Memory ...................................................................................................... 161.1.2 OTP Memory ....................................................................................................... 161.2 Flash and OTP Power Modes ............................................................................................ 161.2.1 Flash and OTP Performance ................................................................................... 181.2.2 Flash Pipeline Mode .............................................................................................. 181.2.3 Reserved Locations Within Flash and OTP ................................................................... 191.2.4 Procedure to Change the Flash Configuration Registers .................................................... 201.3 Flash and OTP Registers ................................................................................................. 21
2 Code Security Module (CSM) ..................................................................................... 272.1 Functional Description ..................................................................................................... 282.2 CSM Impact on Other On-Chip Resources ............................................................................. 302.3 Incorporating Code Security in User Applications ..................................................................... 312.3.1 Environments That Require Security Unlocking .............................................................. 322.3.2 Password Match Flow ........................................................................................... 332.3.3 Unsecuring Considerations for Devices With/Without Code Security ...................................... 342.4 Do's and Don'ts to Protect Security Logic ............................................................................... 362.4.1 Do's ................................................................................................................. 362.4.2 Don'ts .............................................................................................................. 362.5 CSM Features - Summary ................................................................................................ 36
3 Clocking .................................................................................................................. 373.1 Clocking and System Control ............................................................................................. 383.2 OSC and PLL Block ........................................................................................................ 453.2.1 PLL-Based Clock Module ........................................................................................ 453.2.2 Main Oscillator Fail Detection.................................................................................... 463.2.3 XCLKOUT Generation ............................................................................................ 483.2.4 PLL Control (PLLCR) Register .................................................................................. 493.2.5 PLL Control, Status and XCLKOUT Register Descriptions .................................................. 513.2.6 External Reference Oscillator Clock Option ................................................................... 523.3 Low-Power Modes Block .................................................................................................. 533.4 Watchdog Block ............................................................................................................ 553.4.1 Servicing The Watchdog Timer .................................................................................. 563.4.2 Watchdog Reset or Watchdog Interrupt Mode ................................................................ 563.4.3 Watchdog Operation in Low Power Modes .................................................................... 573.4.4 Emulation Considerations ........................................................................................ 573.4.5 Watchdog Registers .............................................................................................. 583.5 32-Bit CPU Timers 0/1/2 .................................................................................................. 60
4 General-Purpose Input/Output (GPIO) ......................................................................... 65
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4.1 GPIO Module Overview ................................................................................................... 664.2 Configuration Overview .................................................................................................... 714.3 Digital General Purpose I/O Control ..................................................................................... 724.4 Input Qualification .......................................................................................................... 744.4.1 No Synchronization (asynchronous input) ..................................................................... 744.4.2 Synchronization to SYSCLKOUT Only ......................................................................... 744.4.3 Qualification Using a Sampling Window ....................................................................... 744.5 GPIO and Peripheral Multiplexing (MUX) ............................................................................... 784.6 Register Bit Definitions .................................................................................................... 83
5 Peripheral Frames ................................................................................................... 1095.1 Peripheral Frame Registers ............................................................................................. 1105.2 EALLOW-Protected Registers .......................................................................................... 1125.3 Device Emulation Registers ............................................................................................. 1165.4 Write-Followed-by-Read Protection .................................................................................... 118
6 Peripheral Interrupt Expansion (PIE) ......................................................................... 1216.1 Overview of the PIE Controller .......................................................................................... 1226.1.1 Interrupt Operation Sequence .................................................................................. 1226.2 Vector Table Mapping .................................................................................................... 1256.3 Interrupt Sources.......................................................................................................... 1276.3.1 Procedure for Handling Multiplexed Interrupts ............................................................... 1296.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts ............................... 1306.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU ................................. 1316.3.4 The PIE Vector Table ........................................................................................... 1326.4 PIE Configuration Registers ............................................................................................. 1396.5 PIE Interrupt Registers ................................................................................................... 1406.5.1 PIE Interrupt Flag Registers .................................................................................... 1416.5.2 PIE Interrupt Enable Registers ................................................................................. 1416.5.3 CPU Interrupt Flag Register (IFR) ............................................................................. 1426.5.4 Interrupt Enable Register (IER) and Debug Interrupt Enable Register (DBGIER) ...................... 1446.6 External Interrupt Control Registers ................................................................................... 148
A Revision History ..................................................................................................... 151
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List of Figures
1-1 Flash Power Mode State Diagram ....................................................................................... 171-2 Flash Pipeline ............................................................................................................... 191-3 Flash Configuration Access Flow Diagram ............................................................................. 201-4 Flash Options Register (FOPT) .......................................................................................... 221-5 Flash Power Register (FPWR) ........................................................................................... 221-6 Flash Status Register (FSTATUS) ....................................................................................... 231-7 Flash Standby Wait Register (FSTDBYWAIT) ......................................................................... 241-8 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) .................................................. 241-9 Flash Wait-State Register (FBANKWAIT) .............................................................................. 251-10 OTP Wait-State Register (FOTPWAIT) ................................................................................. 262-1 CSM Status and Control Register (CSMSCR) ......................................................................... 322-2 Password Match Flow (PMF) ............................................................................................ 333-1 Clock and Reset Domains ................................................................................................ 383-2 Peripheral Clock Control 0 Register (PCLKCR0) ...................................................................... 393-3 Peripheral Clock Control 1 Register (PCLKCR1) ..................................................................... 403-4 Peripheral Clock Control 3 Register (PCLKCR3) ...................................................................... 433-5 High-Speed Peripheral Clock Prescaler (HISPCP) Register ......................................................... 443-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) ......................................................... 443-7 OSC and PLL Block ........................................................................................................ 453-8 Oscillator Fail-Detection Logic Diagram ................................................................................. 463-9 XCLKOUT Generation ..................................................................................................... 483-10 PLLCR Change Procedure Flow Chart .................................................................................. 503-11 PLLCR Register Layout ................................................................................................... 513-12 PLL Status Register (PLLSTS) ........................................................................................... 513-13 Low Power Mode Control 0 Register (LPMCR0) ....................................................................... 543-14 Watchdog Module .......................................................................................................... 553-15 System Control and Status Register (SCSR) .......................................................................... 583-16 Watchdog Counter Register (WDCNTR) ................................................................................ 593-17 Watchdog Reset Key Register (WDKEY) ............................................................................... 593-18 Watchdog Control Register (WDCR) .................................................................................... 593-19 CPU-Timers ................................................................................................................. 603-20 CPU-Timer Interrupts Signals and Output Signal ...................................................................... 613-21 TIMERxTIM Register (x = 0, 1, 2) ........................................................................................ 623-22 TIMERxTIMH Register (x = 0, 1, 2) ...................................................................................... 623-23 TIMERxPRD Register (x = 0, 1, 2) ....................................................................................... 623-24 TIMERxPRDH Register (x = 0, 1, 2) ..................................................................................... 623-25 TIMERxTCR Register (x = 0, 1, 2) ....................................................................................... 633-26 TIMERxTPR Register (x = 0, 1, 2) ....................................................................................... 643-27 TIMERxTPRH Register (x = 0, 1, 2) .................................................................................... 644-1 GPIO0 to GPIO27 Multiplexing Diagram ................................................................................ 664-2 GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 674-3 GPIO32, GPIO33 Multiplexing Diagram ................................................................................. 684-4 GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 694-5 GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification) ................................ 704-6 Input Qualification Using a Sampling Window .......................................................................... 744-7 Input Qualifier Clock Cycles .............................................................................................. 774-8 GPIO Port A MUX 1 (GPAMUX1) Register ............................................................................. 834-9 GPIO Port A MUX 2 (GPAMUX2) Register ............................................................................. 854-10 GPIO Port B MUX 1 (GPBMUX1) Register ............................................................................. 874-11 GPIO Port B MUX 2 (GPBMUX2) Register ............................................................................. 894-12 GPIO Port C MUX 1 (GPCMUX1) Register ............................................................................. 914-13 GPIO Port C MUX 2 (GPCMUX2) Register ............................................................................. 92
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4-14 GPIO Port A Qualification Control (GPACTRL) Register ............................................................ 944-15 GPIO Port B Qualification Control (GPBCTRL) Register ............................................................ 954-16 GPIO Port A Qualification Select 1 (GPAQSEL1) Register........................................................... 964-17 GPIO Port A Qualification Select 2 (GPAQSEL2) Register........................................................... 964-18 GPIO Port B Qualification Select 1 (GPBQSEL1) Register........................................................... 974-19 GPIO Port B Qualification Select 2 (GPBQSEL2) Register........................................................... 974-20 GPIO Port A Direction (GPADIR) Register ............................................................................. 984-21 GPIO Port B Direction (GPBDIR) Register ............................................................................. 984-22 GPIO Port C Direction (GPCDIR) Register ............................................................................ 994-23 GPIO Port A Pullup Disable (GPAPUD) Registers .................................................................. 1004-24 GPIO Port B Pullup Disable (GPBPUD) Registers .................................................................. 1004-25 GPIO Port C Pullup Disable (GPCPUD) Registers .................................................................. 1014-26 GPIO Port A Data (GPADAT) Register ............................................................................... 1014-27 GPIO Port B Data (GPBDAT) Register ............................................................................... 1024-28 GPIO Port C Data (GPCDAT) Register ............................................................................... 1034-29 GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers ....................... 1044-30 GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers ....................... 1054-31 GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers ...................... 1064-32 GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers ............................. 1074-33 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register ................................................ 1085-1 Device Configuration (DEVICECNF) Register ........................................................................ 1165-2 Part ID Register ........................................................................................................... 1175-3 CLASSID Register ........................................................................................................ 1175-4 REVID Register ........................................................................................................... 1176-1 Overview: Multiplexing of Interrupts Using the PIE Block ........................................................... 1226-2 Typical PIE/CPU Interrupt Response - INTx.y ........................................................................ 1246-3 Reset Flow Diagram ...................................................................................................... 1266-4 PIE Interrupt Sources and External Interrupts XINT1/XINT2 ....................................................... 1276-5 PIE Interrupt Sources and External Interrupts (XINT3 – XINT7) ................................................... 1286-6 Multiplexed Interrupt Request Flow Diagram ......................................................................... 1316-7 PIECTRL Register (Address CE0) ..................................................................................... 1406-8 PIE Interrupt Acknowledge Register (PIEACK) Register (Address CE1) ......................................... 1406-9 PIEIFRx Register (x = 1 to 12) .......................................................................................... 1416-10 PIEIERx Register (x = 1 to 12) .......................................................................................... 1416-11 Interrupt Flag Register (IFR) — CPU Register ....................................................................... 1436-12 Interrupt Enable Register (IER) — CPU Register .................................................................... 1456-13 Debug Interrupt Enable Register (DBGIER) — CPU Register ..................................................... 1466-14 External Interrupt nControl Register (XINT nCR) .................................................................... 1486-15 External NMI Interrupt Control Register (XNMICR) — Address 7077h ............................................ 1486-16 External Interrupt 1 Counter (XINT1CTR) (Address 7078h) ........................................................ 1496-17 External Interrupt 2 Counter (XINT2CTR) (Address 7079h) ........................................................ 1496-18 External NMI Interrupt Counter (XNMICTR) (Address 707Fh) ..................................................... 150
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List of Tables
1-1 Flash/OTP Configuration Registers ...................................................................................... 211-2 Flash Options Register (FOPT) Field Descriptions .................................................................... 221-3 Flash Power Register (FPWR) Field Descriptions ..................................................................... 221-4 Flash Status Register (FSTATUS) Field Descriptions ................................................................. 231-5 Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ................................................... 241-6 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions ............................. 241-7 Flash Wait-State Register (FBANKWAIT) Field Descriptions ........................................................ 251-8 OTP Wait-State Register (FOTPWAIT) Field Descriptions ........................................................... 262-1 Security Levels ............................................................................................................. 282-2 Resources Affected by the CSM ......................................................................................... 302-3 Resources Not Affected by the CSM .................................................................................... 302-4 Code Security Module (CSM) Registers ................................................................................ 312-5 CSM Status and Control Register (CSMSCR) Field Descriptions ................................................... 323-1 PLL, Clocking, Watchdog, and Low-Power Mode Registers ........................................................ 393-2 Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions ................................................ 393-3 Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions ............................................... 413-4 Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions ................................................ 433-5 High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions .............................................. 443-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions ................................... 443-7 Possible PLL Configuration Modes ...................................................................................... 463-8 PLLCR Bit Descriptions ................................................................................................... 513-9 PLL Status Register (PLLSTS) Field Descriptions ..................................................................... 513-10 Low-Power Mode Summary .............................................................................................. 533-11 Low Power Modes ......................................................................................................... 533-12 Low Power Mode Control 0 Register (LPMCR0) Field Descriptions ................................................ 543-13 Example Watchdog Key Sequences ..................................................................................... 563-14 System Control and Status Register (SCSR) Field Descriptions .................................................... 583-15 Watchdog Counter Register (WDCNTR) Field Descriptions ......................................................... 593-16 Watchdog Reset Key Register (WDKEY) Field Descriptions ......................................................... 593-17 Watchdog Control Register (WDCR) Field Descriptions .............................................................. 593-18 CPU-Timers 0, 1, 2 Configuration and Control Registers ............................................................. 613-19 TIMERxTIM Register Field Descriptions ................................................................................ 623-20 TIMERxTIMH Register Field Descriptions .............................................................................. 623-21 TIMERxPRD Register Field Descriptions ............................................................................... 623-22 TIMERxPRDH Register Field Descriptions ............................................................................. 633-23 TIMERxTCR Register Field Descriptions ............................................................................... 633-24 TIMERxTPR Register Field Descriptions ............................................................................... 643-25 TIMERxTPRH Register Field Descriptions.............................................................................. 644-1 GPIO Control Registers ................................................................................................... 714-2 GPIO Interrupt and Low Power Mode Select Registers ............................................................... 714-3 GPIO Data Registers ...................................................................................................... 734-4 Sampling Period ............................................................................................................ 754-5 Sampling Frequency ....................................................................................................... 754-6 Case 1: Three-Sample Sampling Window Width ...................................................................... 764-7 Case 2: Six-Sample Sampling Window Width .......................................................................... 764-8 Default State of Peripheral Input ......................................................................................... 794-9 GPIOA MUX ................................................................................................................ 804-10 GPIOB MUX ................................................................................................................ 814-11 GPIOC MUX ................................................................................................................ 82
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4-12 GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions .............................................. 834-13 GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ....................................................... 854-14 GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions ....................................................... 874-15 GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions ....................................................... 894-16 GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions ...................................................... 914-17 GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions ...................................................... 924-18 GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions ....................................... 944-19 GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions ....................................... 954-20 GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions .................................... 964-21 GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions .................................... 964-22 GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions .................................... 974-23 GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions .................................... 974-24 GPIO Port A Direction (GPADIR) Register Field Descriptions ....................................................... 984-25 GPIO Port B Direction (GPBDIR) Register Field Descriptions ....................................................... 994-26 GPIO Port C Direction (GPCDIR) Register Field Descriptions ....................................................... 994-27 GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions .................................... 1004-28 GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions .................................... 1004-29 GPIO Port C Internal Pullup Disable (GPCPUD) Register Field Descriptions .................................... 1014-30 GPIO Port A Data (GPADAT) Register Field Descriptions .......................................................... 1024-31 GPIO Port B Data (GPBDAT) Register Field Descriptions .......................................................... 1024-32 GPIO Port C Data (GPCDAT) Register Field Descriptions ......................................................... 1034-33 GPIO Port A Set (GPASET) Register Field Descriptions ............................................................ 1044-34 GPIO Port A Clear (GPACLEAR) Register Field Descriptions ..................................................... 1044-35 GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions ................................................. 1044-36 GPIO Port B Set (GPBSET) Register Field Descriptions ............................................................ 1054-37 GPIO Port B Clear (GPBCLEAR) Register Field Descriptions ..................................................... 1054-38 GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions ................................................. 1054-39 GPIO Port C Set (GPCSET) Register Field Descriptions ........................................................... 1064-40 GPIO Port C Clear (GPCCLEAR) Register Field Descriptions ..................................................... 1064-41 GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions ................................................. 1064-42 GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions ..................................... 1074-43 XINT1/XINT2 Interrupt Select and Configuration Registers ......................................................... 1074-44 GPIO XINT3 - XINT7 Interrupt Select (GPIOXINTnSEL) Register Field Descriptions .......................... 1074-45 XINT3 - XINT7 Interrupt Select and Configuration Registers ....................................................... 1074-46 GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions ...................................... 1084-47 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions .......................... 1085-1 Peripheral Frame 0 Registers .......................................................................................... 1105-2 Peripheral Frame 1 Registers ........................................................................................... 1105-3 Peripheral Frame 2 Registers ........................................................................................... 1115-4 Peripheral Frame 3 Registers ........................................................................................... 1115-5 Access to EALLOW-Protected Registers .............................................................................. 1125-6 EALLOW-Protected Device Emulation Registers..................................................................... 1125-7 EALLOW-Protected Flash/OTP Configuration Registers ............................................................ 1125-8 EALLOW-Protected Code Security Module (CSM) Registers ...................................................... 1135-9 EALLOW-Protected PIE Vector Table ................................................................................. 1135-10 EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................... 1145-11 EALLOW-Protected GPIO MUX Registers ........................................................................... 1145-12 EALLOW-Protected eCAN Registers .................................................................................. 1155-13 EALLOW-Protected ePWM1 - ePWM 6 Registers .................................................................... 1155-14 XINTF Registers ......................................................................................................... 1155-15 Device Emulation Registers ............................................................................................. 116
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5-16 DEVICECNF Register Field Descriptions.............................................................................. 1165-17 PARTID Register Field Descriptions ................................................................................... 1175-18 CLASSID Register Description .......................................................................................... 1175-19 REVID Register Field Descriptions ..................................................................................... 1185-20 PROTSTART and PROTRANGE Registers........................................................................... 1185-21 PROTSTART Valid Values ............................................................................................. 1185-22 PROTRANGE Valid Values ............................................................................................. 1196-1 Enabling Interrupt ......................................................................................................... 1246-2 Interrupt Vector Table Mapping ........................................................................................ 1256-3 Vector Table Mapping After Reset Operation ........................................................................ 1256-4 PIE MUXed Peripheral Interrupt Vector Table ........................................................................ 1336-5 PIE Vector Table .......................................................................................................... 1346-6 PIE Configuration and Control Registers .............................................................................. 1396-7 PIECTRL Register Address Field Descriptions ....................................................................... 1406-8 PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions ................................................. 1406-9 PIEIFRx Register Field Descriptions ................................................................................... 1416-10 PIEIERx Register (x = 1 to 12) Field Descriptions ................................................................... 1426-11 Interrupt Flag Register (IFR) — CPU Register Field Descriptions ................................................. 1436-12 Interrupt Enable Register (IER) — CPU Register Field Descriptions .............................................. 1456-13 Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions ............................... 1466-14 External Interrupt nControl Register (XINT nCR) Field Descriptions .............................................. 1486-15 External NMI Interrupt Control Register (XNMICR) Field Descriptions ............................................ 1486-16 XNMICR Register Settings and Interrupt Sources ................................................................... 1496-17 External Interrupt 1 Counter (XINT1CTR) Field Descriptions ....................................................... 1496-18 External Interrupt 2 Counter (XINT2CTR) Field Descriptions ....................................................... 1506-19 External NMI Interrupt Counter (XNMICTR) Field Descriptions .................................................... 150A-1 Changes Made in This Revision ........................................................................................ 151
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