Texas Instruments bq24133EVM User manual

User's Guide
SLUU476–December 2010
bq24133EVM Stand-Alone Synchronous, Switch-Mode,
Battery-Charge Controller With Integrated N-MOSFETs
and Power Path Selector
This user's guide describes the features and operation of the bq24133EVM Evaluation Module (EVM). The
EVM assists users in evaluating the bq24133 synchronous battery charger. The EVM is also called the
HPA715A. The manual includes the bq24133EVM bill of materials, board layout, and schematic.
Contents
1 Introduction .................................................................................................................. 2
1.1 EVM Features ...................................................................................................... 2
1.2 General Description ................................................................................................ 2
1.3 I/O Description ...................................................................................................... 2
1.4 Control and Key Parameters Settings ........................................................................... 3
1.5 Recommended Operating Conditions ........................................................................... 3
2 Test Summary ............................................................................................................... 5
2.1 Definitions ........................................................................................................... 5
2.2 Safety ................................................................................................................ 5
2.3 Quality ............................................................................................................... 5
2.4 Safety Apparel ...................................................................................................... 5
2.5 Equipment ........................................................................................................... 6
2.6 Equipment Setup ................................................................................................... 6
2.7 Procedure ........................................................................................................... 7
3 PCB Layout Guideline ...................................................................................................... 9
4 Bill of Materials, Board Layout, and Schematic ....................................................................... 10
4.1 Bill of Materials .................................................................................................... 10
4.2 Board Layout ...................................................................................................... 12
4.3 Schematic ......................................................................................................... 18
List of Figures
1 Original Test Setup for HPA715A (bq24133EVM)...................................................................... 6
2 Top Assembly.............................................................................................................. 12
3 Top Layer................................................................................................................... 13
4 Second Layer .............................................................................................................. 14
5 Third Layer ................................................................................................................. 15
6 Bottom Layer............................................................................................................... 16
7 Bottom Assembly.......................................................................................................... 17
8 bq24133EVM Schematic ................................................................................................. 18
List of Tables
1 I/O Description............................................................................................................... 2
2 Control and Key Parameters Settings.................................................................................... 3
3 Recommended Operating Conditions.................................................................................... 3
4 Bill of Materials............................................................................................................. 10
1
SLUU476–December 2010 bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge
Controller With Integrated N-MOSFETs and Power Path Selector
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Introduction www.ti.com
1 Introduction
1.1 EVM Features
• Evaluation module for bq24133
• Stand-alone synchronous switch-mode, battery-charge controller
• Integrated N-MOSFETs and power path selector
• CELL pin setting up to 12.6-V battery voltage; 1, 2, or 3 cells with 4.2 V/cell
• Input operating range: 4.5 V–16 V
• LED indication for charge status
• Test points for key signals available for testing purposes; easy probe hook-up.
• Jumpers available; easy-to-change setting
1.2 General Description
The bq24133 is highly integrated stand-alone Li-ion and Li-polymer switch-mode battery charge controllers
with two integrated N-channel power MOSFETs and power path selector gate driver. It offers a
constant-frequency synchronous PWM controller with high accuracy regulation of input current, charge
current and voltage. It also provides battery detection, pre-conditioning, charge termination, and charge
status monitoring.
The bq24133 automatically enters a low-quiescent current sleep mode when the input voltage falls below
the battery voltage. The bq24133 charges one, two or three cells (selected by CELL pin), supporting up to
a 2.5-A charge current. The bq24133 is available in a 24-pin, 3.5 x 5.5 mm2, thin QFN package.
For details, see the bq24133 data sheet (SLUSAF7).
1.3 I/O Description
Table 1. I/O Description
Jack Description
J1–VIN Positive input
J1–PGND Negative input
J2–VSYS Connected to system
J2–VBAT Connected to charger output
J2–PGND Ground
J2–TS_EXT Temperature qualification voltage Input
2bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge SLUU476–December 2010
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1520 R
V
IISET
CHARGE
´
=
www.ti.com Introduction
1.4 Control and Key Parameters Settings
Table 2. Control and Key Parameters Settings
Jack Description Factory Setting
JP1 Select external TS input or internal valid TS setting Jumper ON 1-2 (external TS)
1-2 : External TS input
2-3 : Internal valid TS setting
JP2 The pullup power source supplies the LEDs when JP2 is ON. LED has no power Jumper ON (LED power available)
source when JP2 is OFF.
JP3 TTC setting Jumper OPEN (enable timer and
2-3 : Connect TTC to VREF to enable termination and disable timer termination)
1-2 : Connect TTC to GND to disable termination and disable timer
OPEN : Enable timer and termination
JP4 Charger enable/disable setting. ISET is pulled to GND and the charger is Jumper OPEN (disable charger)
disabled when JP4 OPEN; charger is enabled when JP4 is ON.
JP5 CELL selection Jumper ON 1-2 (1 CELL) -001
1-2 : CELL-GND, 1CELL Jumper ON 2-3 (3 CELL) -002
2-3 : CELL-VREF, 3CELL
OPEN: CELL- FLOAT, 2CELL
1.5 Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Symbol Description Min Typ Max Unit Notes
Supply voltage, VBUS Input voltage 4.5 8 V 001
Supply voltage, VBUS Input voltage 6 18 V 002
Battery voltage, VBAT Voltage applied at VBAT terminal of J2 2.1 4.2 V 001
Battery voltage, VBAT Voltage applied at VBAT terminal of J2 2.1 12.6 V 002
Supply current Maximum input current 0 5 A
Charge current, Ichrg Battery charge current 0 2 2.5 A
Operating junction temperature range, TJ0 125 °C
The bq2410 EVM board requires a regulated supply approximately 1 V minimum above the regulated
voltage of the battery pack to a maximum input voltage of 16 Vdc. The bq24133 uses the CELL pin to
select the number of cells with a fixed 4.2 V/cell. Connecting CELL to AGND gives a 1-cell configuration, a
floating CELL pin gives a 2-cell configuration, and connecting to VREF gives a 3-cell configuration. The
CELL pin adjusts the internal resistor voltage divider from the BAT pin to AGND pin for voltage feedback
and regulate to internal 2.1-V voltage reference.
CELL Pin Voltage Regulation
AGND 4.2V
Floating 8.4V
VREF 12.6V
For Note 001, the BAT voltage is set to 4.2 V and for Note 002, the BAT voltage is set to 12.6 V.
The ISET input sets the maximum charging current. Battery current is sensed by current sensing resistor
RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 40 mV
maximum. The equation for charge current is:
(1)
For bq24133, the precharge current is set as 1/10 of the fast-charge rate set by ISET voltage, according to
the formula
3
SLUU476–December 2010 bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge
Controller With Integrated N-MOSFETs and Power Path Selector
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15200 R
V
IISET
PRECHARGE
´
=
÷
ø
ö
ç
è
æ+´=
9
6
150
R
R
V.VACUV
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9
6
161
R
R
V.VACOV
220 R
V
IACSET
DPM
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=
Introduction www.ti.com
(2)
The default setting is 2 Adc for fast-charge current and 0.2 Adc for precharge current.
In the bq24133, once the voltage on OVPSET is above the 1.6-V ACOV threshold or below the 0.5-V
ACUV threshold, the charge is disabled, and the battery is switched to the system instead of the adapter.
(3)
For Note 001, ACUV = 2.51 V; for Note 002, ACUV = 5.87 V.
(4)
For Note 001, ACOV = 8.03 V; for Note 002, ACOV = 18.80 V.
Similar to setting battery regulation current, the adapter current is set by the voltage on ACSET pin using
the following equation:
(5)
The default setting on the EVM is 3 Adc for adapter current regulation.
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www.ti.com Test Summary
2 Test Summary
2.1 Definitions
This procedure details how to configure the HPA715A evaluation board. On the test procedure the
following naming conventions are followed.
VXXX : External voltage supply name (VIN, VBAT, VTS)
LOADW: External load name (LOADR, LOADI)
V(TPyyy): Voltage at internal test point TPyyy. For example, V(TP1) means the voltage at TP1.
V(Jxx): Voltage at jack terminal Jxx.
V(TP(XXX)): Voltage at test point XXX. For example, V(ACSET) means the voltage at the test point
which is marked as ACSET.
V(XXX, YYY): Voltage across point XXX and YYY.
I(JXX(YYY)): Current going out from the YYY terminal of jack XX.
Jxx(BBB): Terminal or pin BBB of jack xx
Jxx ON : Internal jumper Jxx terminals are shorted
Jxx OFF: Internal jumper Jxx terminals are open
Jxx (-YY-) ON: Internal jumper Jxx adjacent terminals marked as YY are shorted
Measure:→A,B Check specified parameters A, B. If measured values are not within specified limits, the
unit under test has failed.
Observe: →A,B Observe if A, B occur. If they do not occur, the unit under test has failed.
Assembly drawings have location for jumpers, test points, and individual components.
2.2 Safety
1. Safety Glasses are to be worn.
2. This test must be performed by qualified personnel who are trained in electronics theory and
understand the risks and hazards of the assembly to be tested.
3. ESD precautions must be followed while handling electronic assemblies and performing this test.
4. Precautions must be observed to avoid touching areas of the assembly that may get hot or present a
shock hazard during testing.
2.3 Quality
1. Test data can be made available on request from Texas Instruments.
2.4 Safety Apparel
1. Electrostatic smock
2. Electrostatic gloves or finger cots
3. Safety glasses
4. Ground ESD wrist strap.
5
SLUU476–December 2010 bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge
Controller With Integrated N-MOSFETs and Power Path Selector
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VIN
J1
PGND
VSYS
J2
PGND
VBAT
APPLICATION CIRCUIT
TP2
SW
U1
V
Iin
I
Power supply
#1
Iout
V
Isys
V
ILoad #1
Load #2
I
TS_EXT
/STAT
JP2
TEST POINTS
D1
JP3
JP4 CE
TTC
LED
SETTINGS
JP5JP1
LEDPWR
bq24133EVM
HPA715A
Test Summary www.ti.com
2.5 Equipment
2.5.1 Power Supplies
Power Supply #1 (PS#1): a power supply capable of supplying 30 V at 5 A is required.
2.5.2 Loads
LOAD#1 A 30-V (or greater), 5-A (or greater) electronic load that can operate at constant current and
constant voltage mode.
LOAD#2: An HP 6060B 3-V to 60-V/0-A to 60-A, 300-W system dc electronic load or equivalent.
2.5.3 Meters
Seven Fluke 75 multimeters (equivalent or better) or four equivalent voltage meters and three equivalent
current meters.
The current meters must be capable of measuring 5-A+ current.
2.6 Equipment Setup
1. Set the Power Supply #1 (PS#1) for 6-V ±200-mVdc (001), or 16-V ±0.200-mV (002),4.5-A ±0.1-A
current limit, and then turn off supply.
2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VIN, PGND).
3. Connect a voltage meter across J1 (VIN, PGND).
4. Connect Load#1 in series with a current meter to J2 (VBAT, PGND). Turn off Load#1.
5. Connect Load#2 in series with a current meter to J2 (VSYS, PGND). Turn off Load#2.
6. Connect a voltage meter across J2 (VBAT, PGND).
7. Connect a voltage meter across J2 (VSYS, PGND).
8. Check all jumper shunts. JP1: connect 2-3 (External TS); JP2: ON; JP3: OPEN; JP4: OPEN. JP5:
connect 1-2 for 001 and connect 2-3 for 002.
Figure 1. Original Test Setup for HPA715A (bq24133EVM)
6bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge SLUU476–December 2010
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www.ti.com Test Summary
2.7 Procedure
Disconnect the load and power supply. Use diode-function of multimeter to check the resistance between
J1-VIN and J2-VSYS. Pass only if both OPEN for bi-direction (positive J1-VIN and negative on J2-VSYS;
negative J1-VIN and positive on J2-VSYS).
2.7.1 Power Supply and VREF
Make sure that Section 2.6 steps are followed.
Disconnect LOAD#1#2. Turn on PS#1 (6 V for 001 and 16 V for 002).
Measure →V(J2(VSYS)) = 6 V ±500 mV (001)
V(J2(VSYS)) = 16 V ±500 mV (002)
Measure →V(J2(VBAT)) = 0.5 V ±500 mV
Measure →V(TP(VREF)) = 3.3 V ±200 mV
Measure →V(TP(REGN)) = 0.5 V ±500 mV
2.7.2 Charger Enable and Battery Detection
Connect 2-3 of JP1 (Internal TS); short JP4 (Charger Enable)
Measure →V(TP(VREF)) = 3.3 V ±200 mV
Measure →V(TP(REGN)) = 6 V ±200 mV
Observe →V(J2(VBAT)) = 4.2 V ±200 mV (001)
V(J2(VBAT)) = 12.6 V ±200 mV (002)
Observe →D1 (/STAT) BLINK
2.7.3 Charge Current/Voltage Regulation and Battery Temperature Qualification
Reconnect LOAD#2, and turn on. Use the constant voltage mode. Set the output voltage to 2.5 V for 001
and 8 V for 002.
Measure →I(J2(VBAT)) = 0.2 A ±100 mA
Observe →D1 (/STAT) ON
Increase the voltage of LOAD#2 to 3.5 V for 001 and 10.5 V for 002.
Measure →I(J2(VBAT)) = 2 A ±200 mA
Observe →D1 (/STAT) ON
Open 2-3 of JP1 (External TS)
Measure →I(J2(VBAT)) = 0 A ±100 mA
Observe →D1 (/STAT) BLINK
Connect 2-3 of JP1 (Internal TS)
Measure →I(J2(VBAT)) = 2 A ±200 mA
Observe →D1 (/STAT) ON
2.7.4 Charger Termination and Recharge
Increase the voltage of LOAD#2 slowly to approximately 4.2 V for Note 001 and 12.6 V for Note 002.
Observe →I(J2(VBAT)) decreases from 2 A while V(J2(VBAT)) becomes constant.
Observe →I(J2(VBAT)) drops to zero when LOAD#2 current is less than 0.2 A.
7
SLUU476–December 2010 bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge
Controller With Integrated N-MOSFETs and Power Path Selector
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Test Summary www.ti.com
Decrease the voltage of LOAD#2 slowly to approximately 3.5 V for Note 001 and 10.5 V for Note 002.
Measure →I(J2(VBAT)) = 2 A ±200 mA.
Observe →D1 (/STAT) ON.
2.7.5 OVP - Input Overvoltage Protection
Increase the voltage of PS#1 to 9 V for Note 001 or 20 V for Note 002.
Measure →I(J1(VIN)) = 0 A ±200 mA.
Observe →D1 (/STAT) BLINK.
2.7.6 DPM - Input Current Regulation
Connect the output of the Load#1 in series with a current meter (multimeter) to J2 (SYS, PGND). Ensure
that a voltage meter is connected across J2 (SYS, PGND). Resume other status as in Section 2.7.3.
Turn on the power of Load#1. Set the load current to 0.5 A. Increase the load current until I(J1(VIN)) = 3
A.
Observe →I(J2(VBAT)) decreases from 3 A to 0 A and I(J1(VIN)) keeps 3 A unchanged.
2.7.7 Test Complete
Turn off the power supply, and remove all connections from the unit under test (UUT).
8bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge SLUU476–December 2010
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www.ti.com PCB Layout Guideline
3 PCB Layout Guideline
1. It is critical that the exposed thermal pad on the backside of the bq24133 package be soldered to the
PCB ground. Ensure that sufficient thermal vias are right underneath the IC, connecting to the ground
plane on the other layers.
2. The control stage and the power stage must be routed separately. At each layer, the signal ground and
the power ground are connected only at the thermal pad.
3. Charge current sense resistor must be connected to SRP and SRN with a Kelvin contact. The area of
this loop must be minimized. The decoupling capacitors for these pins must be placed as close to the
IC as possible.
4. Input current sense resistor must be connected to ACP, ACN with a Kelvin contact. The area of this
loop must be minimized. The decoupling capacitors for these pins should be placed as close to the IC
as possible.
5. Decoupling capacitors for VREF, AVCC, and REGN must make the interconnections to the IC as short
as possible.
6. Decoupling capacitors for BAT must be placed close to the corresponding IC pins, and make the
interconnections to the IC as short as possible.
7. Decoupling capacitor(s) for the charger input must be placed close to SW and PGND.
8. Take the EVM layout for design reference.
9
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Bill of Materials, Board Layout, and Schematic www.ti.com
4 Bill of Materials, Board Layout, and Schematic
4.1 Bill of Materials
Table 4. Bill of Materials
Count
-001 -002 RefDes Value Description Size Part Number MFR
4 4 C1, C7, C14, 10 µF Capacitor, Ceramic, 25V, X7R, 10% 1206 STD STD
C15
0 0 C2 Open
1 1 C3 2.2 µF Capacitor, Ceramic, 25V, X7R, 10% 0805 STD STD
1 1 C4 330 pF Capacitor, Ceramic, 50V, X7R, 10% 0603 STD STD
2 2 C5, C18 0.1 µF Capacitor, Ceramic, 16V, X7R, 10% 0603 STD STD
1 1 C6, C13 0.047 µF Capacitor, Ceramic, 50V, X7R, 10% 0603 STD STD
3 3 C8, C16, C17 1.0 µF Capacitor, Ceramic, 25V, X7R, 10% 0805 STD STD
1 1 C9 4700 pF Capacitor, Ceramic, 25V, X7R, 10% 0603 STD STD
3 3 C10, C20, C24 0.1 µF Capacitor, Ceramic, 50V, X7R, 10% 0603 STD STD
0 0 C11, C12, C21, Open
C23
2 2 C22, C19 1.0 µF Capacitor, Ceramic, 16V, X7R, 20% 0805 STD STD
1 1 D1 LTST-C190GKT Diode, LED, Green, 2.1V, 20mA, 6mcd 0603 LTST-C190GKT Lite On
0 1 D2 BAT54C Diode, Dual Schottky, 200-mA, 30-V SOT23 BAT54C-V-G Vishay
1 1 J1 ED120/2DS Terminal Block, 2 pin, 15A, 5.1mm 0.40 x 0.35 inch ED120/2DS OST
1 1 J2 ED120/4DS Terminal Block, 4 pin, 15A, 5.1mm 0.80 x 0.35 inch ED120/4DS OST
3 3 JP1, JP3, JP5 PEC03SAAN Header, 3 pin, 100mil spacing 0.100 inch x 3 PEC03SAAN Sullins
2 2 JP2, JP4 PEC02SAAN Header, 2 pin, 100mil spacing 0.100 inch x 2 PEC02SAAN Sullins
1 1 L1 3.3 µH Inductor, SMT, 5A, 55milliohm 0.204 x 0.216 IHLP2020CZER3R3M01 Vishay
inch
1 1 Q1 BSS138W MOSFET, Nch, 30V, 0.5A, 700 milliohms SOT323 BSS138W-7-F Diodes Inc
2 2 Q2, Q3 CSD17313Q2 Trans, Nch, 30V, 5A, 26milliohm SON-6 CSD17313Q2 TI
1 1 Q4 CSD25302Q2 Trans, Pch NexFET, 20V, 5 A, 56 milliohm SON-6 CSD25302Q2 TI
1 1 Q5 2N7002 MOSFET, N-ch, 60V, 115mA, 1.2Ohms SOT23 2N7002-7-F Diodes Inc
1 1 R1 1.00M Resistor, Chip, 1/16W, 5% 0603 STD STD
1 1 R2 0.02 ΩResistor, Chip, 1/2 watt, 1% 1206 STD STD
4 4 R3, R16, R20, 0 Resistor, Chip, 1/16W 0603 STD STD
R29
2 2 R4, R5 3.9 Resistor, Chip, 1/4W, 5% 1206 STD STD
1 1 R6 402k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 R7 499k Resistor, Chip, 1/8W, 1% 0603 STD STD
1 0 R8 100k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 0 R9 100k Resistor, Chip, 1/16W, 1% 0603 STD STD
0 1 37.4k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 0 R10 10k Resistor, Chip, 1/16W, 5% 0603 STD STD
0 1 1.00M Resistor, Chip, 1/16W, 5% 0603 STD STD
1 1 R11 1.00k Resistor, Chip, 1/16W, 1% 0603 STD STD
0 0 R12 Open Resistor, Chip 0805 STD STD
2 2 R13, R14 4.02k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 R15 0.01 Resistor, Metal Film, 1/2 watt, 1% 1206 STD STD
1 1 R17 10 Resistor, Chip, 1/16W, 5% 0805 STD STD
1 0 R19 10 Resistor, Chip, 1/16W, 5% 0805 STD STD
1 1 R21 5.23k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 0 R22 0 Resistor, Chip, 1/16W 0603 STD STD
1 1 R23 100 Resistor, Chip, 1/16W, 5% 0603 STD STD
1 1 R24 30.1k Resistor, Chip, 1/16W, 1% 0603 STD STD
1 1 R25 3.01M Resistor, Chip, 1/16W, 1% 0603 STD STD
10 bq24133EVM Stand-Alone Synchronous, Switch-Mode, Battery-Charge SLUU476–December 2010
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