Texas Instruments MSP430x5 series User manual

MSP430x5xx and MSP430x6xx Family
User's Guide
Literature Number: SLAU208Q
June 2008–Revised March 2018

2SLAU208Q–June 2008–Revised March 2018
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Contents
Contents
Preface....................................................................................................................................... 52
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)....................... 54
1.1 System Control Module (SYS) Introduction ............................................................................ 55
1.2 System Reset and Initialization........................................................................................... 55
1.2.1 Device Initial Conditions After System Reset.................................................................. 57
1.3 Interrupts .................................................................................................................... 57
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 58
1.3.2 SNMI Timing ....................................................................................................... 59
1.3.3 Maskable Interrupts............................................................................................... 59
1.3.4 Interrupt Processing............................................................................................... 59
1.3.5 Interrupt Nesting................................................................................................... 61
1.3.6 Interrupt Vectors................................................................................................... 61
1.3.7 SYS Interrupt Vector Generators................................................................................ 62
1.4 Operating Modes........................................................................................................... 63
1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4............................................. 66
1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 67
1.4.3 Extended Time in Low-Power Modes .......................................................................... 68
1.5 Principles for Low-Power Applications .................................................................................. 69
1.6 Connection of Unused Pins............................................................................................... 70
1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 70
1.8 Configuring JTAG Pins .................................................................................................... 71
1.9 Boot Code................................................................................................................... 71
1.10 Bootloader (BSL)........................................................................................................... 71
1.11 Memory Map – Uses and Abilities ....................................................................................... 72
1.11.1 Vacant Memory Space .......................................................................................... 73
1.11.2 JTAG Lock Mechanism Using the Electronic Fuse.......................................................... 73
1.12 JTAG Mailbox (JMB) System ............................................................................................ 73
1.12.1 JMB Configuration ............................................................................................... 73
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox................................................................. 73
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox....................................................................... 74
1.12.4 JMB NMI Usage.................................................................................................. 74
1.13 Device Descriptor Table................................................................................................... 74
1.13.1 Identifying Device Type.......................................................................................... 75
1.13.2 TLV Descriptors .................................................................................................. 75
1.13.3 Peripheral Discovery Descriptor ............................................................................... 77
1.13.4 CRC Computation................................................................................................ 81
1.13.5 Calibration Values................................................................................................ 82
1.13.6 Temperature Sensor Calibration for Devices With CTSD16 ............................................... 83
1.14 SFR Registers .............................................................................................................. 84
1.14.1 SFRIE1 Register ................................................................................................. 85
1.14.2 SFRIFG1 Register ............................................................................................... 86
1.14.3 SFRRPCR Register.............................................................................................. 87
1.15 SYS Registers .............................................................................................................. 88
1.15.1 SYSCTL Register ................................................................................................ 89
1.15.2 SYSBSLC Register .............................................................................................. 90

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1.15.3 SYSJMBC Register.............................................................................................. 91
1.15.4 SYSJMBI0 Register.............................................................................................. 92
1.15.5 SYSJMBI1 Register.............................................................................................. 92
1.15.6 SYSJMBO0 Register ............................................................................................ 93
1.15.7 SYSJMBO1 Register ............................................................................................ 93
1.15.8 SYSUNIV Register............................................................................................... 94
1.15.9 SYSSNIV Register ............................................................................................... 95
1.15.10 SYSRSTIV Register............................................................................................ 96
1.15.11 SYSBERRIV Register.......................................................................................... 97
2 Power Management Module and Supply Voltage Supervisor ................................................... 98
2.1 Power Management Module (PMM) Introduction ...................................................................... 99
2.2 PMM Operation ........................................................................................................... 101
2.2.1 VCORE and the Regulator......................................................................................... 101
2.2.2 Supply Voltage Supervisor and Monitor ...................................................................... 101
2.2.3 Supply Voltage Supervisor and Monitor - Power up ........................................................ 107
2.2.4 Increasing VCORE to Support Higher MCLK Frequencies ................................................... 107
2.2.5 Decreasing VCORE for Power Optimization .................................................................... 109
2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................ 109
2.2.7 LPM3.5 and LPM4.5 ............................................................................................ 109
2.2.8 Brownout Reset (BOR), Software BOR, Software POR.................................................... 109
2.2.9 SVS and SVM Performance Modes and Wake-up Times ................................................. 110
2.2.10 PMM Interrupts.................................................................................................. 113
2.2.11 Port I/O Control ................................................................................................. 113
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional)...................................................... 113
2.3 PMM Registers............................................................................................................ 114
2.3.1 PMMCTL0 Register.............................................................................................. 115
2.3.2 PMMCTL1 Register.............................................................................................. 116
2.3.3 SVSMHCTL Register............................................................................................ 117
2.3.4 SVSMLCTL Register ............................................................................................ 118
2.3.5 SVSMIO Register................................................................................................ 119
2.3.6 PMMIFG Register................................................................................................ 120
2.3.7 PMMRIE Register................................................................................................ 122
2.3.8 PM5CTL0 Register .............................................................................................. 123
3 Battery Backup System ..................................................................................................... 124
3.1 Battery Backup Introduction............................................................................................. 125
3.2 Battery Backup Operation ............................................................................................... 125
3.2.1 Activate Access to Backup-Supplied Subsystem............................................................ 126
3.2.2 Manual Switching................................................................................................ 127
3.2.3 Disable Switching................................................................................................ 127
3.2.4 Measuring the Supplies......................................................................................... 127
3.2.5 LPMx.5 and Backup Operation ................................................................................ 127
3.2.6 Resistive Charger................................................................................................ 128
3.3 Battery Backup Registers................................................................................................ 129
3.3.1 BAKCTL Register................................................................................................ 130
3.3.2 BAKCHCTL Register............................................................................................ 131
4 Auxiliary Supply System (AUX) .......................................................................................... 132
4.1 Auxiliary Supply System Introduction .................................................................................. 133
4.2 Auxiliary Supply Operation .............................................................................................. 134
4.2.1 Start-up............................................................................................................ 135
4.2.2 Switching Control ................................................................................................ 136
4.2.3 Software-Controlled Switching................................................................................. 136
4.2.4 Hardware-Controlled Switching................................................................................ 136
4.2.5 Interactions Among fSYS, VCORE, VDSYS, SVMH, and AUXxLVL ............................................... 138

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4.2.6 Auxiliary Supply Monitor ........................................................................................ 140
4.2.7 LPMx.5 and Auxiliary Supply Operation ...................................................................... 142
4.2.8 Digital I/Os and Auxiliary Supplies............................................................................. 142
4.2.9 Measuring the Supplies......................................................................................... 143
4.2.10 Resistive Charger............................................................................................... 144
4.2.11 Auxiliary Supply Interrupts..................................................................................... 144
4.2.12 Software Flow................................................................................................... 146
4.2.13 Examples of AUX Operation .................................................................................. 146
4.3 AUX Registers............................................................................................................. 149
4.3.1 AUXCTL0 Register .............................................................................................. 150
4.3.2 AUXCTL1 Register .............................................................................................. 151
4.3.3 AUXCTL2 Register .............................................................................................. 152
4.3.4 AUX2CHCTL Register .......................................................................................... 153
4.3.5 AUX3CHCTL Register .......................................................................................... 154
4.3.6 AUXADCCTL Register.......................................................................................... 155
4.3.7 AUXIFG Register ................................................................................................ 156
4.3.8 AUXIE Register .................................................................................................. 157
4.3.9 AUXIV Register .................................................................................................. 158
5 Unified Clock System (UCS)............................................................................................... 159
5.1 Unified Clock System (UCS) Introduction ............................................................................. 160
5.2 UCS Operation............................................................................................................ 162
5.2.1 UCS Module Features for Low-Power Applications......................................................... 162
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 162
5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO).......................................... 163
5.2.4 XT1 Oscillator .................................................................................................... 163
5.2.5 XT2 Oscillator ................................................................................................... 164
5.2.6 Digitally Controlled Oscillator (DCO) .......................................................................... 165
5.2.7 Frequency Locked Loop (FLL)................................................................................. 166
5.2.8 DCO Modulator .................................................................................................. 167
5.2.9 Disabling FLL Hardware and Modulator ...................................................................... 167
5.2.10 FLL Operation From Low-Power Modes..................................................................... 167
5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules................................ 168
5.2.12 UCS Module Fail-Safe Operation............................................................................. 169
5.2.13 Synchronization of Clock Signals............................................................................. 172
5.3 Module Oscillator (MODOSC)........................................................................................... 173
5.3.1 MODOSC Operation ............................................................................................ 173
5.4 UCS Registers ............................................................................................................ 174
5.4.1 UCSCTL0 Register .............................................................................................. 175
5.4.2 UCSCTL1 Register .............................................................................................. 176
5.4.3 UCSCTL2 Register .............................................................................................. 177
5.4.4 UCSCTL3 Register .............................................................................................. 178
5.4.5 UCSCTL4 Register .............................................................................................. 179
5.4.6 UCSCTL5 Register .............................................................................................. 180
5.4.7 UCSCTL6 Register .............................................................................................. 181
5.4.8 UCSCTL7 Register .............................................................................................. 183
5.4.9 UCSCTL8 Register .............................................................................................. 184
5.4.10 UCSCTL9 Register............................................................................................. 185
6 CPUX .............................................................................................................................. 186
6.1 MSP430X CPU (CPUX) Introduction................................................................................... 187
6.2 Interrupts................................................................................................................... 189
6.3 CPU Registers ............................................................................................................ 190
6.3.1 Program Counter (PC) .......................................................................................... 190
6.3.2 Stack Pointer (SP)............................................................................................... 190

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6.3.3 Status Register (SR) ............................................................................................ 192
6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 193
6.3.5 General-Purpose Registers (R4 to R15)...................................................................... 194
6.4 Addressing Modes........................................................................................................ 196
6.4.1 Register Mode.................................................................................................... 197
6.4.2 Indexed Mode .................................................................................................... 198
6.4.3 Symbolic Mode................................................................................................... 203
6.4.4 Absolute Mode ................................................................................................... 207
6.4.5 Indirect Register Mode.......................................................................................... 209
6.4.6 Indirect Autoincrement Mode................................................................................... 210
6.4.7 Immediate Mode ................................................................................................. 211
6.5 MSP430 and MSP430X Instructions................................................................................... 213
6.5.1 MSP430 Instructions ............................................................................................ 213
6.5.2 MSP430X Extended Instructions .............................................................................. 218
6.6 Instruction Set Description............................................................................................... 229
6.6.1 Extended Instruction Binary Descriptions..................................................................... 230
6.6.2 MSP430 Instructions ............................................................................................ 232
6.6.3 Extended Instructions ........................................................................................... 284
6.6.4 Address Instructions............................................................................................. 327
7 Flash Memory Controller ................................................................................................... 342
7.1 Flash Memory Introduction .............................................................................................. 343
7.2 Flash Memory Segmentation............................................................................................ 344
7.2.1 Segment A........................................................................................................ 345
7.3 Flash Memory Operation ................................................................................................ 346
7.3.1 Erasing Flash Memory .......................................................................................... 346
7.3.2 Writing Flash Memory........................................................................................... 350
7.3.3 Flash Memory Access During Write or Erase................................................................ 357
7.3.4 Stopping Write or Erase Cycle................................................................................. 358
7.3.5 Checking Flash Memory........................................................................................ 358
7.3.6 Configuring and Accessing the Flash Memory Controller.................................................. 359
7.3.7 Flash Memory Controller Interrupts ........................................................................... 359
7.3.8 Programming Flash Memory Devices......................................................................... 360
7.4 FCTL Registers ........................................................................................................... 361
7.4.1 FCTL1 Register .................................................................................................. 362
7.4.2 FCTL3 Register .................................................................................................. 363
7.4.3 FCTL4 Register .................................................................................................. 364
7.4.4 SFRIE1 Register................................................................................................. 365
8 Memory Integrity Detection (MID)........................................................................................ 366
8.1 MID Overview ............................................................................................................. 367
8.2 Flash Memory With MID Support....................................................................................... 368
8.3 MID Parity Check Logic.................................................................................................. 368
8.4 Detecting Unprogrammed Memory Accesses ........................................................................ 368
8.5 MID ROM .................................................................................................................. 369
8.6 MID Support Software Function ........................................................................................ 369
8.6.1 MidEnable() Function............................................................................................ 370
8.6.2 MidDisable() Function........................................................................................... 371
8.6.3 MidGetErrAdr() Function........................................................................................ 371
8.6.4 MidCheckMem() Function ...................................................................................... 372
8.6.5 MidSetRaw() Function........................................................................................... 372
8.6.6 MidGetParity() Function......................................................................................... 373
8.6.7 MidCalcVParity() Function...................................................................................... 373
8.7 User's UNMI Interrupt Handler.......................................................................................... 373

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9 RAM Controller (RAMCTL) ................................................................................................. 374
9.1 RAM Controller (RAMCTL) Introduction ............................................................................... 375
9.2 RAMCTL Operation....................................................................................................... 375
9.3 RAMCTL Registers....................................................................................................... 376
9.3.1 RCCTL0 Register................................................................................................ 377
10 Backup RAM .................................................................................................................... 378
10.1 Backup RAM Introduction and Operation.............................................................................. 379
10.2 Battery Backup Registers................................................................................................ 379
11 Direct Memory Access (DMA) Controller Module .................................................................. 380
11.1 Direct Memory Access (DMA) Introduction............................................................................ 381
11.2 DMA Operation............................................................................................................ 383
11.2.1 DMA Addressing Modes....................................................................................... 383
11.2.2 DMA Transfer Modes .......................................................................................... 384
11.2.3 Initiating DMA Transfers ....................................................................................... 390
11.2.4 Halting Executing Instructions for DMA Transfers.......................................................... 390
11.2.5 Stopping DMA Transfers....................................................................................... 391
11.2.6 DMA Channel Priorities........................................................................................ 391
11.2.7 DMA Transfer Cycle Time..................................................................................... 392
11.2.8 Using DMA With System Interrupts .......................................................................... 392
11.2.9 DMA Controller Interrupts ..................................................................................... 392
11.2.10 Using the USCI_B I2C Module With the DMA Controller................................................. 394
11.2.11 Using ADC10 With the DMA Controller .................................................................... 394
11.2.12 Using ADC12 With the DMA Controller .................................................................... 394
11.2.13 Using DAC12 With the DMA Controller .................................................................... 394
11.3 DMA Registers............................................................................................................ 395
11.3.1 DMACTL0 Register............................................................................................. 397
11.3.2 DMACTL1 Register............................................................................................. 398
11.3.3 DMACTL2 Register............................................................................................. 399
11.3.4 DMACTL3 Register............................................................................................. 400
11.3.5 DMACTL4 Register............................................................................................. 401
11.3.6 DMAxCTL Register............................................................................................. 402
11.3.7 DMAxSA Register .............................................................................................. 404
11.3.8 DMAxDA Register .............................................................................................. 405
11.3.9 DMAxSZ Register............................................................................................... 406
11.3.10 DMAIV Register ............................................................................................... 407
12 Digital I/O Module ............................................................................................................. 408
12.1 Digital I/O Introduction ................................................................................................... 409
12.2 Digital I/O Operation...................................................................................................... 410
12.2.1 Input Registers (PxIN).......................................................................................... 410
12.2.2 Output Registers (PxOUT) .................................................................................... 410
12.2.3 Direction Registers (PxDIR)................................................................................... 410
12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 410
12.2.5 Output Drive Strength Registers (PxDS) .................................................................... 411
12.2.6 Function Select Registers (PxSEL) .......................................................................... 411
12.2.7 Port Interrupts................................................................................................... 411
12.2.8 Configuring Unused Port Pins ................................................................................ 413
12.3 I/O Configuration and LPMx.5 Low-Power Modes ................................................................... 413
12.4 Digital I/O Registers ...................................................................................................... 416
12.4.1 P1IV Register ................................................................................................... 422
12.4.2 P2IV Register ................................................................................................... 423
12.4.3 P1IES Register.................................................................................................. 424
12.4.4 P1IE Register ................................................................................................... 424
12.4.5 P1IFG Register.................................................................................................. 424

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12.4.6 P2IES Register.................................................................................................. 425
12.4.7 P2IE Register ................................................................................................... 425
12.4.8 P2IFG Register.................................................................................................. 425
12.4.9 PxIN Register ................................................................................................... 426
12.4.10 PxOUT Register............................................................................................... 426
12.4.11 PxDIR Register................................................................................................ 426
12.4.12 PxREN Register............................................................................................... 427
12.4.13 PxDS Register................................................................................................. 427
12.4.14 PxSEL Register................................................................................................ 427
13 Port Mapping Controller .................................................................................................... 428
13.1 Port Mapping Controller Introduction................................................................................... 429
13.2 Port Mapping Controller Operation..................................................................................... 429
13.2.1 Access ........................................................................................................... 429
13.2.2 Mapping.......................................................................................................... 429
13.3 Port Mapping Controller Registers ..................................................................................... 431
13.3.1 PMAPKEYID Register.......................................................................................... 432
13.3.2 PMAPCTL Register............................................................................................. 432
13.3.3 PxMAPy Register............................................................................................... 432
14 Cyclic Redundancy Check (CRC) Module ............................................................................ 433
14.1 Cyclic Redundancy Check (CRC) Module Introduction.............................................................. 434
14.2 CRC Standard and Bit Order............................................................................................ 434
14.3 CRC Checksum Generation............................................................................................. 435
14.3.1 CRC Implementation........................................................................................... 435
14.3.2 Assembler Examples........................................................................................... 436
14.4 CRC Registers ............................................................................................................ 438
14.4.1 CRCDI Register................................................................................................. 439
14.4.2 CRCDIRB Register............................................................................................. 439
14.4.3 CRCINIRES Register........................................................................................... 440
14.4.4 CRCRESR Register............................................................................................ 440
15 AES Accelerator ............................................................................................................... 441
15.1 AES Accelerator Introduction............................................................................................ 442
15.2 AES Accelerator Operation.............................................................................................. 443
15.2.1 Encryption ....................................................................................................... 444
15.2.2 Decryption ....................................................................................................... 445
15.2.3 Decryption Key Generation.................................................................................... 446
15.2.4 Using the AES Accelerator With Low-Power Modes....................................................... 447
15.2.5 AES Accelerator Interrupts .................................................................................... 447
15.2.6 Implementing Block Cipher Modes........................................................................... 447
15.3 AES_ACCEL Registers .................................................................................................. 448
15.3.1 AESACTL0 Register............................................................................................ 449
15.3.2 AESASTAT Register ........................................................................................... 450
15.3.3 AESAKEY Register............................................................................................. 451
15.3.4 AESADIN Register ............................................................................................. 452
15.3.5 AESADOUT Register .......................................................................................... 452
16 Watchdog Timer (WDT_A).................................................................................................. 453
16.1 WDT_A Introduction...................................................................................................... 454
16.2 WDT_A Operation ........................................................................................................ 456
16.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 456
16.2.2 Watchdog Mode ................................................................................................ 456
16.2.3 Interval Timer Mode ............................................................................................ 456
16.2.4 Watchdog Timer Interrupts .................................................................................... 456
16.2.5 Clock Fail-Safe Feature........................................................................................ 457

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16.2.6 Operation in Low-Power Modes .............................................................................. 457
16.2.7 Software Examples............................................................................................. 457
16.3 WDT_A Registers......................................................................................................... 458
16.3.1 WDTCTL Register .............................................................................................. 459
17 Timer_A........................................................................................................................... 460
17.1 Timer_A Introduction ..................................................................................................... 461
17.2 Timer_A Operation ....................................................................................................... 463
17.2.1 16-Bit Timer Counter........................................................................................... 463
17.2.2 Starting the Timer............................................................................................... 463
17.2.3 Timer Mode Control ............................................................................................ 464
17.2.4 Capture/Compare Blocks...................................................................................... 467
17.2.5 Output Unit ...................................................................................................... 469
17.2.6 Timer_A Interrupts.............................................................................................. 473
17.3 Timer_A Registers........................................................................................................ 475
17.3.1 TAxCTL Register ............................................................................................... 476
17.3.2 TAxR Register................................................................................................... 477
17.3.3 TAxCCTLn Register............................................................................................ 478
17.3.4 TAxCCRn Register ............................................................................................ 480
17.3.5 TAxIV Register.................................................................................................. 480
17.3.6 TAxEX0 Register ............................................................................................... 481
18 Timer_B........................................................................................................................... 482
18.1 Timer_B Introduction ..................................................................................................... 483
18.1.1 Similarities and Differences From Timer_A ................................................................. 483
18.2 Timer_B Operation ....................................................................................................... 485
18.2.1 16-Bit Timer Counter........................................................................................... 485
18.2.2 Starting the Timer............................................................................................... 485
18.2.3 Timer Mode Control ............................................................................................ 486
18.2.4 Capture/Compare Blocks...................................................................................... 489
18.2.5 Output Unit ...................................................................................................... 492
18.2.6 Timer_B Interrupts.............................................................................................. 496
18.3 Timer_B Registers........................................................................................................ 498
18.3.1 TBxCTL Register ............................................................................................... 499
18.3.2 TBxR Register................................................................................................... 501
18.3.3 TBxCCTLn Register............................................................................................ 502
18.3.4 TBxCCRn Register ............................................................................................. 504
18.3.5 TBxIV Register.................................................................................................. 505
18.3.6 TBxEX0 Register ............................................................................................... 506
19 Timer_D........................................................................................................................... 507
19.1 Timer_D Introduction..................................................................................................... 508
19.1.1 Differences From Timer_B .................................................................................... 508
19.2 Timer_D Operation ....................................................................................................... 510
19.2.1 16-Bit Timer Counter........................................................................................... 510
19.2.2 High-Resolution Generator.................................................................................... 511
19.2.3 Starting the Timer............................................................................................... 513
19.2.4 Timer Mode Control ............................................................................................ 513
19.2.5 PWM Generation ............................................................................................... 518
19.2.6 Capture/Compare Blocks...................................................................................... 521
19.2.7 Compare Mode.................................................................................................. 524
19.2.8 Switching From Capture to Compare Mode................................................................. 525
19.2.9 Output Unit ...................................................................................................... 525
19.2.10 Synchronization Between Timer_D Instances ............................................................ 532
19.2.11 Timer_D Interrupts ............................................................................................ 532
19.3 Timer_D Registers........................................................................................................ 534

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19.3.1 TDxCTL0 Register.............................................................................................. 535
19.3.2 TDxCTL1 Register.............................................................................................. 537
19.3.3 TDxCTL2 Register.............................................................................................. 538
19.3.4 TDxR Register .................................................................................................. 539
19.3.5 TDxCCTLn Register............................................................................................ 540
19.3.6 TDxCCRn Register............................................................................................. 542
19.3.7 TDxCLn Register ............................................................................................... 542
19.3.8 TDxHCTL0 Register............................................................................................ 543
19.3.9 TDxHCTL1 Register............................................................................................ 544
19.3.10 TDxHINT Register............................................................................................. 545
19.3.11 TDxIV Register ................................................................................................ 546
20 Timer Event Control (TEC)................................................................................................. 547
20.1 Timer Event Control Introduction ....................................................................................... 548
20.2 TEC Operation ............................................................................................................ 549
20.2.1 AUXCLK Selection Sub-Block ................................................................................ 549
20.2.2 External Clear Sub-Block ..................................................................................... 549
20.2.3 Channel Event Sub-Block..................................................................................... 549
20.2.4 Module Level Connection Between TEC and Timer_D.................................................... 550
20.2.5 Synchronization Mechanism Between Timer_D Instances................................................ 552
20.2.6 Timer Event Control Interrupts................................................................................ 554
20.3 TEC Registers............................................................................................................. 555
20.3.1 TECxCTL0 Register............................................................................................ 556
20.3.2 TECxCTL1 Register............................................................................................ 558
20.3.3 TECxCTL2 Register............................................................................................ 560
20.3.4 TECxSTA Register ............................................................................................. 561
20.3.5 TECxINT Register .............................................................................................. 562
20.3.6 TECxIV Register................................................................................................ 563
21 Real-Time Clock (RTC) Overview........................................................................................ 564
21.1 RTC Overview............................................................................................................. 564
22 Real-Time Clock (RTC_A) .................................................................................................. 565
22.1 RTC_A Introduction....................................................................................................... 566
22.2 RTC_A Operation......................................................................................................... 568
22.2.1 Counter Mode................................................................................................... 568
22.2.2 Calendar Mode.................................................................................................. 568
22.2.3 Real-Time Clock Interrupts.................................................................................... 570
22.2.4 Real-Time Clock Calibration .................................................................................. 572
22.3 RTC_A Registers ......................................................................................................... 574
22.3.1 RTCCTL0 Register ............................................................................................. 576
22.3.2 RTCCTL1 Register ............................................................................................. 577
22.3.3 RTCCTL2 Register ............................................................................................. 578
22.3.4 RTCCTL3 Register ............................................................................................. 578
22.3.5 RTCNT1 Register............................................................................................... 579
22.3.6 RTCNT2 Register............................................................................................... 579
22.3.7 RTCNT3 Register............................................................................................... 579
22.3.8 RTCNT4 Register............................................................................................... 579
22.3.9 RTCSEC Register – Calendar Mode With Hexadecimal Format......................................... 580
22.3.10 RTCSEC Register – Calendar Mode With BCD Format................................................. 580
22.3.11 RTCMIN Register – Calendar Mode With Hexadecimal Format........................................ 581
22.3.12 RTCMIN Register – Calendar Mode With BCD Format.................................................. 581
22.3.13 RTCHOUR Register – Calendar Mode With Hexadecimal Format..................................... 582
22.3.14 RTCHOUR Register – Calendar Mode With BCD Format............................................... 582
22.3.15 RTCDOW Register – Calendar Mode ...................................................................... 583

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22.3.16 RTCDAY Register – Calendar Mode With Hexadecimal Format ....................................... 583
22.3.17 RTCDAY Register – Calendar Mode With BCD Format................................................. 583
22.3.18 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 584
22.3.19 RTCMON Register – Calendar Mode With BCD Format ................................................ 584
22.3.20 RTCYEARL Register – Calendar Mode With Hexadecimal Format.................................... 585
22.3.21 RTCYEARL Register – Calendar Mode With BCD Format.............................................. 585
22.3.22 RTCYEARH Register – Calendar Mode With Hexadecimal Format ................................... 586
22.3.23 RTCYEARH Register – Calendar Mode With BCD Format ............................................. 586
22.3.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format...................................... 587
22.3.25 RTCAMIN Register – Calendar Mode With BCD Format................................................ 587
22.3.26 RTCAHOUR Register – Calendar Mode With Hexadecimal Format................................... 588
22.3.27 RTCAHOUR Register – Calendar Mode With BCD Format............................................. 588
22.3.28 RTCADOW Register.......................................................................................... 589
22.3.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 589
22.3.30 RTCADAY Register – Calendar Mode With BCD Format ............................................... 590
22.3.31 RTCPS0CTL Register ........................................................................................ 591
22.3.32 RTCPS1CTL Register ........................................................................................ 592
22.3.33 RT0PS Register ............................................................................................... 593
22.3.34 RT1PS Register ............................................................................................... 593
22.3.35 RTCIV Register................................................................................................ 593
23 Real-Time Clock B (RTC_B) ............................................................................................... 594
23.1 Real-Time Clock RTC_B Introduction.................................................................................. 595
23.2 RTC_B Operation......................................................................................................... 597
23.2.1 Real-Time Clock and Prescale Dividers..................................................................... 597
23.2.2 Real-Time Clock Alarm Function ............................................................................. 597
23.2.3 Reading or Writing Real-Time Clock Registers............................................................. 598
23.2.4 Real-Time Clock Interrupts.................................................................................... 598
23.2.5 Real-Time Clock Calibration .................................................................................. 600
23.2.6 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 601
23.3 RTC_B Registers ......................................................................................................... 602
23.3.1 RTCCTL0 Register ............................................................................................. 604
23.3.2 RTCCTL1 Register ............................................................................................. 605
23.3.3 RTCCTL2 Register ............................................................................................. 606
23.3.4 RTCCTL3 Register ............................................................................................. 606
23.3.5 RTCSEC Register – Hexadecimal Format .................................................................. 607
23.3.6 RTCSEC Register – BCD Format ............................................................................ 607
23.3.7 RTCMIN Register – Hexadecimal Format................................................................... 608
23.3.8 RTCMIN Register – BCD Format............................................................................. 608
23.3.9 RTCHOUR Register – Hexadecimal Format................................................................ 609
23.3.10 RTCHOUR Register – BCD Format ........................................................................ 609
23.3.11 RTCDOW Register............................................................................................ 610
23.3.12 RTCDAY Register – Hexadecimal Format................................................................. 610
23.3.13 RTCDAY Register – BCD Format........................................................................... 610
23.3.14 RTCMON Register – Hexadecimal Format................................................................ 611
23.3.15 RTCMON Register – BCD Format.......................................................................... 611
23.3.16 RTCYEAR Register – Hexadecimal Format............................................................... 612
23.3.17 RTCYEAR Register – BCD Format......................................................................... 612
23.3.18 RTCAMIN Register – Hexadecimal Format ............................................................... 613
23.3.19 RTCAMIN Register – BCD Format ......................................................................... 613
23.3.20 RTCAHOUR Register – Hexadecimal Format ............................................................ 614
23.3.21 RTCAHOUR Register – BCD Format ...................................................................... 614
23.3.22 RTCADOW Register.......................................................................................... 615
23.3.23 RTCADAY Register – Hexadecimal Format............................................................... 616