Texas Instruments MSP430x5 series User manual

MSP430x5xx and MSP430x6xx Family
User's Guide
Literature Number: SLAU208Q
June 2008–Revised March 2018

2SLAU208Q–June 2008–Revised March 2018
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Contents
Contents
Preface....................................................................................................................................... 52
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)....................... 54
1.1 System Control Module (SYS) Introduction ............................................................................ 55
1.2 System Reset and Initialization........................................................................................... 55
1.2.1 Device Initial Conditions After System Reset.................................................................. 57
1.3 Interrupts .................................................................................................................... 57
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 58
1.3.2 SNMI Timing ....................................................................................................... 59
1.3.3 Maskable Interrupts............................................................................................... 59
1.3.4 Interrupt Processing............................................................................................... 59
1.3.5 Interrupt Nesting................................................................................................... 61
1.3.6 Interrupt Vectors................................................................................................... 61
1.3.7 SYS Interrupt Vector Generators................................................................................ 62
1.4 Operating Modes........................................................................................................... 63
1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4............................................. 66
1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 67
1.4.3 Extended Time in Low-Power Modes .......................................................................... 68
1.5 Principles for Low-Power Applications .................................................................................. 69
1.6 Connection of Unused Pins............................................................................................... 70
1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 70
1.8 Configuring JTAG Pins .................................................................................................... 71
1.9 Boot Code................................................................................................................... 71
1.10 Bootloader (BSL)........................................................................................................... 71
1.11 Memory Map – Uses and Abilities ....................................................................................... 72
1.11.1 Vacant Memory Space .......................................................................................... 73
1.11.2 JTAG Lock Mechanism Using the Electronic Fuse.......................................................... 73
1.12 JTAG Mailbox (JMB) System ............................................................................................ 73
1.12.1 JMB Configuration ............................................................................................... 73
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox................................................................. 73
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox....................................................................... 74
1.12.4 JMB NMI Usage.................................................................................................. 74
1.13 Device Descriptor Table................................................................................................... 74
1.13.1 Identifying Device Type.......................................................................................... 75
1.13.2 TLV Descriptors .................................................................................................. 75
1.13.3 Peripheral Discovery Descriptor ............................................................................... 77
1.13.4 CRC Computation................................................................................................ 81
1.13.5 Calibration Values................................................................................................ 82
1.13.6 Temperature Sensor Calibration for Devices With CTSD16 ............................................... 83
1.14 SFR Registers .............................................................................................................. 84
1.14.1 SFRIE1 Register ................................................................................................. 85
1.14.2 SFRIFG1 Register ............................................................................................... 86
1.14.3 SFRRPCR Register.............................................................................................. 87
1.15 SYS Registers .............................................................................................................. 88
1.15.1 SYSCTL Register ................................................................................................ 89
1.15.2 SYSBSLC Register .............................................................................................. 90

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1.15.3 SYSJMBC Register.............................................................................................. 91
1.15.4 SYSJMBI0 Register.............................................................................................. 92
1.15.5 SYSJMBI1 Register.............................................................................................. 92
1.15.6 SYSJMBO0 Register ............................................................................................ 93
1.15.7 SYSJMBO1 Register ............................................................................................ 93
1.15.8 SYSUNIV Register............................................................................................... 94
1.15.9 SYSSNIV Register ............................................................................................... 95
1.15.10 SYSRSTIV Register............................................................................................ 96
1.15.11 SYSBERRIV Register.......................................................................................... 97
2 Power Management Module and Supply Voltage Supervisor ................................................... 98
2.1 Power Management Module (PMM) Introduction ...................................................................... 99
2.2 PMM Operation ........................................................................................................... 101
2.2.1 VCORE and the Regulator......................................................................................... 101
2.2.2 Supply Voltage Supervisor and Monitor ...................................................................... 101
2.2.3 Supply Voltage Supervisor and Monitor - Power up ........................................................ 107
2.2.4 Increasing VCORE to Support Higher MCLK Frequencies ................................................... 107
2.2.5 Decreasing VCORE for Power Optimization .................................................................... 109
2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................ 109
2.2.7 LPM3.5 and LPM4.5 ............................................................................................ 109
2.2.8 Brownout Reset (BOR), Software BOR, Software POR.................................................... 109
2.2.9 SVS and SVM Performance Modes and Wake-up Times ................................................. 110
2.2.10 PMM Interrupts.................................................................................................. 113
2.2.11 Port I/O Control ................................................................................................. 113
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional)...................................................... 113
2.3 PMM Registers............................................................................................................ 114
2.3.1 PMMCTL0 Register.............................................................................................. 115
2.3.2 PMMCTL1 Register.............................................................................................. 116
2.3.3 SVSMHCTL Register............................................................................................ 117
2.3.4 SVSMLCTL Register ............................................................................................ 118
2.3.5 SVSMIO Register................................................................................................ 119
2.3.6 PMMIFG Register................................................................................................ 120
2.3.7 PMMRIE Register................................................................................................ 122
2.3.8 PM5CTL0 Register .............................................................................................. 123
3 Battery Backup System ..................................................................................................... 124
3.1 Battery Backup Introduction............................................................................................. 125
3.2 Battery Backup Operation ............................................................................................... 125
3.2.1 Activate Access to Backup-Supplied Subsystem............................................................ 126
3.2.2 Manual Switching................................................................................................ 127
3.2.3 Disable Switching................................................................................................ 127
3.2.4 Measuring the Supplies......................................................................................... 127
3.2.5 LPMx.5 and Backup Operation ................................................................................ 127
3.2.6 Resistive Charger................................................................................................ 128
3.3 Battery Backup Registers................................................................................................ 129
3.3.1 BAKCTL Register................................................................................................ 130
3.3.2 BAKCHCTL Register............................................................................................ 131
4 Auxiliary Supply System (AUX) .......................................................................................... 132
4.1 Auxiliary Supply System Introduction .................................................................................. 133
4.2 Auxiliary Supply Operation .............................................................................................. 134
4.2.1 Start-up............................................................................................................ 135
4.2.2 Switching Control ................................................................................................ 136
4.2.3 Software-Controlled Switching................................................................................. 136
4.2.4 Hardware-Controlled Switching................................................................................ 136
4.2.5 Interactions Among fSYS, VCORE, VDSYS, SVMH, and AUXxLVL ............................................... 138

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4.2.6 Auxiliary Supply Monitor ........................................................................................ 140
4.2.7 LPMx.5 and Auxiliary Supply Operation ...................................................................... 142
4.2.8 Digital I/Os and Auxiliary Supplies............................................................................. 142
4.2.9 Measuring the Supplies......................................................................................... 143
4.2.10 Resistive Charger............................................................................................... 144
4.2.11 Auxiliary Supply Interrupts..................................................................................... 144
4.2.12 Software Flow................................................................................................... 146
4.2.13 Examples of AUX Operation .................................................................................. 146
4.3 AUX Registers............................................................................................................. 149
4.3.1 AUXCTL0 Register .............................................................................................. 150
4.3.2 AUXCTL1 Register .............................................................................................. 151
4.3.3 AUXCTL2 Register .............................................................................................. 152
4.3.4 AUX2CHCTL Register .......................................................................................... 153
4.3.5 AUX3CHCTL Register .......................................................................................... 154
4.3.6 AUXADCCTL Register.......................................................................................... 155
4.3.7 AUXIFG Register ................................................................................................ 156
4.3.8 AUXIE Register .................................................................................................. 157
4.3.9 AUXIV Register .................................................................................................. 158
5 Unified Clock System (UCS)............................................................................................... 159
5.1 Unified Clock System (UCS) Introduction ............................................................................. 160
5.2 UCS Operation............................................................................................................ 162
5.2.1 UCS Module Features for Low-Power Applications......................................................... 162
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 162
5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO).......................................... 163
5.2.4 XT1 Oscillator .................................................................................................... 163
5.2.5 XT2 Oscillator ................................................................................................... 164
5.2.6 Digitally Controlled Oscillator (DCO) .......................................................................... 165
5.2.7 Frequency Locked Loop (FLL)................................................................................. 166
5.2.8 DCO Modulator .................................................................................................. 167
5.2.9 Disabling FLL Hardware and Modulator ...................................................................... 167
5.2.10 FLL Operation From Low-Power Modes..................................................................... 167
5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules................................ 168
5.2.12 UCS Module Fail-Safe Operation............................................................................. 169
5.2.13 Synchronization of Clock Signals............................................................................. 172
5.3 Module Oscillator (MODOSC)........................................................................................... 173
5.3.1 MODOSC Operation ............................................................................................ 173
5.4 UCS Registers ............................................................................................................ 174
5.4.1 UCSCTL0 Register .............................................................................................. 175
5.4.2 UCSCTL1 Register .............................................................................................. 176
5.4.3 UCSCTL2 Register .............................................................................................. 177
5.4.4 UCSCTL3 Register .............................................................................................. 178
5.4.5 UCSCTL4 Register .............................................................................................. 179
5.4.6 UCSCTL5 Register .............................................................................................. 180
5.4.7 UCSCTL6 Register .............................................................................................. 181
5.4.8 UCSCTL7 Register .............................................................................................. 183
5.4.9 UCSCTL8 Register .............................................................................................. 184
5.4.10 UCSCTL9 Register............................................................................................. 185
6 CPUX .............................................................................................................................. 186
6.1 MSP430X CPU (CPUX) Introduction................................................................................... 187
6.2 Interrupts................................................................................................................... 189
6.3 CPU Registers ............................................................................................................ 190
6.3.1 Program Counter (PC) .......................................................................................... 190
6.3.2 Stack Pointer (SP)............................................................................................... 190

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6.3.3 Status Register (SR) ............................................................................................ 192
6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 193
6.3.5 General-Purpose Registers (R4 to R15)...................................................................... 194
6.4 Addressing Modes........................................................................................................ 196
6.4.1 Register Mode.................................................................................................... 197
6.4.2 Indexed Mode .................................................................................................... 198
6.4.3 Symbolic Mode................................................................................................... 203
6.4.4 Absolute Mode ................................................................................................... 207
6.4.5 Indirect Register Mode.......................................................................................... 209
6.4.6 Indirect Autoincrement Mode................................................................................... 210
6.4.7 Immediate Mode ................................................................................................. 211
6.5 MSP430 and MSP430X Instructions................................................................................... 213
6.5.1 MSP430 Instructions ............................................................................................ 213
6.5.2 MSP430X Extended Instructions .............................................................................. 218
6.6 Instruction Set Description............................................................................................... 229
6.6.1 Extended Instruction Binary Descriptions..................................................................... 230
6.6.2 MSP430 Instructions ............................................................................................ 232
6.6.3 Extended Instructions ........................................................................................... 284
6.6.4 Address Instructions............................................................................................. 327
7 Flash Memory Controller ................................................................................................... 342
7.1 Flash Memory Introduction .............................................................................................. 343
7.2 Flash Memory Segmentation............................................................................................ 344
7.2.1 Segment A........................................................................................................ 345
7.3 Flash Memory Operation ................................................................................................ 346
7.3.1 Erasing Flash Memory .......................................................................................... 346
7.3.2 Writing Flash Memory........................................................................................... 350
7.3.3 Flash Memory Access During Write or Erase................................................................ 357
7.3.4 Stopping Write or Erase Cycle................................................................................. 358
7.3.5 Checking Flash Memory........................................................................................ 358
7.3.6 Configuring and Accessing the Flash Memory Controller.................................................. 359
7.3.7 Flash Memory Controller Interrupts ........................................................................... 359
7.3.8 Programming Flash Memory Devices......................................................................... 360
7.4 FCTL Registers ........................................................................................................... 361
7.4.1 FCTL1 Register .................................................................................................. 362
7.4.2 FCTL3 Register .................................................................................................. 363
7.4.3 FCTL4 Register .................................................................................................. 364
7.4.4 SFRIE1 Register................................................................................................. 365
8 Memory Integrity Detection (MID)........................................................................................ 366
8.1 MID Overview ............................................................................................................. 367
8.2 Flash Memory With MID Support....................................................................................... 368
8.3 MID Parity Check Logic.................................................................................................. 368
8.4 Detecting Unprogrammed Memory Accesses ........................................................................ 368
8.5 MID ROM .................................................................................................................. 369
8.6 MID Support Software Function ........................................................................................ 369
8.6.1 MidEnable() Function............................................................................................ 370
8.6.2 MidDisable() Function........................................................................................... 371
8.6.3 MidGetErrAdr() Function........................................................................................ 371
8.6.4 MidCheckMem() Function ...................................................................................... 372
8.6.5 MidSetRaw() Function........................................................................................... 372
8.6.6 MidGetParity() Function......................................................................................... 373
8.6.7 MidCalcVParity() Function...................................................................................... 373
8.7 User's UNMI Interrupt Handler.......................................................................................... 373

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9 RAM Controller (RAMCTL) ................................................................................................. 374
9.1 RAM Controller (RAMCTL) Introduction ............................................................................... 375
9.2 RAMCTL Operation....................................................................................................... 375
9.3 RAMCTL Registers....................................................................................................... 376
9.3.1 RCCTL0 Register................................................................................................ 377
10 Backup RAM .................................................................................................................... 378
10.1 Backup RAM Introduction and Operation.............................................................................. 379
10.2 Battery Backup Registers................................................................................................ 379
11 Direct Memory Access (DMA) Controller Module .................................................................. 380
11.1 Direct Memory Access (DMA) Introduction............................................................................ 381
11.2 DMA Operation............................................................................................................ 383
11.2.1 DMA Addressing Modes....................................................................................... 383
11.2.2 DMA Transfer Modes .......................................................................................... 384
11.2.3 Initiating DMA Transfers ....................................................................................... 390
11.2.4 Halting Executing Instructions for DMA Transfers.......................................................... 390
11.2.5 Stopping DMA Transfers....................................................................................... 391
11.2.6 DMA Channel Priorities........................................................................................ 391
11.2.7 DMA Transfer Cycle Time..................................................................................... 392
11.2.8 Using DMA With System Interrupts .......................................................................... 392
11.2.9 DMA Controller Interrupts ..................................................................................... 392
11.2.10 Using the USCI_B I2C Module With the DMA Controller................................................. 394
11.2.11 Using ADC10 With the DMA Controller .................................................................... 394
11.2.12 Using ADC12 With the DMA Controller .................................................................... 394
11.2.13 Using DAC12 With the DMA Controller .................................................................... 394
11.3 DMA Registers............................................................................................................ 395
11.3.1 DMACTL0 Register............................................................................................. 397
11.3.2 DMACTL1 Register............................................................................................. 398
11.3.3 DMACTL2 Register............................................................................................. 399
11.3.4 DMACTL3 Register............................................................................................. 400
11.3.5 DMACTL4 Register............................................................................................. 401
11.3.6 DMAxCTL Register............................................................................................. 402
11.3.7 DMAxSA Register .............................................................................................. 404
11.3.8 DMAxDA Register .............................................................................................. 405
11.3.9 DMAxSZ Register............................................................................................... 406
11.3.10 DMAIV Register ............................................................................................... 407
12 Digital I/O Module ............................................................................................................. 408
12.1 Digital I/O Introduction ................................................................................................... 409
12.2 Digital I/O Operation...................................................................................................... 410
12.2.1 Input Registers (PxIN).......................................................................................... 410
12.2.2 Output Registers (PxOUT) .................................................................................... 410
12.2.3 Direction Registers (PxDIR)................................................................................... 410
12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 410
12.2.5 Output Drive Strength Registers (PxDS) .................................................................... 411
12.2.6 Function Select Registers (PxSEL) .......................................................................... 411
12.2.7 Port Interrupts................................................................................................... 411
12.2.8 Configuring Unused Port Pins ................................................................................ 413
12.3 I/O Configuration and LPMx.5 Low-Power Modes ................................................................... 413
12.4 Digital I/O Registers ...................................................................................................... 416
12.4.1 P1IV Register ................................................................................................... 422
12.4.2 P2IV Register ................................................................................................... 423
12.4.3 P1IES Register.................................................................................................. 424
12.4.4 P1IE Register ................................................................................................... 424
12.4.5 P1IFG Register.................................................................................................. 424

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12.4.6 P2IES Register.................................................................................................. 425
12.4.7 P2IE Register ................................................................................................... 425
12.4.8 P2IFG Register.................................................................................................. 425
12.4.9 PxIN Register ................................................................................................... 426
12.4.10 PxOUT Register............................................................................................... 426
12.4.11 PxDIR Register................................................................................................ 426
12.4.12 PxREN Register............................................................................................... 427
12.4.13 PxDS Register................................................................................................. 427
12.4.14 PxSEL Register................................................................................................ 427
13 Port Mapping Controller .................................................................................................... 428
13.1 Port Mapping Controller Introduction................................................................................... 429
13.2 Port Mapping Controller Operation..................................................................................... 429
13.2.1 Access ........................................................................................................... 429
13.2.2 Mapping.......................................................................................................... 429
13.3 Port Mapping Controller Registers ..................................................................................... 431
13.3.1 PMAPKEYID Register.......................................................................................... 432
13.3.2 PMAPCTL Register............................................................................................. 432
13.3.3 PxMAPy Register............................................................................................... 432
14 Cyclic Redundancy Check (CRC) Module ............................................................................ 433
14.1 Cyclic Redundancy Check (CRC) Module Introduction.............................................................. 434
14.2 CRC Standard and Bit Order............................................................................................ 434
14.3 CRC Checksum Generation............................................................................................. 435
14.3.1 CRC Implementation........................................................................................... 435
14.3.2 Assembler Examples........................................................................................... 436
14.4 CRC Registers ............................................................................................................ 438
14.4.1 CRCDI Register................................................................................................. 439
14.4.2 CRCDIRB Register............................................................................................. 439
14.4.3 CRCINIRES Register........................................................................................... 440
14.4.4 CRCRESR Register............................................................................................ 440
15 AES Accelerator ............................................................................................................... 441
15.1 AES Accelerator Introduction............................................................................................ 442
15.2 AES Accelerator Operation.............................................................................................. 443
15.2.1 Encryption ....................................................................................................... 444
15.2.2 Decryption ....................................................................................................... 445
15.2.3 Decryption Key Generation.................................................................................... 446
15.2.4 Using the AES Accelerator With Low-Power Modes....................................................... 447
15.2.5 AES Accelerator Interrupts .................................................................................... 447
15.2.6 Implementing Block Cipher Modes........................................................................... 447
15.3 AES_ACCEL Registers .................................................................................................. 448
15.3.1 AESACTL0 Register............................................................................................ 449
15.3.2 AESASTAT Register ........................................................................................... 450
15.3.3 AESAKEY Register............................................................................................. 451
15.3.4 AESADIN Register ............................................................................................. 452
15.3.5 AESADOUT Register .......................................................................................... 452
16 Watchdog Timer (WDT_A).................................................................................................. 453
16.1 WDT_A Introduction...................................................................................................... 454
16.2 WDT_A Operation ........................................................................................................ 456
16.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 456
16.2.2 Watchdog Mode ................................................................................................ 456
16.2.3 Interval Timer Mode ............................................................................................ 456
16.2.4 Watchdog Timer Interrupts .................................................................................... 456
16.2.5 Clock Fail-Safe Feature........................................................................................ 457

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16.2.6 Operation in Low-Power Modes .............................................................................. 457
16.2.7 Software Examples............................................................................................. 457
16.3 WDT_A Registers......................................................................................................... 458
16.3.1 WDTCTL Register .............................................................................................. 459
17 Timer_A........................................................................................................................... 460
17.1 Timer_A Introduction ..................................................................................................... 461
17.2 Timer_A Operation ....................................................................................................... 463
17.2.1 16-Bit Timer Counter........................................................................................... 463
17.2.2 Starting the Timer............................................................................................... 463
17.2.3 Timer Mode Control ............................................................................................ 464
17.2.4 Capture/Compare Blocks...................................................................................... 467
17.2.5 Output Unit ...................................................................................................... 469
17.2.6 Timer_A Interrupts.............................................................................................. 473
17.3 Timer_A Registers........................................................................................................ 475
17.3.1 TAxCTL Register ............................................................................................... 476
17.3.2 TAxR Register................................................................................................... 477
17.3.3 TAxCCTLn Register............................................................................................ 478
17.3.4 TAxCCRn Register ............................................................................................ 480
17.3.5 TAxIV Register.................................................................................................. 480
17.3.6 TAxEX0 Register ............................................................................................... 481
18 Timer_B........................................................................................................................... 482
18.1 Timer_B Introduction ..................................................................................................... 483
18.1.1 Similarities and Differences From Timer_A ................................................................. 483
18.2 Timer_B Operation ....................................................................................................... 485
18.2.1 16-Bit Timer Counter........................................................................................... 485
18.2.2 Starting the Timer............................................................................................... 485
18.2.3 Timer Mode Control ............................................................................................ 486
18.2.4 Capture/Compare Blocks...................................................................................... 489
18.2.5 Output Unit ...................................................................................................... 492
18.2.6 Timer_B Interrupts.............................................................................................. 496
18.3 Timer_B Registers........................................................................................................ 498
18.3.1 TBxCTL Register ............................................................................................... 499
18.3.2 TBxR Register................................................................................................... 501
18.3.3 TBxCCTLn Register............................................................................................ 502
18.3.4 TBxCCRn Register ............................................................................................. 504
18.3.5 TBxIV Register.................................................................................................. 505
18.3.6 TBxEX0 Register ............................................................................................... 506
19 Timer_D........................................................................................................................... 507
19.1 Timer_D Introduction..................................................................................................... 508
19.1.1 Differences From Timer_B .................................................................................... 508
19.2 Timer_D Operation ....................................................................................................... 510
19.2.1 16-Bit Timer Counter........................................................................................... 510
19.2.2 High-Resolution Generator.................................................................................... 511
19.2.3 Starting the Timer............................................................................................... 513
19.2.4 Timer Mode Control ............................................................................................ 513
19.2.5 PWM Generation ............................................................................................... 518
19.2.6 Capture/Compare Blocks...................................................................................... 521
19.2.7 Compare Mode.................................................................................................. 524
19.2.8 Switching From Capture to Compare Mode................................................................. 525
19.2.9 Output Unit ...................................................................................................... 525
19.2.10 Synchronization Between Timer_D Instances ............................................................ 532
19.2.11 Timer_D Interrupts ............................................................................................ 532
19.3 Timer_D Registers........................................................................................................ 534

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19.3.1 TDxCTL0 Register.............................................................................................. 535
19.3.2 TDxCTL1 Register.............................................................................................. 537
19.3.3 TDxCTL2 Register.............................................................................................. 538
19.3.4 TDxR Register .................................................................................................. 539
19.3.5 TDxCCTLn Register............................................................................................ 540
19.3.6 TDxCCRn Register............................................................................................. 542
19.3.7 TDxCLn Register ............................................................................................... 542
19.3.8 TDxHCTL0 Register............................................................................................ 543
19.3.9 TDxHCTL1 Register............................................................................................ 544
19.3.10 TDxHINT Register............................................................................................. 545
19.3.11 TDxIV Register ................................................................................................ 546
20 Timer Event Control (TEC)................................................................................................. 547
20.1 Timer Event Control Introduction ....................................................................................... 548
20.2 TEC Operation ............................................................................................................ 549
20.2.1 AUXCLK Selection Sub-Block ................................................................................ 549
20.2.2 External Clear Sub-Block ..................................................................................... 549
20.2.3 Channel Event Sub-Block..................................................................................... 549
20.2.4 Module Level Connection Between TEC and Timer_D.................................................... 550
20.2.5 Synchronization Mechanism Between Timer_D Instances................................................ 552
20.2.6 Timer Event Control Interrupts................................................................................ 554
20.3 TEC Registers............................................................................................................. 555
20.3.1 TECxCTL0 Register............................................................................................ 556
20.3.2 TECxCTL1 Register............................................................................................ 558
20.3.3 TECxCTL2 Register............................................................................................ 560
20.3.4 TECxSTA Register ............................................................................................. 561
20.3.5 TECxINT Register .............................................................................................. 562
20.3.6 TECxIV Register................................................................................................ 563
21 Real-Time Clock (RTC) Overview........................................................................................ 564
21.1 RTC Overview............................................................................................................. 564
22 Real-Time Clock (RTC_A) .................................................................................................. 565
22.1 RTC_A Introduction....................................................................................................... 566
22.2 RTC_A Operation......................................................................................................... 568
22.2.1 Counter Mode................................................................................................... 568
22.2.2 Calendar Mode.................................................................................................. 568
22.2.3 Real-Time Clock Interrupts.................................................................................... 570
22.2.4 Real-Time Clock Calibration .................................................................................. 572
22.3 RTC_A Registers ......................................................................................................... 574
22.3.1 RTCCTL0 Register ............................................................................................. 576
22.3.2 RTCCTL1 Register ............................................................................................. 577
22.3.3 RTCCTL2 Register ............................................................................................. 578
22.3.4 RTCCTL3 Register ............................................................................................. 578
22.3.5 RTCNT1 Register............................................................................................... 579
22.3.6 RTCNT2 Register............................................................................................... 579
22.3.7 RTCNT3 Register............................................................................................... 579
22.3.8 RTCNT4 Register............................................................................................... 579
22.3.9 RTCSEC Register – Calendar Mode With Hexadecimal Format......................................... 580
22.3.10 RTCSEC Register – Calendar Mode With BCD Format................................................. 580
22.3.11 RTCMIN Register – Calendar Mode With Hexadecimal Format........................................ 581
22.3.12 RTCMIN Register – Calendar Mode With BCD Format.................................................. 581
22.3.13 RTCHOUR Register – Calendar Mode With Hexadecimal Format..................................... 582
22.3.14 RTCHOUR Register – Calendar Mode With BCD Format............................................... 582
22.3.15 RTCDOW Register – Calendar Mode ...................................................................... 583

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22.3.16 RTCDAY Register – Calendar Mode With Hexadecimal Format ....................................... 583
22.3.17 RTCDAY Register – Calendar Mode With BCD Format................................................. 583
22.3.18 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 584
22.3.19 RTCMON Register – Calendar Mode With BCD Format ................................................ 584
22.3.20 RTCYEARL Register – Calendar Mode With Hexadecimal Format.................................... 585
22.3.21 RTCYEARL Register – Calendar Mode With BCD Format.............................................. 585
22.3.22 RTCYEARH Register – Calendar Mode With Hexadecimal Format ................................... 586
22.3.23 RTCYEARH Register – Calendar Mode With BCD Format ............................................. 586
22.3.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format...................................... 587
22.3.25 RTCAMIN Register – Calendar Mode With BCD Format................................................ 587
22.3.26 RTCAHOUR Register – Calendar Mode With Hexadecimal Format................................... 588
22.3.27 RTCAHOUR Register – Calendar Mode With BCD Format............................................. 588
22.3.28 RTCADOW Register.......................................................................................... 589
22.3.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 589
22.3.30 RTCADAY Register – Calendar Mode With BCD Format ............................................... 590
22.3.31 RTCPS0CTL Register ........................................................................................ 591
22.3.32 RTCPS1CTL Register ........................................................................................ 592
22.3.33 RT0PS Register ............................................................................................... 593
22.3.34 RT1PS Register ............................................................................................... 593
22.3.35 RTCIV Register................................................................................................ 593
23 Real-Time Clock B (RTC_B) ............................................................................................... 594
23.1 Real-Time Clock RTC_B Introduction.................................................................................. 595
23.2 RTC_B Operation......................................................................................................... 597
23.2.1 Real-Time Clock and Prescale Dividers..................................................................... 597
23.2.2 Real-Time Clock Alarm Function ............................................................................. 597
23.2.3 Reading or Writing Real-Time Clock Registers............................................................. 598
23.2.4 Real-Time Clock Interrupts.................................................................................... 598
23.2.5 Real-Time Clock Calibration .................................................................................. 600
23.2.6 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 601
23.3 RTC_B Registers ......................................................................................................... 602
23.3.1 RTCCTL0 Register ............................................................................................. 604
23.3.2 RTCCTL1 Register ............................................................................................. 605
23.3.3 RTCCTL2 Register ............................................................................................. 606
23.3.4 RTCCTL3 Register ............................................................................................. 606
23.3.5 RTCSEC Register – Hexadecimal Format .................................................................. 607
23.3.6 RTCSEC Register – BCD Format ............................................................................ 607
23.3.7 RTCMIN Register – Hexadecimal Format................................................................... 608
23.3.8 RTCMIN Register – BCD Format............................................................................. 608
23.3.9 RTCHOUR Register – Hexadecimal Format................................................................ 609
23.3.10 RTCHOUR Register – BCD Format ........................................................................ 609
23.3.11 RTCDOW Register............................................................................................ 610
23.3.12 RTCDAY Register – Hexadecimal Format................................................................. 610
23.3.13 RTCDAY Register – BCD Format........................................................................... 610
23.3.14 RTCMON Register – Hexadecimal Format................................................................ 611
23.3.15 RTCMON Register – BCD Format.......................................................................... 611
23.3.16 RTCYEAR Register – Hexadecimal Format............................................................... 612
23.3.17 RTCYEAR Register – BCD Format......................................................................... 612
23.3.18 RTCAMIN Register – Hexadecimal Format ............................................................... 613
23.3.19 RTCAMIN Register – BCD Format ......................................................................... 613
23.3.20 RTCAHOUR Register – Hexadecimal Format ............................................................ 614
23.3.21 RTCAHOUR Register – BCD Format ...................................................................... 614
23.3.22 RTCADOW Register.......................................................................................... 615
23.3.23 RTCADAY Register – Hexadecimal Format............................................................... 616

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23.3.24 RTCADAY Register – BCD Format......................................................................... 616
23.3.25 RTCPS0CTL Register ........................................................................................ 617
23.3.26 RTCPS1CTL Register ........................................................................................ 618
23.3.27 RTCPS0 Register ............................................................................................. 619
23.3.28 RTCPS1 Register ............................................................................................. 619
23.3.29 RTCIV Register................................................................................................ 620
23.3.30 BIN2BCD Register ............................................................................................ 621
23.3.31 BCD2BIN Register ............................................................................................ 621
24 Real-Time Clock C (RTC_C) ............................................................................................... 622
24.1 Real-Time Clock (RTC_C) Introduction................................................................................ 623
24.2 RTC_C Operation......................................................................................................... 625
24.2.1 Calendar Mode.................................................................................................. 625
24.2.2 Real-Time Clock and Prescale Dividers .................................................................... 625
24.2.3 Real-Time Clock Alarm Function ............................................................................ 625
24.2.4 Real-Time Clock Protection ................................................................................... 626
24.2.5 Reading or Writing Real-Time Clock Registers............................................................ 627
24.2.6 Real-Time Clock Interrupts.................................................................................... 627
24.2.7 Real-Time Clock Calibration for Crystal Offset Error....................................................... 629
24.2.8 Real-Time Clock Compensation for Crystal Temperature Drift........................................... 630
24.2.9 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 632
24.3 RTC_C Operation - Device-Dependent Features .................................................................... 634
24.3.1 Counter Mode................................................................................................... 634
24.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp............................................. 637
24.4 RTC_C Registers......................................................................................................... 639
24.4.1 RTCCTL0_L Register .......................................................................................... 642
24.4.2 RTCCTL0_H Register.......................................................................................... 643
24.4.3 RTCCTL1 Register ............................................................................................. 644
24.4.4 RTCCTL3 Register ............................................................................................. 645
24.4.5 RTCOCAL Register ............................................................................................ 645
24.4.6 RTCTCMP Register ............................................................................................ 646
24.4.7 RTCNT1 Register............................................................................................... 647
24.4.8 RTCNT2 Register............................................................................................... 647
24.4.9 RTCNT3 Register............................................................................................... 647
24.4.10 RTCNT4 Register ............................................................................................. 647
24.4.11 RTCSEC Register – Calendar Mode With Hexadecimal Format ....................................... 648
24.4.12 RTCSEC Register – Calendar Mode With BCD Format................................................. 648
24.4.13 RTCMIN Register – Calendar Mode With Hexadecimal Format........................................ 649
24.4.14 RTCMIN Register – Calendar Mode With BCD Format.................................................. 649
24.4.15 RTCHOUR Register – Calendar Mode With Hexadecimal Format..................................... 650
24.4.16 RTCHOUR Register – Calendar Mode With BCD Format............................................... 650
24.4.17 RTCDOW Register – Calendar Mode ...................................................................... 651
24.4.18 RTCDAY Register – Calendar Mode With Hexadecimal Format ....................................... 651
24.4.19 RTCDAY Register – Calendar Mode With BCD Format................................................. 651
24.4.20 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 652
24.4.21 RTCMON Register – Calendar Mode With BCD Format ................................................ 652
24.4.22 RTCYEAR Register – Calendar Mode With Hexadecimal Format ..................................... 653
24.4.23 RTCYEAR Register – Calendar Mode With BCD Format ............................................... 653
24.4.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format...................................... 654
24.4.25 RTCAMIN Register – Calendar Mode With BCD Format................................................ 654
24.4.26 RTCAHOUR Register......................................................................................... 655
24.4.27 RTCAHOUR Register – Calendar Mode With BCD Format............................................. 655
24.4.28 RTCADOW Register – Calendar Mode .................................................................... 656
24.4.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 657

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24.4.30 RTCADAY Register – Calendar Mode With BCD Format ............................................... 657
24.4.31 RTCPS0CTL Register ........................................................................................ 658
24.4.32 RTCPS1CTL Register ........................................................................................ 659
24.4.33 RTCPS0 Register ............................................................................................. 661
24.4.34 RTCPS1 Register ............................................................................................. 661
24.4.35 RTCIV Register................................................................................................ 662
24.4.36 BIN2BCD Register ............................................................................................ 663
24.4.37 BCD2BIN Register ............................................................................................ 663
24.4.38 RTCSECBAKx Register – Hexadecimal Format.......................................................... 664
24.4.39 RTCSECBAKx Register – BCD Format.................................................................... 664
24.4.40 RTCMINBAKx Register – Hexadecimal Format........................................................... 665
24.4.41 RTCMINBAKx Register – BCD Format .................................................................... 665
24.4.42 RTCHOURBAKx Register – Hexadecimal Format........................................................ 666
24.4.43 RTCHOURBAKx Register – BCD Format ................................................................. 666
24.4.44 RTCDAYBAKx Register – Hexadecimal Format.......................................................... 667
24.4.45 RTCDAYBAKx Register – BCD Format.................................................................... 667
24.4.46 RTCMONBAKx Register – Hexadecimal Format ......................................................... 668
24.4.47 RTCMONBAKx Register – BCD Format ................................................................... 668
24.4.48 RTCYEARBAKx Register – Hexadecimal Format ........................................................ 669
24.4.49 RTCYEARBAKx Register – BCD Format.................................................................. 669
24.4.50 RTCTCCTL0 Register ........................................................................................ 670
24.4.51 RTCTCCTL1 Register ........................................................................................ 670
24.4.52 RTCCAPxCTL Register ...................................................................................... 671
25 32-Bit Hardware Multiplier (MPY32)..................................................................................... 672
25.1 32-Bit Hardware Multiplier (MPY32) Introduction..................................................................... 673
25.2 MPY32 Operation......................................................................................................... 675
25.2.1 Operand Registers ............................................................................................. 676
25.2.2 Result Registers ................................................................................................ 677
25.2.3 Software Examples............................................................................................. 678
25.2.4 Fractional Numbers............................................................................................. 679
25.2.5 Putting It All Together.......................................................................................... 682
25.2.6 Indirect Addressing of Result Registers ..................................................................... 685
25.2.7 Using Interrupts................................................................................................. 685
25.2.8 Using DMA ...................................................................................................... 686
25.3 MPY32 Registers ......................................................................................................... 687
25.3.1 MPY32CTL0 Register.......................................................................................... 689
26 REF................................................................................................................................. 690
26.1 REF Introduction.......................................................................................................... 691
26.2 Principle of Operation .................................................................................................... 694
26.2.1 Low-Power Operation.......................................................................................... 695
26.2.2 REFCTL.......................................................................................................... 695
26.2.3 Reference System Requests.................................................................................. 697
26.3 REF Registers............................................................................................................. 700
26.3.1 REFCTL0 Register (offset = 00h) [reset = 0080h] ......................................................... 701
27 ADC10_A ......................................................................................................................... 703
27.1 ADC10_A Introduction ................................................................................................... 704
27.2 ADC10_A Operation...................................................................................................... 706
27.2.1 10-Bit ADC Core................................................................................................ 706
27.2.2 ADC10_A Inputs and Multiplexer............................................................................. 706
27.2.3 Voltage Reference Generator................................................................................. 707
27.2.4 Auto Power Down .............................................................................................. 707
27.2.5 Sample and Conversion Timing .............................................................................. 707
27.2.6 Conversion Result.............................................................................................. 709

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27.2.7 ADC10_A Conversion Modes................................................................................. 709
27.2.8 Window Comparator ........................................................................................... 714
27.2.9 Using the Integrated Temperature Sensor .................................................................. 715
27.2.10 ADC10_A Grounding and Noise Considerations ......................................................... 716
27.2.11 ADC10_A Interrupts .......................................................................................... 716
27.3 ADC10_A Registers...................................................................................................... 718
27.3.1 ADC10CTL0 Register.......................................................................................... 719
27.3.2 ADC10CTL1 Register.......................................................................................... 720
27.3.3 ADC10CTL2 Register.......................................................................................... 722
27.3.4 ADC10MEM0 Register......................................................................................... 723
27.3.5 ADC10MEM0 Register, Twos-Complement Format ....................................................... 723
27.3.6 ADC10MCTL0 Register........................................................................................ 724
27.3.7 ADC10HI Register.............................................................................................. 725
27.3.8 ADC10HI Register, Twos-Complement Format ............................................................ 725
27.3.9 ADC10LO Register............................................................................................. 726
27.3.10 ADC10LO Register, Twos-Complement Format.......................................................... 726
27.3.11 ADC10IE Register............................................................................................. 727
27.3.12 ADC10IFG Register........................................................................................... 728
27.3.13 ADC10IV Register............................................................................................. 729
28 ADC12_A ......................................................................................................................... 730
28.1 ADC12_A Introduction ................................................................................................... 731
28.2 ADC12_A Operation...................................................................................................... 734
28.2.1 12-Bit ADC Core................................................................................................ 734
28.2.2 ADC12_A Inputs and Multiplexer............................................................................. 734
28.2.3 Voltage Reference Generator................................................................................. 735
28.2.4 Auto Power Down .............................................................................................. 736
28.2.5 Sample and Conversion Timing .............................................................................. 736
28.2.6 Conversion Memory............................................................................................ 738
28.2.7 ADC12_A Conversion Modes................................................................................. 738
28.2.8 Using the Integrated Temperature Sensor .................................................................. 744
28.2.9 ADC12_A Grounding and Noise Considerations........................................................... 745
28.2.10 ADC12_A Interrupts .......................................................................................... 746
28.3 ADC12_A Registers...................................................................................................... 748
28.3.1 ADC12CTL0 Register.......................................................................................... 750
28.3.2 ADC12CTL1 Register.......................................................................................... 752
28.3.3 ADC12CTL2 Register.......................................................................................... 753
28.3.4 ADC12MEMx Register......................................................................................... 754
28.3.5 ADC12MCTLx Register........................................................................................ 755
28.3.6 ADC12IE Register.............................................................................................. 756
28.3.7 ADC12IFG Register ............................................................................................ 758
28.3.8 ADC12IV Register.............................................................................................. 760
29 SD24_B ........................................................................................................................... 761
29.1 SD24_B Introduction ..................................................................................................... 762
29.2 SD24_B Operation........................................................................................................ 766
29.2.1 Principle of Operation .......................................................................................... 766
29.2.2 ADC Core........................................................................................................ 766
29.2.3 Voltage Reference.............................................................................................. 767
29.2.4 Modulator Clock................................................................................................. 767
29.2.5 Auto Power-Down .............................................................................................. 767
29.2.6 Analog Inputs.................................................................................................... 767
29.2.7 Digital Filter ..................................................................................................... 768
29.2.8 Bitstream Input and Output.................................................................................... 772
29.2.9 Conversion Modes.............................................................................................. 772

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29.2.10 Conversion Operation Using Preload....................................................................... 774
29.2.11 Grounding and Noise Considerations ...................................................................... 775
29.2.12 Trigger Generator ............................................................................................. 776
29.2.13 SD24_B Interrupts ............................................................................................ 777
29.2.14 Using SD24_B With DMA.................................................................................... 777
29.3 SD24_B Registers........................................................................................................ 778
29.3.1 SD24BCTL0 Register .......................................................................................... 780
29.3.2 SD24BCTL1 Register .......................................................................................... 781
29.3.3 SD24BTRGCTL Register...................................................................................... 782
29.3.4 SD24BIFG Register ............................................................................................ 783
29.3.5 SD24BIE Register .............................................................................................. 786
29.3.6 SD24BIV Register .............................................................................................. 788
29.3.7 SD24BCCTLx Register ........................................................................................ 789
29.3.8 SD24BINCTLx Register........................................................................................ 791
29.3.9 SD24BOSRx Register.......................................................................................... 792
29.3.10 SD24BTRGOSR Register.................................................................................... 792
29.3.11 SD24BPREx Register ........................................................................................ 793
29.3.12 SD24BTRGPRE Register.................................................................................... 793
29.3.13 SD24BMEMLx Register ...................................................................................... 794
29.3.14 SD24BMEMHx Register...................................................................................... 794
30 CTSD16 ........................................................................................................................... 795
30.1 CTSD16 Introduction..................................................................................................... 796
30.2 CTSD16 Operation ....................................................................................................... 798
30.2.1 Principle of Operation .......................................................................................... 798
30.2.2 ADC Core........................................................................................................ 798
30.2.3 Voltage Reference.............................................................................................. 799
30.2.4 CTSD16 Clock .................................................................................................. 799
30.2.5 Automatic Power Down........................................................................................ 799
30.2.6 Analog Inputs.................................................................................................... 800
30.2.7 Digital Filter...................................................................................................... 801
30.2.8 Conversion Memory Registers: CTSD16MEMx ............................................................ 804
30.2.9 Conversion Modes.............................................................................................. 805
30.2.10 Conversion Operation Using Preload....................................................................... 807
30.2.11 Using the Integrated Temperature Sensor................................................................. 808
30.2.12 Using the Integrated AVCC Sense.......................................................................... 809
30.2.13 Grounding and Noise Considerations ...................................................................... 809
30.2.14 Interrupt Handling ............................................................................................. 809
30.3 CTSD16 Registers........................................................................................................ 811
30.3.1 CTSD16CTL Register.......................................................................................... 812
30.3.2 CTSD16CCTL0 to CTSD16CCTL6 Register................................................................ 813
30.3.3 CTSD16MEM0 to CTSD16MEM6 Register ................................................................. 814
30.3.4 CTSD16INCTL0 to CTSD16INCTL6 Register .............................................................. 815
30.3.5 CTSD16PRE0 to CTSD16PRE6 Register................................................................... 816
30.3.6 CTSD16IFG Register .......................................................................................... 817
30.3.7 CTSD16IE Register ............................................................................................ 819
30.3.8 CTSD16IV Register ............................................................................................ 821
31 DAC12_A ......................................................................................................................... 822
31.1 DAC12_A Introduction ................................................................................................... 823
31.2 DAC12_A Operation...................................................................................................... 826
31.2.1 DAC12_A Core.................................................................................................. 826
31.2.2 DAC12_A Port Selection....................................................................................... 826
31.2.3 DAC12_A Reference........................................................................................... 826
31.2.4 Updating the DAC12_A Voltage Output ..................................................................... 827

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31.2.5 DAC12_xDAT Data Formats.................................................................................. 827
31.2.6 DAC12_A Output Amplifier Offset Calibration .............................................................. 828
31.2.7 Grouping Multiple DAC12_A Modules ....................................................................... 829
31.2.8 DAC12_A Interrupts............................................................................................ 830
31.3 DAC Outputs .............................................................................................................. 831
31.4 DAC12_A Registers...................................................................................................... 832
31.4.1 DAC12_xCTL0 Register ....................................................................................... 833
31.4.2 DAC12_xCTL1 Register ....................................................................................... 835
31.4.3 DAC12_xDAT Register, Unsigned 12-Bit Binary Format, Right Justified ............................... 836
31.4.4 DAC12_xDAT Register, Unsigned 12-Bit Binary Format, Left Justified................................. 836
31.4.5 DAC12_xDAT Register, Twos-Complement 12-Bit Binary Format, Right Justified.................... 837
31.4.6 DAC12_xDAT Register, Twos-Complement 12-Bit Binary Format, Left Justified...................... 837
31.4.7 DAC12_xDAT Register, Unsigned 8-Bit Binary Format, Right Justified................................. 838
31.4.8 DAC12_xDAT Register, Unsigned 8-Bit Binary Format, Left Justified................................... 838
31.4.9 DAC12_xDAT Register, Twos-Complement 8-Bit Binary Format, Right Justified ..................... 839
31.4.10 DAC12_xDAT Register, Twos-Complement 8-Bit Binary Format, Left Justified...................... 839
31.4.11 DAC12_xCALCTL Register.................................................................................. 840
31.4.12 DAC12_xCALDAT Register.................................................................................. 840
31.4.13 DAC12IV Register............................................................................................. 841
32 Comparator B (Comp_B) ................................................................................................... 842
32.1 Comp_B Introduction..................................................................................................... 843
32.2 Comp_B Operation ....................................................................................................... 844
32.2.1 Comparator...................................................................................................... 844
32.2.2 Analog Input Switches ......................................................................................... 844
32.2.3 Port Logic........................................................................................................ 844
32.2.4 Input Short Switch .............................................................................................. 844
32.2.5 Output Filter ..................................................................................................... 845
32.2.6 Reference Voltage Generator................................................................................. 846
32.2.7 Comp_B Port Disable Register CBCTL3 .................................................................... 847
32.2.8 Comp_B Interrupts ............................................................................................. 847
32.2.9 Comp_B Used to Measure Resistive Elements ............................................................ 847
32.3 Comp_B Registers........................................................................................................ 850
32.3.1 CBCTL0 Register............................................................................................... 851
32.3.2 CBCTL1 Register............................................................................................... 852
32.3.3 CBCTL2 Register............................................................................................... 853
32.3.4 CBCTL3 Register............................................................................................... 854
32.3.5 CBINT Register ................................................................................................. 856
32.3.6 CBIV Register................................................................................................... 857
33 Operational Amplifier (OA)................................................................................................. 858
33.1 OA Introduction ........................................................................................................... 859
33.2 OA Operation.............................................................................................................. 861
33.2.1 OA Modes ....................................................................................................... 861
33.2.2 Rail-to-Rail Input Modes ....................................................................................... 861
33.2.3 OA Inputs ........................................................................................................ 861
33.3 Ground Switches.......................................................................................................... 862
33.4 OA and Power Modes.................................................................................................... 862
33.5 OA Registers .............................................................................................................. 863
33.5.1 OAnCTL0 Register ............................................................................................. 864
33.5.2 OAnPSW Register.............................................................................................. 865
33.5.3 OAnNSW Register.............................................................................................. 866
33.5.4 OAnGSW Register ............................................................................................. 867
34 LCD_B Controller.............................................................................................................. 868

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34.1 LCD_B Controller Introduction .......................................................................................... 869
34.2 LCD_B Controller Operation ............................................................................................ 871
34.2.1 LCD Memory .................................................................................................... 871
34.2.2 LCD Timing Generation........................................................................................ 871
34.2.3 Blanking the LCD............................................................................................... 872
34.2.4 LCD Blinking..................................................................................................... 872
34.2.5 LCD_B Voltage And Bias Generation........................................................................ 873
34.2.6 LCD Outputs..................................................................................................... 875
34.2.7 LCD_B Interrupts ............................................................................................... 875
34.2.8 Static Mode...................................................................................................... 877
34.2.9 2-Mux Mode ..................................................................................................... 880
34.2.10 3-Mux Mode.................................................................................................... 883
34.2.11 4-Mux Mode.................................................................................................... 886
34.3 LCD_B Registers ......................................................................................................... 889
34.3.1 LCDBCTL0 Register............................................................................................ 892
34.3.2 LCDBCTL1 Register............................................................................................ 893
34.3.3 LCDBBLKCTL Register........................................................................................ 894
34.3.4 LCDBMEMCTL Register....................................................................................... 895
34.3.5 LCDBVCTL Register ........................................................................................... 896
34.3.6 LCDBPCTL0 Register.......................................................................................... 898
34.3.7 LCDBPCTL1 Register.......................................................................................... 898
34.3.8 LCDBPCTL2 Register.......................................................................................... 899
34.3.9 LCDBPCTL3 Register.......................................................................................... 899
34.3.10 LCDBCPCTL Register........................................................................................ 900
34.3.11 LCDBIV Register .............................................................................................. 901
35 LCD_C Controller.............................................................................................................. 902
35.1 LCD_C Introduction....................................................................................................... 903
35.2 LCD_C Operation......................................................................................................... 905
35.2.1 LCD Memory .................................................................................................... 905
35.2.2 LCD Timing Generation........................................................................................ 906
35.2.3 Blanking the LCD............................................................................................... 907
35.2.4 LCD Blinking..................................................................................................... 907
35.2.5 LCD Voltage And Bias Generation........................................................................... 908
35.2.6 LCD Outputs..................................................................................................... 911
35.2.7 LCD Interrupts................................................................................................... 912
35.2.8 Static Mode...................................................................................................... 914
35.2.9 2-Mux Mode ..................................................................................................... 915
35.2.10 3-Mux Mode.................................................................................................... 916
35.2.11 4-Mux Mode.................................................................................................... 917
35.2.12 6-Mux Mode.................................................................................................... 918
35.2.13 8-Mux Mode.................................................................................................... 919
35.3 LCD_C Registers ......................................................................................................... 921
35.3.1 LCDCCTL0 Register ........................................................................................... 926
35.3.2 LCDCCTL1 Register ........................................................................................... 928
35.3.3 LCDCBLKCTL Register........................................................................................ 929
35.3.4 LCDCMEMCTL Register....................................................................................... 930
35.3.5 LCDCVCTL Register ........................................................................................... 931
35.3.6 LCDCPCTL0 Register.......................................................................................... 933
35.3.7 LCDCPCTL1 Register.......................................................................................... 933
35.3.8 LCDCPCTL2 Register.......................................................................................... 934
35.3.9 LCDCPCTL3 Register.......................................................................................... 934
35.3.10 LCDCCPCTL Register........................................................................................ 935
35.3.11 LCDCIV Register.............................................................................................. 935

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36 Universal Serial Communication Interface – UART Mode....................................................... 936
36.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 937
36.2 USCI Introduction – UART Mode....................................................................................... 938
36.3 USCI Operation – UART Mode ......................................................................................... 940
36.3.1 USCI Initialization and Reset.................................................................................. 940
36.3.2 Character Format............................................................................................... 940
36.3.3 Asynchronous Communication Format ...................................................................... 940
36.3.4 Automatic Baud-Rate Detection .............................................................................. 943
36.3.5 IrDA Encoding and Decoding ................................................................................. 945
36.3.6 Automatic Error Detection ..................................................................................... 946
36.3.7 USCI Receive Enable.......................................................................................... 947
36.3.8 USCI Transmit Enable ......................................................................................... 947
36.3.9 UART Baud-Rate Generation................................................................................. 948
36.3.10 Setting a Baud Rate .......................................................................................... 950
36.3.11 Transmit Bit Timing ........................................................................................... 950
36.3.12 Receive Bit Timing ............................................................................................ 951
36.3.13 Typical Baud Rates and Errors.............................................................................. 952
36.3.14 Using the USCI Module in UART Mode With Low-Power Modes ...................................... 955
36.3.15 USCI Interrupts in UART Mode ............................................................................. 955
36.3.16 DMA Operation................................................................................................ 956
36.4 USCI_A UART Mode Registers......................................................................................... 957
36.4.1 UCAxCTL0 Register............................................................................................ 958
36.4.2 UCAxCTL1 Register............................................................................................ 959
36.4.3 UCAxBR0 Register............................................................................................. 960
36.4.4 UCAxBR1 Register............................................................................................. 960
36.4.5 UCAxMCTL Register........................................................................................... 960
36.4.6 UCAxSTAT Register ........................................................................................... 961
36.4.7 UCAxRXBUF Register ......................................................................................... 962
36.4.8 UCAxTXBUF Register ......................................................................................... 962
36.4.9 UCAxIRTCTL Register......................................................................................... 963
36.4.10 UCAxIRRCTL Register....................................................................................... 963
36.4.11 UCAxABCTL Register ........................................................................................ 964
36.4.12 UCAxIE Register .............................................................................................. 965
36.4.13 UCAxIFG Register ............................................................................................ 965
36.4.14 UCAxIV Register .............................................................................................. 966
37 Universal Serial Communication Interface – SPI Mode .......................................................... 967
37.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 968
37.2 USCI Introduction – SPI Mode.......................................................................................... 969
37.3 USCI Operation – SPI Mode ............................................................................................ 971
37.3.1 USCI Initialization and Reset.................................................................................. 971
37.3.2 Character Format............................................................................................... 971
37.3.3 Master Mode .................................................................................................... 972
37.3.4 Slave Mode...................................................................................................... 973
37.3.5 SPI Enable....................................................................................................... 974
37.3.6 Serial Clock Control ............................................................................................ 974
37.3.7 Using the SPI Mode With Low-Power Modes............................................................... 975
37.3.8 USCI Interrupts in SPI Mode.................................................................................. 976
37.4 USCI_A SPI Mode Registers............................................................................................ 977
37.4.1 UCAxCTL0 Register............................................................................................ 978
37.4.2 UCAxCTL1 Register............................................................................................ 979
37.4.3 UCAxBR0 Register............................................................................................. 980
37.4.4 UCAxBR1 Register............................................................................................. 980
37.4.5 UCAxMCTL Register........................................................................................... 980

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37.4.6 UCAxSTAT Register ........................................................................................... 981
37.4.7 UCAxRXBUF Register ......................................................................................... 982
37.4.8 UCAxTXBUF Register ......................................................................................... 982
37.4.9 UCAxIE Register................................................................................................ 983
37.4.10 UCAxIFG Register ............................................................................................ 983
37.4.11 UCAxIV Register .............................................................................................. 984
37.5 USCI_B SPI Mode Registers............................................................................................ 985
37.5.1 UCBxCTL0 Register............................................................................................ 986
37.5.2 UCBxCTL1 Register............................................................................................ 987
37.5.3 UCBxBR0 Register............................................................................................. 988
37.5.4 UCBxBR1 Register............................................................................................. 988
37.5.5 UCBxMCTL Register........................................................................................... 988
37.5.6 UCBxSTAT Register ........................................................................................... 989
37.5.7 UCBxRXBUF Register ......................................................................................... 990
37.5.8 UCBxTXBUF Register ......................................................................................... 990
37.5.9 UCBxIE Register................................................................................................ 991
37.5.10 UCBxIFG Register ............................................................................................ 991
37.5.11 UCBxIV Register .............................................................................................. 992
38 Universal Serial Communication Interface – I2C Mode........................................................... 993
38.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 994
38.2 USCI Introduction – I2C Mode........................................................................................... 995
38.3 USCI Operation – I2C Mode............................................................................................. 996
38.3.1 USCI Initialization and Reset.................................................................................. 997
38.3.2 I2C Serial Data .................................................................................................. 997
38.3.3 I2C Addressing Modes ......................................................................................... 999
38.3.4 I2C Module Operating Modes................................................................................ 1000
38.3.5 I2C Clock Generation and Synchronization ................................................................ 1011
38.3.6 Using the USCI Module in I2C Mode With Low-Power Modes .......................................... 1012
38.3.7 USCI Interrupts in I2C Mode ................................................................................. 1012
38.4 USCI_B I2C Mode Registers .......................................................................................... 1015
38.4.1 UCBxCTL0 Register .......................................................................................... 1016
38.4.2 UCBxCTL1 Register .......................................................................................... 1017
38.4.3 UCBxBR0 Register............................................................................................ 1018
38.4.4 UCBxBR1 Register............................................................................................ 1018
38.4.5 UCBxSTAT Register.......................................................................................... 1019
38.4.6 UCBxRXBUF Register........................................................................................ 1020
38.4.7 UCBxTXBUF Register........................................................................................ 1020
38.4.8 UCBxI2COA Register......................................................................................... 1021
38.4.9 UCBxI2CSA Register......................................................................................... 1021
38.4.10 UCBxIE Register............................................................................................. 1022
38.4.11 UCBxIFG Register........................................................................................... 1023
38.4.12 UCBxIV Register............................................................................................. 1024
39 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode .......................... 1025
39.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview ................................. 1026
39.2 eUSCI_A Introduction – UART Mode................................................................................. 1026
39.3 eUSCI_A Operation – UART Mode................................................................................... 1028
39.3.1 eUSCI_A Initialization and Reset ........................................................................... 1028
39.3.2 Character Format ............................................................................................. 1028
39.3.3 Asynchronous Communication Format..................................................................... 1028
39.3.4 Automatic Baud-Rate Detection............................................................................. 1031
39.3.5 IrDA Encoding and Decoding................................................................................ 1032
39.3.6 Automatic Error Detection.................................................................................... 1033
39.3.7 eUSCI_A Receive Enable.................................................................................... 1034

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39.3.8 eUSCI_A Transmit Enable................................................................................... 1034
39.3.9 UART Baud-Rate Generation ............................................................................... 1035
39.3.10 Setting a Baud Rate......................................................................................... 1037
39.3.11 Transmit Bit Timing - Error calculation.................................................................... 1038
39.3.12 Receive Bit Timing – Error Calculation ................................................................... 1038
39.3.13 Typical Baud Rates and Errors ............................................................................ 1039
39.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes................................ 1041
39.3.15 eUSCI_A Interrupts in UART Mode ....................................................................... 1042
39.3.16 DMA Operation............................................................................................... 1043
39.4 eUSCI_A UART Registers ............................................................................................. 1044
39.4.1 UCAxCTLW0 Register........................................................................................ 1045
39.4.2 UCAxCTLW1 Register........................................................................................ 1046
39.4.3 UCAxBRW Register........................................................................................... 1047
39.4.4 UCAxMCTLW Register....................................................................................... 1047
39.4.5 UCAxSTATW Register ....................................................................................... 1048
39.4.6 UCAxRXBUF Register........................................................................................ 1049
39.4.7 UCAxTXBUF Register........................................................................................ 1049
39.4.8 UCAxABCTL Register ........................................................................................ 1050
39.4.9 UCAxIRCTL Register......................................................................................... 1051
39.4.10 UCAxIE Register............................................................................................. 1052
39.4.11 UCAxIFG Register........................................................................................... 1053
39.4.12 UCAxIV Register............................................................................................. 1054
40 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode.............................. 1055
40.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview...................... 1056
40.2 eUSCI Introduction – SPI Mode....................................................................................... 1056
40.3 eUSCI Operation – SPI Mode ......................................................................................... 1058
40.3.1 eUSCI Initialization and Reset............................................................................... 1058
40.3.2 Character Format ............................................................................................. 1059
40.3.3 Master Mode................................................................................................... 1059
40.3.4 Slave Mode .................................................................................................... 1060
40.3.5 SPI Enable ..................................................................................................... 1061
40.3.6 Serial Clock Control........................................................................................... 1061
40.3.7 Using the SPI Mode With Low-Power Modes ............................................................. 1062
40.3.8 eUSCI Interrupts in SPI Mode............................................................................... 1062
40.4 eUSCI_A SPI Registers ................................................................................................ 1064
40.4.1 UCAxCTLW0 Register........................................................................................ 1065
40.4.2 UCAxBRW Register........................................................................................... 1066
40.4.3 UCAxSTATW Register ....................................................................................... 1067
40.4.4 UCAxRXBUF Register........................................................................................ 1068
40.4.5 UCAxTXBUF Register........................................................................................ 1069
40.4.6 UCAxIE Register .............................................................................................. 1070
40.4.7 UCAxIFG Register ............................................................................................ 1071
40.4.8 UCAxIV Register .............................................................................................. 1072
40.5 eUSCI_B SPI Registers ................................................................................................ 1073
40.5.1 UCBxCTLW0 Register........................................................................................ 1074
40.5.2 UCBxBRW Register........................................................................................... 1075
40.5.3 UCBxSTATW Register ....................................................................................... 1075
40.5.4 UCBxRXBUF Register........................................................................................ 1076
40.5.5 UCBxTXBUF Register........................................................................................ 1076
40.5.6 UCBxIE Register ............................................................................................. 1077
40.5.7 UCBxIFG Register ............................................................................................ 1077
40.5.8 UCBxIV Register .............................................................................................. 1078
41 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode .............................. 1079

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Contents
41.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview ................................. 1080
41.2 eUSCI_B Introduction – I2C Mode .................................................................................... 1080
41.3 eUSCI_B Operation – I2C Mode....................................................................................... 1081
41.3.1 eUSCI_B Initialization and Reset ........................................................................... 1082
41.3.2 I2C Serial Data................................................................................................. 1082
41.3.3 I2C Addressing Modes........................................................................................ 1083
41.3.4 I2C Quick Setup................................................................................................ 1084
41.3.5 I2C Module Operating Modes................................................................................ 1085
41.3.6 Glitch Filtering ................................................................................................. 1095
41.3.7 I2C Clock Generation and Synchronization ................................................................ 1095
41.3.8 Byte Counter .................................................................................................. 1097
41.3.9 Multiple Slave Addresses .................................................................................... 1097
41.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes.................................... 1098
41.3.11 eUSCI_B Interrupts in I2C Mode........................................................................... 1098
41.4 eUSCI_B I2C Registers ................................................................................................ 1102
41.4.1 UCBxCTLW0 Register........................................................................................ 1103
41.4.2 UCBxCTLW1 Register........................................................................................ 1105
41.4.3 UCBxBRW Register........................................................................................... 1107
41.4.4 UCBxSTATW .................................................................................................. 1107
41.4.5 UCBxTBCNT Register........................................................................................ 1108
41.4.6 UCBxRXBUF Register........................................................................................ 1109
41.4.7 UCBxTXBUF................................................................................................... 1109
41.4.8 UCBxI2COA0 Register ....................................................................................... 1110
41.4.9 UCBxI2COA1 Register ....................................................................................... 1111
41.4.10 UCBxI2COA2 Register...................................................................................... 1111
41.4.11 UCBxI2COA3 Register...................................................................................... 1112
41.4.12 UCBxADDRX Register...................................................................................... 1112
41.4.13 UCBxADDMASK Register.................................................................................. 1113
41.4.14 UCBxI2CSA Register ....................................................................................... 1113
41.4.15 UCBxIE Register............................................................................................. 1114
41.4.16 UCBxIFG Register........................................................................................... 1116
41.4.17 UCBxIV Register............................................................................................. 1118
42 USB Module ................................................................................................................... 1119
42.1 USB Introduction ........................................................................................................ 1120
42.2 USB Operation........................................................................................................... 1122
42.2.1 USB Transceiver (PHY)...................................................................................... 1122
42.2.2 USB Power System........................................................................................... 1123
42.2.3 USB Phase-Locked Loop (PLL)............................................................................. 1126
42.2.4 USB Controller Engine ....................................................................................... 1128
42.2.5 USB Vector Interrupts ........................................................................................ 1132
42.2.6 Power Consumption .......................................................................................... 1132
42.2.7 Suspend and Resume ....................................................................................... 1133
42.3 USB Transfers........................................................................................................... 1133
42.3.1 Control Transfers.............................................................................................. 1133
42.3.2 Interrupt Transfers ............................................................................................ 1137
42.3.3 Bulk Transfers ................................................................................................. 1138
42.4 USB Registers........................................................................................................... 1140
42.4.1 USB Configuration Registers................................................................................ 1140
42.4.2 USB Control Registers ....................................................................................... 1148
42.4.3 USB Buffer Registers and Memory ......................................................................... 1165
43 LDO-PWR Module ........................................................................................................... 1176
43.1 LDO-PWR Introduction ................................................................................................. 1177
43.2 LDO-PWR Operation ................................................................................................... 1178