Epson S1R72V17 Instruction Manual

Rev. 1.0
S1R72V17
CPU Connection Guide

NOTICE
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©SEIKO EPSON CORPORATION 2008, All rights reserved.

Scope
This document applies to the S1R72V17 USB2.0 host/device controller LSI.

S1R72V17 CPU Connection Guide EPSON i
(Rev. 1.0)
Table of Contents
1. Introduction....................................................................................................................................... 1
1.1 Overview..................................................................................................................................... 1
1.2 Related Documents .................................................................................................................... 1
2. Connection Example with Standard CPU ....................................................................................... 2
3. Endian Settings for 16-bit Bus Width Connection ......................................................................... 4
3.1 Connection to Big-endian CPU................................................................................................... 4
3.2 Connection to Little-endian CPU ................................................................................................ 7
4. CPUIF Verification Procedure ........................................................................................................ 10
5. Connection Example with FreeScale iMX21 ................................................................................. 14
5.1 Connection Example ................................................................................................................ 14
5.2 iMX21 Bus Cycle Setting Example ........................................................................................... 16
5.3 Checking S1R72V17 AC Spec and iMX21 Bus Cycle .............................................................. 18

1. Introduction
S1R72V17 CPU Connection Guide EPSON 1
(Rev. 1.0)
1. Introduction
1.1 Overview
This document contains information required for actual use of the S1R72V17 by the customer,
focusing on the details necessary to connect the S1R72V17 to the control CPU.
This document describes typical connection methods. No guarantees are made regarding the
suitability of these methods. The connection methods must be modified to suit specific customer
system configurations.
The contents of this document are subject to change without notice.
1.2 Related Documents
•S1R72V17 Technical Manual (Hardware Specifications)

2. Connection Example with Standard CPU
2 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
2. Connection Example with Standard CPU
This section illustrates a typical connection with a standard CPU.
1) 16-bit bus, Strobe mode connection example
Set CPU_Config register (0x075h address) BusMode bit to “0” and Bus8x16 bit to “0.”
16bit Strobe mode
CPU S1R72V17
IOVDD CVDD
Address[8:1] CA[8:1]
XBEL(CA[0])
DATA[15:0] CD[15:0]
XCS XCS
XRD XRD
XWRH XWRH(XBEH)
XWRL XWRL(XWR)
XDREQ
X
DREQ *1
XDACK
X
DACK *2
XINT
X
INT
<When DMA is not used>
*1: Open
*2: Fixed at High or Low
1.65 V to 3.6 V
Fig. 2-1 16-bit bus, Strobe mode connection example

2. Connection Example with Standard CPU
S1R72V17 CPU Connection Guide EPSON 3
(Rev. 1.0)
2) 16-bit bus, BE mode connection example
Set CPU_Config register (0x075h address) BusMode bit to “1” and Bus8x16 bit to “0.”
16bit BE mode
CPU S1R72V17
IOVDD CVDD
Address[8:1] CA[8:1]
XBEL XBEL(CA[0])
DATA[15:0] CD[15:0]
XCS XCS
XRD XRD
XBEH XWRH(XBEH)
XWR XWRL(XWR)
XDREQ
X
DREQ *1
XDACK
X
DACK *2
XINT
X
INT
<When DMA is not used>
*1: Open
*2: Fixed at High or Low
1.65 V to 3.6 V
Fig. 2-2 16-bit bus, BE mode connection example
3) 8-bit bus mode connection example
Set CPU_Config register (0x075h address) BusMode bit to “0” and Bus8x16 bit to “1.”
8bit mode
CPU S1R72V17
IOVDD CVDD
Address[8:1] CA[8:1]
Address[0] XBEL(CA[0])
CD[15:8]
DATA[7:0] CD[7:0]
XCS XCS
XRD XRD
XWRH(XBEH)
XWR XWRL(XWR)
XDREQ
X
DREQ *1
XDACK
X
DACK *2
XINT
X
INT
<When DMA is not used>
*1: Open
*2: Fixed at High or Low
1.65 V to 3.6 V
Fig. 2-3 8-bit bus mode connection example

3. Endian Settings for 16-bit Bus Width Connection
4 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
3. Endian Settings for 16-bit Bus Width Connection
This section describes endian settings when connecting to a CPU with a 16-bit bus width.
The discussion of the S1R72V17 registers divides them into the following three types. For register details,
refer to the S1R72V17 Technical Manual.
1) Word register: Registers with _H/_L/_HH/_HL/_LH/_LL at the end of the register name
2) Byte register: Registers not corresponding to Word or FIFO registers
3) FIFO register: RAM_Rd_00 to _1F/RAM_WrDoor_0,1/FIFO_Rd_0,1/FIFO_Wr_0,1/
FIFO_ByteRd registers
3.1 Connection to Big-endian CPU
Access is normally in the mode with “0” set in the CPU_Config register (0x075h address)
CPU_Endian bit.
1) Access to Word register
The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0]
bus to the last byte of the Word register.
The example below illustrates the writing and reading of 0x1234h data to/from the Word register.
Writing: The data (12h) in the CPU memory even-number address is saved to the first byte
of the S1R72V17 Word register.
Reading: The first byte data (12h) of the S1R72V17 Word register is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
12h
Even-number address
34h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
12h 34h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
12h 34h V17 Word register
Higher byte [15:8] Lower byte [7:0]
_H, _HH, _LH registers _L, _HL, _LL registers
Fig. 3-1 Access to Word registers (big-endian CPU)

3. Endian Settings for 16-bit Bus Width Connection
S1R72V17 CPU Connection Guide EPSON 5
(Rev. 1.0)
2) Access to Byte register
The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus
to the odd-number address register when the CPU_Endian bit is set to “0.”
The example below illustrates the writing and reading of F1h to/from the Byte register
even-number address register and of F2h to/from the Byte register odd-number address register.
Writing: The data (F1h) in the CPU memory even-number address is saved to the
S1R72V17 even-number address register.
Reading: The S1R72V17 even-number address register data (F1h) is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
F1h
Even-number address
F2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
F1h F2h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
F2h F1h V17 Byte register
Odd-number address Even-number address
re
g
ister register
Fig. 3-2 Access to Byte registers (big-endian CPU)

3. Endian Settings for 16-bit Bus Width Connection
6 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
3) Access to FIFO register
The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus
to the odd-number address register when the CPU_Endian bit is set to “0.”
The example below illustrates transmission from the USB bus in the sequence C1h/C2h and
receiving in the sequence C1h/C2h.
Writing: The data (C1h) in the CPU memory even-number address is sent from the USB
bus as the first data.
Reading: The first data received from the USB bus (C1h) is saved to the even-number
address in CPU memory.
CPU
Data
・・・・
・・・・
C1h
Even-number address
C2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
C1h C2h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
C2h C1h V17 Byte register
Odd-number address Even-number address
re
g
ister register
Data[15:8] Data[7:0]
・・・・ ・・・・ V17 FIFO data
・・・・ ・・・・
(2) C2h (1) C1h Sent via USB bus in order (1), (2).
(4) ・・・・ (3) ・・・・
・・・・ ・・・・
・・・・ ・・・・
Fig. 3-3 Access to FIFO registers (big-endian CPU)

3. Endian Settings for 16-bit Bus Width Connection
S1R72V17 CPU Connection Guide EPSON 7
(Rev. 1.0)
3.2 Connection to Little-endian CPU
Access is normally in the mode with “1” set in the CPU_Config register (0x075h address)
CPU_Endian bit.
1) Access to Word register
The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0]
bus to the last byte of the Word register.
The example below illustrates the writing and reading of 0x1234h data to/from the Word
register.
Writing: The data (34h) in the CPU memory even-number address is saved to the last byte
of the S1R72V17 Word register.
Reading: The last byte data (34h) of the S1R72V17 Word register is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
34h
Even-number address
12h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
12h 34h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
12h 34h V17 Word register
Higher byte [15:8] Lower byte [7:0]
_H, _HH, _LH registers _L, _HL, _LL registers
Fig. 3-4 Access to Word registers (little-endian CPU)

3. Endian Settings for 16-bit Bus Width Connection
8 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
2) Access to Byte register
The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus
to the odd-number address register when the CPU_Endian bit is set to “1.”
The example below illustrates the writing and reading of F1h to/from the Byte register
even-number address register and of F2h to/from the Byte register odd-number address register.
Writing: The data (F1h) in the CPU memory even-number address is saved to the
S1R72V17 even-number address register.
Reading: The S1R72V17 even-number address register data (F1h) is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
F1h
Even-number address
F2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
F2h F1h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
F2h F1h V17 Byte register
Odd-number address Even-number address
re
g
ister register
Fig. 3-5 Access to Byte registers (little-endian CPU)

3. Endian Settings for 16-bit Bus Width Connection
S1R72V17 CPU Connection Guide EPSON 9
(Rev. 1.0)
3) Access to FIFO register
The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus
to the odd-number address register when the CPU_Endian bit is set to “1.”
The example below illustrates transmission from the USB bus in the sequence C1h/C2h and
receiving in the sequence C1h/C2h.
Writing: The data (C1h) in the CPU memory even-number address is sent from the USB
bus as the first data.
Reading: The first data received from the USB bus (C1h) is saved to the even-number
address in CPU memory.
CPU
Data
・・・・
・・・・
C1h
Even-number address
C2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
C2h C1h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
C2h C1h V17 Byte register
Odd-number address Even-number address
re
g
ister register
Data[15:8] Data[7:0]
・・・・ ・・・・ V17 FIFO data
・・・・ ・・・・
(2) C2h (1) C1h Sent via USB bus in order (1), (2).
(4) ・・・・ (3) ・・・・
・・・・ ・・・・
・・・・ ・・・・
Fig. 3-6 Access to FIFO registers (little-endian CPU)

4. CPUIF Verification Procedure
10 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
4. CPUIF Verification Procedure
The procedure shown here checks whether the S1R72V17 is correctly connected to the CPU. Follow the
procedure given below, using ICE on the CPU used to control this LSI.
<Connection test start
(
HW reset cancel
)
>
Dumm
y
read PM
_
Control re
g
ister
(
0x012 address
)
Dumm
y
read CPU
_
Ch
g
Endian re
g
ister
(
0x077h address
)
Set CPU
_
Endian, BusMode, Bus8x16 to the CPU
_
Confi
g
re
g
iste
r
Little-endian CPU: 0x74h address
Bi
g
-endian CPU: 0x75h address
Dumm
y
read CPU
_
Ch
g
Endian re
g
ister
(
0x077h address
)
Read/write test to/from Wakeu
p
Tim
_
H,L re
g
isters
(
0x014h address
)
Write clock settin
g
value to ClkSelect re
g
ister
(
0x73h address
)
Write 0x00 to ModeProtect re
g
ister
(
0x071 address
)
Write 0x00 to Chi
p
Reset re
g
ister
(
0x011 address
)
Write oscillation start time to Wakeu
p
Tim
_
H,L re
g
isters
(
0x014 address
)
Write 0x40 to PM
_
Control re
g
ister
(
0x012 address
)
Read MainIntStat re
g
ister
(
0x000 address
)
to check that
FinishedPM bit
(
bit 0
)
is set to “1.”
Read/write test to/from AREA0StartAdrs
_
L,H re
g
isters
(
0x080 address
)
Read/write test to/from D
_
EPaIntEnb re
g
ister
(
0x0C6 address
)
and
D
_
EPbIntEnb re
g
ister
(
0x0C7 address
)
<Connection test end>
1) Recovery processing from
CPU_Cut state
3) CPU operating mode setting
4) Endian setting enabling
5) Asynchronous register access
test (Word register)
6) Clock input setting
7) Clock input setting protect
8) MTM reset
9) Oscillation start time setting
10) Internal clock feed setting
⑦ MTMリセット 11) Internal clock setting
confirmation
12) Synchronous register access
test (Word register)
13) Synchronous register access
test (Byte register)
2) Endian setting initialization
Fig. 4-1 CPU-IF verification procedure

4. CPUIF Verification Procedure
S1R72V17 CPU Connection Guide EPSON 11
(Rev. 1.0)
1) Recovery processing from CPU_Cut state
Dummy read the PM_Control register (0x012h address).
The S1R72V17 switches to CPU_Cut state after resetting has been cancelled. This dummy read
operation ends the CPU_Cut state and switches to Sleep. In the Sleep state, reading/writing is possible
to/from all asynchronous registers.
2) Endian setting initialization
Dummy read the CPU_ChgEndian register (0x077h address).
Setting the ChipReset register (0x011h address) AllReset bit to “1” enables the reset CPU_Config
register CPU_Endian setting after this register has been dummy read when the S1R72V17 has been
reset.
3) CPU operating mode setting
Write the usage mode settings to the CPU_Config register CPU_Endian, BusMode, and Bus8x16 bits.
Little-endian CPU: 0x74h address
Big-endian CPU: 0x75h address
This register address is assigned to the 0x075h address. Since the S1R72V17 operates in the default
big-endian state until this setting is changed, the 0x074h address should be accessed to access a
little-endian CPU.
Table 4-1 CPU_Config register settings
Bus mode CPU endian Setting
Little Endian 0x0416-bit Strobe mode
Big Endian 0x00
Little Endian 0x0616-bit BE mode
Big Endian 0x02
8-bit mode - 0x01
4) Endian setting enabling
Dummy read the CPU_ChgEndian register (0x77h address).
Reading this register enables the CPU_Endian bit set in 3).
5) Asynchronous register access test (Word register)
Read/write test to/from the WakeupTim_L,H registers (0x014 address).
This register can be read/written in the Sleep state. All bits are enabled.
Read/write testing this register checks whether the CPU data bus is correctly connected. If this
read/write operation is not performed correctly, check the physical connection with the CPU.

4. CPUIF Verification Procedure
12 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
6) Clock input setting
Write the clock input setting value to the ClkSelect register (0x73h address).
This sets the clock input method and frequency used for the S1R72V17. The settings are shown in Table
4-2.
Table 4-2 ClkSelect register settings
Clock input method
Clock frequency External oscillator External clock source
12 MHz 0x00 0x80
24 MHz 0x01 0x81
48 MHz Not available 0x83
7) Clock input setting protect
Write 0x00 to the ModeProtect register (0x071 address).
Writing a value other than 0x56 to this register enables write protection for the ClkSelect register.
8) MTM reset
Write 0x00 to the ChipReset register (0x011 address).
Clearing the bit7 ResetMTM bit to “0” clears the USB Transceiver Macro reset and enables oscillation
of the PLL contained in the S1R72V17.
9) Oscillation start time setting
Write the oscillation start time to the WakeupTim_H,L registers (0x014 address).
With external clock source:
Write 0x0010. Note that the external clock source oscillation must have stabilized before this occurs.
With external oscillator:
The standard time is usually within the clock frequency ±10%, but this will vary greatly, depending
on the selected oscillator, circuit board, and external components. Write 0x2500 here to check the
connection.
10) Internal clock feed setting
Write 0x40 to the PM_Control register (0x012 address).
Setting the bit6 GoActive bit to “1” starts the internal clock operation (starts OSC and PLL) and starts
the clock feed to the internal circuit.

4. CPUIF Verification Procedure
S1R72V17 CPU Connection Guide EPSON 13
(Rev. 1.0)
11) Internal clock feed confirmation
Read the MainIntStat register (0x000 address) to confirm that the FinishedPM bit (bit 0) has been set to
“1.”
If this bit is not set, it is likely that the clock is not fed from the external clock when the external clock
source is selected and that the oscillator is not oscillating correctly when the external oscillator is
selected.
In this case, the 0x008 address (MainIntEnb register) bit 0 (EnFinishedPM bit) should be set to “1.” This
asserts the XINT output pin to “Low.” Subsequently clearing the bit to “0” negates the XINT output pin
to “High.” This operation should be used to confirm that an interrupt occurs in the CPU.
Writing “1” to the MainIntStat register (0x000 address) bit 0 (FinishedPM bit) clears this status. Read
the MainIntStat register (0x000 address) bit 0 (FinishedPM bit) again to confirm that it has been cleared
to “0.”
12) Synchronous register access test (Word register)
Read/write test to/from the AREA0StartAdrs_L,H registers (0x080 address).
These registers can be read/written in the Active state.
The first 3 bits (bits [15:13]) and the last 2 bits (bits [1:0]) cannot be written to. They will always read
“0.”
13) Synchronous register access test (Byte register)
Read/write test to/from the D_EPaIntEnb register (0x0C6 address) and D_EPbIntEnb registers (0x0C7
address).
These registers can be read/written in the Active state.
The first bit (bit [7]) for the D_EPaIntEnb and D_EPbIntEnb registers cannot be written to and always
reads “0.”
<This ends the connection test.>

5. Connection Example with FreeScale iMX21
14 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
5. Connection Example with FreeScale iMX21
5.1 Connection Example
This section illustrates an example of a connection between the proven CPU-IF on the S1R72V17
and the iMX21.
The connection uses the S1R72V17 16-bit BE mode bus mode.
iMX21（MC9328MX21）S1R72V17
NVDD1 to 6 CVDD
A
[
8:1
]
CA
[
8:1
]
D
[
15:0
]
CD
[
15:0
]
CS1
X
CS
OE/PC
_
IOWR
X
RD
EB3/DQM3/PC
_
IORD
X
BEL
(
CA
[
0
])
EB2/DQM3/PC
_
REG
X
WRH
(
XBEH
)
RW/PC
_
WE
X
WRL
(
XWR
)
CSPI1
_
RDY
X
DREQ
LD16
X
DACK
LD17
X
INT
Typ: 1.8V
Fig. 5-1 Connection example with iMX21
1) CPU-IF power supply voltage
In this connection example, the CPU-IF supply voltage is Typ 1.8 V.
iMX21 IO supply voltage (NVDD1 to 6): 1.7 V to 3.3 V
S1R72V17 CPU-IF supply voltage (CVDD): 1.65 V to 3.6 V

5. Connection Example with FreeScale iMX21
S1R72V17 CPU Connection Guide EPSON 15
(Rev. 1.0)
2) iMX21 shared pin settings
The iMX21 shared pins are set as shown below in this connection example.
Table 5-1 iMX21 shared pin settings
iMX21 pin name iMX21 pin function
NVDD1 to NVDD6 NVDD1 to NVDD6
A[8:1] A[8:1]
D[15:0] D[15:0]
CS1 CS1
OE/PC_IOWR OE
EB3/DQM3/PC_IORD EB3
EB2/DQM2/PC_REG EB2
RW/PC_WE RW
CSPI1_RDY EXT_DMAREQ
LD16 EXT_DMAGRANT
LD17 PA23(GPIO used as XINT)

5. Connection Example with FreeScale iMX21
16 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
5.2 iMX21 Bus Cycle Setting Example
•iMX21 clock settings
The iMX21 clock settings are set as shown below in this connection example.
System clock: 264 MHz
CPU-IF bus clock (HCLK): 88 MHz (system clock 3 divisions)
•Bus cycle settings
CS1U register (0xDF001008 address) Setting: 0x0402_0700
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SP WP PME SYN
C
1514131211109876543210
EW
CS1L register (0xDF00100C address) Setting: 0x4200_0D01
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
EBC PSR CRE
W
RA
P
CSEN
Setting descriptions
Register Setting Description
RWA 4'b0100 RW output assert timing (2HCLK)
SYNC 1'b0 Synchronous transfer mode (disabled)
RWN 4'b0010 RW output negate timing (1HCLK)
WSC 6'b000111 Access cycle (8HCLK)
WWS 3'b000 Wait cycle for write (0HCLK)
OEA 4'b0100 OE output assert timing (2HCLK)
OEN 4'b0010 OE output negate timing (1HCLK)
WEA 4'b0000 EBx output assert timing (0HCLK)
WEN 4'b0000 EBx output negate timing (0HCLK)
CSA 4'b0000 CS1 output assert timing (0HCLK)
EBC 1'b1 EB3, 2 output mode for read (disabled)
DSZ 3'b101 Data bus size (using 16 bits [15:0])
CSN 4'b0000 CS1 output assert timing (0HCLK)
CSEN 1'b1 CS1 enable (enabled)
DSZ CSN
OEA OEN WEA
CSA
WEN
CNC WSC WWS EDC
DCT RWA PSZ RWN
Fig. 5-2 Bus cycle setting registers