Texas Instruments OMAP5910 User manual

OMAP5910 Dual-Core Processor
Memory Interface Traffic Controller
Reference Guide
Literature Number: SPRU673
October 2003

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5OMAP5910SPRU673
Preface
Read This First
About This Manual
This document describes the OMAP5910 multimedia processor memory
interface traffic controller (TC).
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
www.ti.com.
OMAP5910 Dual-Core Processor MPU Subsystem Reference Guide (litera-
ture number SPRU671)
OMAP5910 Dual-Core Processor DSP Subsystem Reference Guide
(literature number SPRU672)
OMAP5910 Dual-Core Processor Memory Interface Traffic Controller
Reference Guide (literature number SPRU673)
OMAP5910 Dual-Core Processor System DMA Controller Reference Guide
(literature number SPRU674)
OMAP5910 Dual-Core Processor LCD Controller Reference Guide (litera-
ture number SPRU675)
OMAP5910 Dual-Core Processor Universal Asynchronous
Receiver/Transmitter (UART) Devices Reference Guide (literature number
SPRU676)

Trademarks
6OMAP5910 SPRU673
OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame
Adjustment Counter (FAC) Reference Guide (literature number SPRU677)
OMAP5910 Dual-Core Processor Clock Generation and System Reset
Management Reference Guide (literature number SPRU678)
OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO)
Reference Guide (literature number SPRU679)
OMAP5910 Dual-Core Processor MMC/SD Reference Guide (literature
number SPRU680)
OMAP5910 Dual-Core Processor Inter-Integrated Circuit (I2C) Controller
Reference Guide (literature number SPRU681)
OMAP5910 Dual-Core Processor Timer Reference Guide (literature number
SPRU682)
OMAP5910 Dual-Core Processor Inter-Processor Communication
Reference Guide (literature number SPRU683)
OMAP5910 Dual-Core Processor Camera Interface Reference Guide
(literature number SPRU684)
OMAP5905 Dual-Core Processor Multichannel Serial Interface (MCSI)
Reference Guide (literature number SPRU685)
OMAP5910 Dual-Core Processor Micro-Wire Interface Reference Guide
(literature number SPRU686)
OMAP5910 Dual-Core Processor Real-Time Clock (RTC) Reference Guide
(literature number SPRU687)
OMAP5910 Dual-Core Processor HDQ/1-Wire Interface Reference Guide
(literature number SPRU688)
OMAP5910 Dual-Core Processor PWL, PWT, and LED Peripheral
Reference Guide (literature number SPRU689)
OMAP5910 Dual-Core Processor Multichannel Buffered Serial Port (McBSP)
Reference Guide (literature number SPRU708)
Trademarks
OMAP and the OMAP symbol are trademarks of Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
7SPRU673
Contents
1 Introduction 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Memory Map 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Memory Interfaces 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Internal Memory Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 IMIF Priority Handler 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 IMIF Operation 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 External Memory Interface Slow 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 EMIFS Priority Handler 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 EMIFS Operation 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Device Initialization 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 EMIFS Memory Timing Control 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Asynchronous Read Operation 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Asynchronous Page Mode Read Operation 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 Burst Read Operation 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 Asynchronous Write With WE Operation 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9 EMIFS Dual-Port RAM Interface Mode 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 External Memory Interface Fast 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 EMIFF Priority Handler 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 EMIFF Operation 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 SDRAM Mode and Extended Mode Register Initialization 36. . . . . . . . . . . . . . . . . .
3.3.4 SDRAM Autorefresh Initialization 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 SDRAM Self-Refresh Protection 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.6 SDRAM Clock Disable 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.7 Endian Conversion Control 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.8 SDRAM Access Timing Diagrams 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Traffic Controller Memory Interface Registers 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Interfacing Memories With the OMAP5910 Device 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
8SPRU673
Figures
1. TC Block Diagram 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Traffic Controller 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device 27. . . . . . . . . . . . . . . . . . . . . .
4. Asynchronous Page Mode 8x16-Bit Read Operation on a 16-Bit Width Device
(8 Words per Page) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. Asynchronous Page Mode 8x16-Bit Read With Page Crossing on 16-Bit Width Device (4
Words per Page) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. Synchronous Burst Read With Page Alignment 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. Asynchronous Write With WE Operation 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8. SDRAM Write Single 32-Bit Word With Burst Stop 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9. SDRAM Write Single 16-Bit Half-Word With Burst Stop 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10. SDRAM Write Single 16-Bit Half-Word Followed by Write Burst 8 41. . . . . . . . . . . . . . . . . . . . .
11. SDRAM Read Single 16-Bit Half-Word With Burst Stop 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12. SDRAM Read Single 16-Bit Half-Word Followed by Read Burst 8 Half-Word 43. . . . . . . . . . .
13. SDRAM Write Burst 32-Bit Word Followed by Read Burst 8 Half-Word 44. . . . . . . . . . . . . . . .
14. SDRAM Single Half-Word Followed by a Read Burst 6 Half-Words 45. . . . . . . . . . . . . . . . . . .
15. SDRAM Read Burst 4 Half-Words Followed by a Write Burst 3 Half-Words 46. . . . . . . . . . . .
16. SDRAM Read Single Half-Word Followed by a Write Byte 47. . . . . . . . . . . . . . . . . . . . . . . . . . .
17. SDRAM Write Single Followed by Write Burst 6 on the Same Bank
and Different Page 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18. SDRAM Read Single Half-Word Followed by a Read Burst 8 With Page Crossing 49. . . . . .
19. External Memory Interconnection Using Intel Flash Memory 66. . . . . . . . . . . . . . . . . . . . . . . . .
20. External Memory Interconnection Using Hitachi Flash Memory 67. . . . . . . . . . . . . . . . . . . . . . .

Tables
9SPRU673
Tables
1 Controller Access Mode and Data Access Width 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Device Types Associated With Chip-Select 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 MPU Memory Map 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 External Memory Interface Slow Signal List 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 FCLKDIV Settings and Resulting EMIFS Reference Clock 25. . . . . . . . . . . . . . . . . . . . . . . . . .
6 EMIFS CS Active Widths for Asynchronous Reads/Writes 32. . . . . . . . . . . . . . . . . . . . . . . . . . .
7 External Memory Interface Fast Signal List NIL 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Possible SDRAM Configurations 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Traffic Controller Registers 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 IMIF Priority Register (IMIF_PRIO) 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 EMIF Slow Priority Register (EMIFS_PRIO) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 EMIF Fast Priority Register (EMIFF_PRIO) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG) 53. . . . . . . . . . . . . . . . .
14 EMIF Slow Chip-Select Configuration Registers (EMIFS_CS0_CONFIG
EMIFS_CS3_CONFIG) 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 Memory Type 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Wait Cycles Insertion 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 EMIF Fast Interface SDRAM Configuration Register 1 (EMIFF_SDRAM_CONFIG) 56. . . . .
18 SDRAM Internal Organization 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19 Frequency Range(see parameter definitions below 1−19) 59. . . . . . . . . . . . . . . . . . . . . . . . . . .
20 SDRAM Timing Requirements (see parameter definitions below) 60. . . . . . . . . . . . . . . . . . . . .
21 EMIF Fast Interface SDRAM MRS Register—Default (EMIFF_MRS) 61. . . . . . . . . . . . . . . . . .
22 EMIF Fast Interface SDRAM MRS Register—EMRS Mode (EMIFF_MRS) 62. . . . . . . . . . . . .
23 Time-Out 1 Register (TIMEOUT1) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 Time-Out 2 Register (TIMEOUT2) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 Time-Out 3 Register (TIMEOUT3) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 Endianism Register (ENDIANISM) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 EMIF Fast Interface SDRAM Configuration Register 2
(EMIFF_SDRAM_CONFIG_2) 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 EMIF Slow Wait State Configuration (EMIFS_CFG_DYN_WAIT) 64. . . . . . . . . . . . . . . . . . . . .

10 SPRU673

11Memory Interface Traffic ControllerSPRU673
Memory Interface Traffic Controller
This document describes the OMAP5910 multimedia processor memory
interface traffic controller (TC).
1 Introduction
The memory interface traffic controller (TC) manages all accesses by the
MPU, the TMS320C55x DSP, the system DMA, and the local bus to the
OMAP5910 system memory resources (SRAM, SDRAM, flash, ROM, etc.).
The TC also manages accesses by the MPU or the USB host. The USB host
is an internal OMAP5910 peripheral connected on the local bus, so the TC
contributes to managing USB host accesses.
Figure 1 shows the OMAP5910 device with the traffic controller highlighted.
Figure 2 shows the traffic controller in more detail. Table 1 lists the access
modes and data access width of the controllers (MPU, C55x DSP, system
DMA, and local bus).

Introduction
Memory Interface Traffic Controller12 SPRU673
Figure 1. TC Block Diagram
32
32
32
32 System
DMA
controller
E
M
I
F
S
F
F
I
E
M
F
I
M
I
Memory
interface
traffic
controller
(TC)
MPU bus
32
MPU
interface
32
32
DSP
MMU
TMS320C55x DSP
(instruction cache,
SARAM, DARAM, DMA,
H/W accelerators)
16
32
16
FLASH
and
SRAM
memories
memories
SDRAM 16
32
SRAM
1.5 M
bits
32
MPU core
(TI925T)
(instruction
cache, data
cache, MMU)
MPU
peripheral
bridge
32
ETM9
JTAG
emulation
I/F
LCD
I/F
16
32
Osc Osc
Clock and reset
management
12 MHz 32
KHz
Clock
Reset
External
clock
request
DSP private
peripherals
Timers (3)
Watchdog timer
Level1/2
interrupt handlers
DSP private
peripheral
bus
16
DSP public (shared) peripheral bus
MPU private
peripherals
Timers (3)
Watchdog timer
Level 1/2 interrupt
handlers
Configuration
registers
Device
identification
MPU private peripheral bus
32
DSP public peripherals
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
TIPB
switch
UART1
UART2
UART3 IrDA
Mailbox
GPIO I/F
16
USB host I/F
MPU public peripherals
McBSP2
MSB function I/F
I2C
µWire
Camera I/F
MPUIO
32 KHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjustment
counter
HDQ/1-WIRE
RTC
MPU public
peripheral
bus
OMAP5910
or 13 MHz
ROM