Texas Instruments OMAP5910 User manual

OMAP5910 Dual-Core Processor
Memory Interface Traffic Controller
Reference Guide
Literature Number: SPRU673
October 2003

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,
modifications, enhancements, improvements, and other changes to its products and services at any
time and to discontinue any product or service without notice. Customers should obtain the latest
relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order
acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale
in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the
extent TI deems necessary to support this warranty. Except where mandated by government
requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are
responsible for their products and applications using TI components. To minimize the risks associated
with customer products and applications, customers should provide adequate design and operating
safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI
patent right, copyright, mask work right, or other TI intellectual property right relating to any
combination, machine, or process in which TI products or services are used. Information published by
TI regarding third-party products or services does not constitute a license from TI to use such products
or services or a warranty or endorsement thereof. Use of such information may require a license from
a third party under the patents or other intellectual property of the third party, or a license from TI under
the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not
responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by
TI for that product or service voids all express and any implied warranties for the associated TI product
or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such
statements.
Following are URLs where you can obtain information on other Texas Instruments products and
application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

5OMAP5910SPRU673
Preface
Read This First
About This Manual
This document describes the OMAP5910 multimedia processor memory
interface traffic controller (TC).
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
www.ti.com.
OMAP5910 Dual-Core Processor MPU Subsystem Reference Guide (litera-
ture number SPRU671)
OMAP5910 Dual-Core Processor DSP Subsystem Reference Guide
(literature number SPRU672)
OMAP5910 Dual-Core Processor Memory Interface Traffic Controller
Reference Guide (literature number SPRU673)
OMAP5910 Dual-Core Processor System DMA Controller Reference Guide
(literature number SPRU674)
OMAP5910 Dual-Core Processor LCD Controller Reference Guide (litera-
ture number SPRU675)
OMAP5910 Dual-Core Processor Universal Asynchronous
Receiver/Transmitter (UART) Devices Reference Guide (literature number
SPRU676)

Trademarks
6OMAP5910 SPRU673
OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame
Adjustment Counter (FAC) Reference Guide (literature number SPRU677)
OMAP5910 Dual-Core Processor Clock Generation and System Reset
Management Reference Guide (literature number SPRU678)
OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO)
Reference Guide (literature number SPRU679)
OMAP5910 Dual-Core Processor MMC/SD Reference Guide (literature
number SPRU680)
OMAP5910 Dual-Core Processor Inter-Integrated Circuit (I2C) Controller
Reference Guide (literature number SPRU681)
OMAP5910 Dual-Core Processor Timer Reference Guide (literature number
SPRU682)
OMAP5910 Dual-Core Processor Inter-Processor Communication
Reference Guide (literature number SPRU683)
OMAP5910 Dual-Core Processor Camera Interface Reference Guide
(literature number SPRU684)
OMAP5905 Dual-Core Processor Multichannel Serial Interface (MCSI)
Reference Guide (literature number SPRU685)
OMAP5910 Dual-Core Processor Micro-Wire Interface Reference Guide
(literature number SPRU686)
OMAP5910 Dual-Core Processor Real-Time Clock (RTC) Reference Guide
(literature number SPRU687)
OMAP5910 Dual-Core Processor HDQ/1-Wire Interface Reference Guide
(literature number SPRU688)
OMAP5910 Dual-Core Processor PWL, PWT, and LED Peripheral
Reference Guide (literature number SPRU689)
OMAP5910 Dual-Core Processor Multichannel Buffered Serial Port (McBSP)
Reference Guide (literature number SPRU708)
Trademarks
OMAP and the OMAP symbol are trademarks of Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
7SPRU673
Contents
1 Introduction 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Memory Map 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Memory Interfaces 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Internal Memory Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 IMIF Priority Handler 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 IMIF Operation 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 External Memory Interface Slow 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 EMIFS Priority Handler 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 EMIFS Operation 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Device Initialization 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 EMIFS Memory Timing Control 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Asynchronous Read Operation 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Asynchronous Page Mode Read Operation 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 Burst Read Operation 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 Asynchronous Write With WE Operation 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9 EMIFS Dual-Port RAM Interface Mode 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 External Memory Interface Fast 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 EMIFF Priority Handler 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 EMIFF Operation 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 SDRAM Mode and Extended Mode Register Initialization 36. . . . . . . . . . . . . . . . . .
3.3.4 SDRAM Autorefresh Initialization 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 SDRAM Self-Refresh Protection 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.6 SDRAM Clock Disable 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.7 Endian Conversion Control 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.8 SDRAM Access Timing Diagrams 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Traffic Controller Memory Interface Registers 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Interfacing Memories With the OMAP5910 Device 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
8SPRU673
Figures
1. TC Block Diagram 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Traffic Controller 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device 27. . . . . . . . . . . . . . . . . . . . . .
4. Asynchronous Page Mode 8x16-Bit Read Operation on a 16-Bit Width Device
(8 Words per Page) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. Asynchronous Page Mode 8x16-Bit Read With Page Crossing on 16-Bit Width Device (4
Words per Page) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. Synchronous Burst Read With Page Alignment 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. Asynchronous Write With WE Operation 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8. SDRAM Write Single 32-Bit Word With Burst Stop 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9. SDRAM Write Single 16-Bit Half-Word With Burst Stop 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10. SDRAM Write Single 16-Bit Half-Word Followed by Write Burst 8 41. . . . . . . . . . . . . . . . . . . . .
11. SDRAM Read Single 16-Bit Half-Word With Burst Stop 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12. SDRAM Read Single 16-Bit Half-Word Followed by Read Burst 8 Half-Word 43. . . . . . . . . . .
13. SDRAM Write Burst 32-Bit Word Followed by Read Burst 8 Half-Word 44. . . . . . . . . . . . . . . .
14. SDRAM Single Half-Word Followed by a Read Burst 6 Half-Words 45. . . . . . . . . . . . . . . . . . .
15. SDRAM Read Burst 4 Half-Words Followed by a Write Burst 3 Half-Words 46. . . . . . . . . . . .
16. SDRAM Read Single Half-Word Followed by a Write Byte 47. . . . . . . . . . . . . . . . . . . . . . . . . . .
17. SDRAM Write Single Followed by Write Burst 6 on the Same Bank
and Different Page 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18. SDRAM Read Single Half-Word Followed by a Read Burst 8 With Page Crossing 49. . . . . .
19. External Memory Interconnection Using Intel Flash Memory 66. . . . . . . . . . . . . . . . . . . . . . . . .
20. External Memory Interconnection Using Hitachi Flash Memory 67. . . . . . . . . . . . . . . . . . . . . . .

Tables
9SPRU673
Tables
1 Controller Access Mode and Data Access Width 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Device Types Associated With Chip-Select 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 MPU Memory Map 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 External Memory Interface Slow Signal List 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 FCLKDIV Settings and Resulting EMIFS Reference Clock 25. . . . . . . . . . . . . . . . . . . . . . . . . .
6 EMIFS CS Active Widths for Asynchronous Reads/Writes 32. . . . . . . . . . . . . . . . . . . . . . . . . . .
7 External Memory Interface Fast Signal List NIL 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Possible SDRAM Configurations 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Traffic Controller Registers 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 IMIF Priority Register (IMIF_PRIO) 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 EMIF Slow Priority Register (EMIFS_PRIO) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 EMIF Fast Priority Register (EMIFF_PRIO) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG) 53. . . . . . . . . . . . . . . . .
14 EMIF Slow Chip-Select Configuration Registers (EMIFS_CS0_CONFIG
EMIFS_CS3_CONFIG) 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 Memory Type 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Wait Cycles Insertion 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 EMIF Fast Interface SDRAM Configuration Register 1 (EMIFF_SDRAM_CONFIG) 56. . . . .
18 SDRAM Internal Organization 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19 Frequency Range(see parameter definitions below 1−19) 59. . . . . . . . . . . . . . . . . . . . . . . . . . .
20 SDRAM Timing Requirements (see parameter definitions below) 60. . . . . . . . . . . . . . . . . . . . .
21 EMIF Fast Interface SDRAM MRS Register—Default (EMIFF_MRS) 61. . . . . . . . . . . . . . . . . .
22 EMIF Fast Interface SDRAM MRS Register—EMRS Mode (EMIFF_MRS) 62. . . . . . . . . . . . .
23 Time-Out 1 Register (TIMEOUT1) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 Time-Out 2 Register (TIMEOUT2) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 Time-Out 3 Register (TIMEOUT3) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 Endianism Register (ENDIANISM) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 EMIF Fast Interface SDRAM Configuration Register 2
(EMIFF_SDRAM_CONFIG_2) 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 EMIF Slow Wait State Configuration (EMIFS_CFG_DYN_WAIT) 64. . . . . . . . . . . . . . . . . . . . .

10 SPRU673

11Memory Interface Traffic ControllerSPRU673
Memory Interface Traffic Controller
This document describes the OMAP5910 multimedia processor memory
interface traffic controller (TC).
1 Introduction
The memory interface traffic controller (TC) manages all accesses by the
MPU, the TMS320C55x DSP, the system DMA, and the local bus to the
OMAP5910 system memory resources (SRAM, SDRAM, flash, ROM, etc.).
The TC also manages accesses by the MPU or the USB host. The USB host
is an internal OMAP5910 peripheral connected on the local bus, so the TC
contributes to managing USB host accesses.
Figure 1 shows the OMAP5910 device with the traffic controller highlighted.
Figure 2 shows the traffic controller in more detail. Table 1 lists the access
modes and data access width of the controllers (MPU, C55x DSP, system
DMA, and local bus).

Introduction
Memory Interface Traffic Controller12 SPRU673
Figure 1. TC Block Diagram
32
32
32
32 System
DMA
controller
E
M
I
F
S
F
F
I
E
M
F
I
M
I
Memory
interface
traffic
controller
(TC)
MPU bus
32
MPU
interface
32
32
DSP
MMU
TMS320C55x DSP
(instruction cache,
SARAM, DARAM, DMA,
H/W accelerators)
16
32
16
FLASH
and
SRAM
memories
memories
SDRAM 16
32
SRAM
1.5 M
bits
32
MPU core
(TI925T)
(instruction
cache, data
cache, MMU)
MPU
peripheral
bridge
32
ETM9
JTAG
emulation
I/F
LCD
I/F
16
32
Osc Osc
Clock and reset
management
12 MHz 32
KHz
Clock
Reset
External
clock
request
DSP private
peripherals
Timers (3)
Watchdog timer
Level1/2
interrupt handlers
DSP private
peripheral
bus
16
DSP public (shared) peripheral bus
MPU private
peripherals
Timers (3)
Watchdog timer
Level 1/2 interrupt
handlers
Configuration
registers
Device
identification
MPU private peripheral bus
32
DSP public peripherals
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
TIPB
switch
UART1
UART2
UART3 IrDA
Mailbox
GPIO I/F
16
USB host I/F
MPU public peripherals
McBSP2
MSB function I/F
I2C
µWire
Camera I/F
MPUIO
32 KHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjustment
counter
HDQ/1-WIRE
RTC
MPU public
peripheral
bus
OMAP5910
or 13 MHz
ROM

Introduction
13Memory Interface Traffic ControllerSPRU673
Figure 2. Traffic Controller
E
M
I
F
S
E
F
F
M
I
I
F
M
I
16
Slow
bus
Fast
bus
16
S
R
A
M
192
KB
32
Internal
SRAM
bus
MMU
32
MPU bus
Slow I/F DMA
MPU bus
SRAM DMA
Local bus DMA
32
32
32
Slow
port
Fast
port
SRAM port
Local port
32
32
32
32
MPUI
32 32
MPUI-
DMA
port
T
I
P
B
b
r
i
d
g
e
32
TIPB
port
System
DMA
controller
32
32
16
32
Traffic controller
MPU TI peripheral
bus (private)
Local bus
Local
bus
interface
MPU
MPU bus
MPU TI
peripheral
bus (public)
MPU TI
peripheral
bus (private)
ROM SRAM
Flash
SBFlash
SDRAM
To/from
DSP MMU
To/from
MPUI port
Fast I/F DMA
USB Host I/F

Introduction
Memory Interface Traffic Controller14 SPRU673
Table 1. Controller Access Mode and Data Access Width
Controllers
Single Access Mode
Data Access Width
(Bits)
Burst Access Mode
Data Access Width
(Bits) Remarks
MPU 8, 16, 32 32 Single and burst access
C55x DSP 8, 16, 32 32 Single and burst access
System DMA controller 8, 16, 32 16, 32 Single and burst access; the
16-bit burst access is reserved for
the LCD controller channel
Local bus 8, 16, 32 32 Single and burst access
The memories accessed by the TC are separated into two groups:
-External memory is memory that is not part of the OMAP5910 device. It
can be SDRAM, flash, ROM, RAM, etc. External memory is accessed
using the external memory interface (EMIF). The TC has two separate
memory interfaces to access the external memories.
JExternal memory interface fast (EMIFF): A fast synchronous interface
for SDRAM
JExternal memory interface slow (EMIFS): An asynchronous/
synchronous interface to handle flash, ROM, RAM, etc.
-Internal memory is memory that is part of the OMAP5910 device and
consists of 192K bytes (1.5MB) of SRAM. The TC accesses the internal
memory using an internal memory interface (IMIF) that is part of the TC.
Four hosts access the system resources using the TC.
-MPU: The MPU is connected to the TC via the MPU bus. The MPU can
access memories that are connected to the IMIF, EMIFF, and EMIFS.
-DSP: The DSP is connected to the TC via the DSP MMU bus. The C55x
DSP can access memories connected to IMIF, EMIFF, and EMIFS.
-System DMA: The system DMA is connected to the TC using four
separate 32-bit buses, providing the system DMA controller with
concurrent
access to memories connected to the IMIF, EMIFF, and EMIFS.
-Internal local bus interface: An internal local bus interface is connected to
the TC to allow access to memories connected to IMIF, EMIFF, and
EMIFS. In OMAP5910, the USB host controller interfaces to (and is
master of) the local bus.

Memory Map
15Memory Interface Traffic ControllerSPRU673
The TC provides each of the four hosts with:
-8-/16-/32-bit single access and burst access, except the LCD controller
channel. 16- or 32-bit access must start from the 16- or 32-bit boundary
address.
-Size adaptation for 8-, 16-, or 32-bit words, with the requirement that
address must be aligned on the correct bit boundary. For example, 32-bit
access must be aligned on 32-bit boundary, 16-bit access must be aligned
on 16-bit boundary, and so forth.
-Access duration management (wait state insertion) to enable the
connection of slow memory devices
-Memory control signal generation (chip-select, memory-specific protocol
generation)
-16-bit burst access for the LCD controller channels
2 Memory Map
Four external chip-selects and a series of internal address decodes are
provided for external and internal memories and for peripherals attached to the
TI peripheral bus (see Table 2). CS0, CS1, CS2, and CS3 each has an address
range of 32M bytes; the external SDRAM space has an address range of 64M
bytes; the internal SRAM space has an address range of 512K bytes.
EMIFS memory spaces corresponding to CS0 and CS3 are swapped if the
MPU_BOOT pin is high during reset. MPU_BOOT pin 11 is multiplexed with
MCBSP3.DR and USBI_SUSP. This multiplex configuration can be changed
after the reset. The state of this pin is reflected in the BM bit field of the EMIF
slow interface configuration register. For details, see Table 13, EMIF Slow
Interface Configuration Register (EMIFS_CONFIG_REG).
Table 2. Device Types Associated With Chip-Select
CS Device
CS0 External asynchronous RAM, ROM or flash
External synchronous burst flash
CS1 External asynchronous RAM, ROM or flash
External synchronous burst flash
CS2 External asynchronous RAM, ROM, or flash
External synchronous burst flash
CS3 External asynchronous RAM, ROM, or flash
External synchronous burst flash

Memory Map
Memory Interface Traffic Controller16 SPRU673
Table 2. Device Types Associated With Chip-Select (Continued)
CS Device
None†External synchronous dynamic RAM
None†Internal SRAM
†The interface to these memory devices is activated via internal address decoding. There is no
external chip select.
The OMAP5910 peripherals are mapped on the MPU memory space in two
different segments: through STROBE0 (public peripherals) and STROBE1
(private peripherals). Each peripheral has a range of 2K bytes.
Table 3 shows the MPU memory map.
Table 3. MPU Memory Map
Device Name Start Address End Address Size in Bytes Data Access†
System Memory Address Space
External Slow Memory Interface (Flash)
FLASH CS0 0000:0000 01FF:FFFF 32M bytes 8/16/32 R/W
Reserved 0200:0000 03FF:FFFF
FLASH CS1 0400:0000 05FF:FFFF 32M bytes 8/16/32 R/W
Reserved 0600:0000 07FF:FFFF
FLASH CS2 0800:0000 09FF:FFFF 32M bytes 8/16/32 R/W
Reserved 0A00:0000 0BFF:FFFF
FLASH CS3 0C00:0000 0DFF:FFFF 32M bytes 8/16/32 R/W
Reserved 0E00:0000 0FFF:FFFF
External Fast Memory Interface (SDRAM)
SDRAM 1000:0000 13FF:FFFF 64M bytes 8/16 R/W
Reserved 1400:0000 1FFF:FFFF
Internal Memory Interface (SRAM)
Internal RAM 2000:0000 2002:FFFF 192K bytes 8/16/32 R/W
Reserved 2003:0000 2FFF:FFFF
†Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.

Memory Map
17Memory Interface Traffic ControllerSPRU673
Table 3. MPU Memory Map (Continued)
Device Name Data Access† Size in BytesEnd AddressStart Address
DSP Processor Address Space
DSP MPUI Interface
MPUI Port RAM E000:0000 E0FF:FFFF 16M bytes 16/32 R/W
MPUI DSP Peripherals I/O Space E100:0000 E101:FFFF 128K bytes 16 R/W
DSP Private TIPB Peripherals (Strobe0)
DSP TI peripheral bus E100:0000 E100:07FF 2K bytes 16 R/W
Reserved E100:0800 E100:7FFF 30K bytes
DSP CLKM (clock control) E100:8000 E100:87FF 2K bytes 16 R/W
Reserved E100:8800 E100:8FFF 2K bytes
DSP Shared TIPB Peripherals (Strobe1)
UART1 E101:0000 E101:07FF 2K bytes 8 R/W
UART2 E101:0800 E101:0FFF 2K bytes 8 R/W
Reserved E101:1000 E101:17FF 2K bytes
McBSP1 E101:1800 E101:1FFF 2K bytes 16 R/W
MCSI2 E101:2000 E101:27FF 2K bytes 16 R/W
MCSI1 E101:2800 E101:2FFF 2K bytes 16 R/W
Reserved E101:3000 E101:6FFF 16K bytes
McBSP3 E101:7000 E101:77FF 2K bytes 16 R/W
Reserved E101:7800 E101:97FF 8K bytes
UART3 E101:9800 E101:9FFF 2K bytes 8 R/W
Reserved E101:A000 E101:DFFF 16K bytes
GPIOs E101:E000 E101:E7FF 2K bytes 16 R/W
Reserved E101:E800 E101:EFFF 6K bytes
MPU Address Space
MPUI port interrupt, control and
status registers
E102:0000 E102:0003 4 bytes 16 R/W
†Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.

Memory Map
Memory Interface Traffic Controller18 SPRU673
Table 3. MPU Memory Map (Continued)
Device Name Data Access† Size in BytesEnd AddressStart Address
MPU Address Space (Continued)
Reserved E102:0004 EFFF:FFFF
Reserved F000:0000 FFFD:0000
MPU Public TIPB Peripherals (Strobe 0)
UART1 FFFB:0000 FFFB:07FF 2K bytes 8 R/W
UART2 FFFB:0800 FFFB:0FFF 2K bytes 8 R/W
McBSP2 FFFB:1000 FFFB:17FF 2K bytes 16 R/W
Reserved FFFB:1800 FFFB:2FFF 6K bytes
µWire FFFB:3000 FFFB:37FF 2K bytes 16 R/W
I2C FFFB:3800 FFFB:3FFF 2K bytes 16 R/W
USB function FFFB:4000 FFFB:47FF 2K bytes 16 R/W
RTC FFFB:4800 FFFB:4FFF 2K bytes 8 R/W
MPUIO FFFB:5000 FFFB:57FF 2K bytes 16 R/W
PWL FFFB:5800 FFFB:5FFF 2K bytes 8 R/W
PWT FFFB:6000 FFFB:67FF 2K bytes 8 R/W
Camera IF FFFB:6800 FFFB:6FFF 2K bytes 32 R/W
Reserved FFFB:7000 FFFB:77FF 2K bytes
MMC FFFB:7800 FFFB:7FFF 2K bytes 16 R/W
Reserved FFFB:8000 FFFB:8FFF 4K bytes
32-kHz timer FFFB:9000 FFFB:97FF 2K bytes 32 R/W
UART3 FFFB:9800 FFFB:9FFF 2K bytes 8 R/W
USB host FFFB:A000 FFFB:A7FF 2K bytes 32 R/W
FAC FFFB:A800 FFFB:AFFF 2K bytes 16 R/W
Reserved FFFB:B000 FFFB:BFFF 4K bytes
HDQ/1-Wire FFFB:C000 FFFB:C7FF 2K bytes 8 R/W
†Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.

Memory Map
19Memory Interface Traffic ControllerSPRU673
Table 3. MPU Memory Map (Continued)
Device Name Data Access† Size in BytesEnd AddressStart Address
MPU Public TIPB Peripherals (Strobe 0) (continued)
TIPB switches FFFB:C800 FFFB:CFFF 2K bytes 16 R/W
LED1 FFFB:D000 FFFB:D7FF 2K bytes 8 R/W
LED2 FFFB:D800 FFFB:DFFF 2K bytes 8 R/W
Reserved FFFB:E000 FFFB:FFFF 8K bytes
MPU Public TIPB Peripherals (Strobe 1)
Reserved FFFC:0000 FFFC:DFFF 56K bytes
GPIOs FFFC:E000 FFFC:E7FF 2K bytes 32 R/W
Reserved FFFC:E800 FFFC:EFFF 2K bytes
Mailbox FFFC:F000 FFFC:F7FF 2K bytes 16 R/W
Reserved FFFC:F800 FFFC:FFFF 2K bytes
MPU Private TIPB Peripherals (Strobe 0)
Reserved FFFD:0000 FFFD:FFFF 2K bytes
MPU Private TIPB Peripherals (Strobe 1)
MPU level 2 interrupt handler FFFE:0000 FFFE:07FF 2K bytes 32 R/W
ULPD power management FFFE:0800 FFFE:0FFF 2K bytes 16 R/W
OMAP5910 configuration FFFE:1000 FFFE:17FF 2K bytes 32 R/W
Die ID FFFE:1800 FFFE:1FFF 2K bytes 32 R/W
Reserved FFFE:2000 FFFE:BFFF 40K bytes
LCD controller FFFE:C000 FFFE:C0FF 256 bytes 32 R/W
Local bus interface FFFE:C100 FFFE:C1FF 256 bytes 32 R/W
Local bus MMU FFFE:C200 FFFE:C2FF 256 bytes 32 R/W
Reserved FFFE:C300 FFFE:C4FF 512 bytes
MPU Timer 1 FFFE:C500 FFFE:C5FF 256 bytes 32 R/W
MPU Timer 2 FFFE:C600 FFFE:C6FF 256 bytes 32 R/W
†Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.

Memory Interfaces
Memory Interface Traffic Controller20 SPRU673
Table 3. MPU Memory Map (Continued)
Device Name Data Access† Size in BytesEnd AddressStart Address
MPU Private TIPB Peripherals (Strobe 1) (Continued)
MPU Timer 3 FFFE:C700 FFFE:C7FF 256 bytes 32 R/W
MPU watchdog timer FFFE:C800 FFFE:C8FF 256 bytes 32 R/W
MPUI FFFE:C900 FFFE:C9FF 256 bytes 32 R/W
MPU private TIPB bridge FFFE:CA00 FFFE:CAFF 256 bytes 32 R/W
MPU level 1 interrupt handler FFFE:CB00 FFFE:CBFF 256 bytes 32 R/W
Traffic controller FFFE:CC00 FFFE:CCFF 256 bytes 32 R/W
Reserved FFFE:CD00 FFFE:CDFF 256 bytes
MPU CLKM (clock control) FFFE:CE00 FFFE:CEFF 256 bytes 32 R/W
DPLL1 FFFE:CF00 FFFE:CFFF 256 bytes 32 R/W
Reserved FFFE:D000 FFFE:D0FF 256 bytes
Reserved FFFE:D100 FFFE:D1FF 256 bytes
DSP MMU FFFE:D200 FFFE:D2FF 256 bytes 32 R/W
MPU public TIPB bridge FFFE:D300 FFFE:D3FF 256 bytes 16 R/W
JTAG ID code FFFE:D400 FFFE:D4FF 256 bytes 32 R/W
Reserved FFFE:D500 FFFE:D7FF
System DMA controller FFFE:D800 FFFE:DFFF 2K bytes 16 R/W
Reserved FFFE:E000 FFFE:FFFF 2K bytes each
†Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.
3 Memory Interfaces
The TC has three memory interfaces:
-Internal memory interface (IMIF)
-External memory interface slow (EMIFS)
-External memory interface fast (EMIFF)

Memory Interfaces
21Memory Interface Traffic ControllerSPRU673
3.1 Internal Memory Interface
The IMIF interfaces to an on-chip 192K byte (1.5 MB) block of SRAM. The
interface handles all single and burst requests from the MPU, the DSP, the
system DMA controller, and the local bus.
3.1.1 IMIF Priority Handler
This memory interface has two software-selectable priority algorithms for
resolving simultaneous access requests: least recently used and dynamic
priority. The priority scheme is shared with the EMIFS and EMIFF and is set
in the OMAP5910 configuration registers (bit 20, LRU_SEL in
FUNC_MUX_CTRL_0). See SPRU671, MPU Subsystem Reference Gide, for
details on configuration registers.
-Least recently used
JA round-robin arbitration scheme. The highest priority requestor is the
one that least recently accessed the memory.
-Dynamic priority
JDynamic priority uses high- and low-priority queues.
JEach requestor, except the MPU, has a time-out register allocated to it
(see Time-Out Registers in Section 4). These registers hold the
number of clock cycles that a low-priority queue request must wait
before it is moved from the low-priority queue to the high-priority
queue.
JAt reset, all requestors are initially in the low-priority queue and the
time-out registers are set to minimum value for each requestor. You
must program these registers before using dynamic priority.
JThe low-priority queue order is:
HMPU
HDSP
HLocal bus
HDMA (all channels including LCD)
JThe high-priority queue order is:
HDMA transfer to LCD controller
HDSP
HLocal bus
HDMA transfer involving channels other than LCD channel
-Fixed priority is a special case of dynamic priority. To create a fixed priority,
all time-out registers must have a value of 0. This way any request made
goes into the high-priority queue after one clock cycle. Then the high-
priority queue provides a fixed priority.

Memory Interfaces
Memory Interface Traffic Controller22 SPRU673
3.1.2 IMIF Operation
The 192K bytes of internal SRAM are selected by an internal chip select based
on the appropriate address decode. The interface to the SRAM is 32 bits wide
and provides support for single and burst accesses. The SRAM operates at
the frequency of the traffic controller.
3.2 External Memory Interface Slow
The EMIFS interfaces traditional and synchronous flash, asynchronous
SRAM, and ROM. The interface can drive up to four devices with one of four
chip-select pins. Each chip-select pin has a corresponding register to specify
the protocol for the associated external device.
Table 4 shows the EMIFS signal list.
Table 4. External Memory Interface Slow Signal List
Signal Name I/O Bus Description
FLASH.RDY I −Ready/busy signal from device
FLASH.WP O −Write protection
FLASH.CLK O −Clock signal for flash device
FLASH.RP O−Flash power-down/reset
FLASH.CS0 O−Active-low chip-select for device
FLASH.CS1 O−Active-low chip-select for device
FLASH.CS2†O−Active-low chip-select for device
FLASH.CS3 O−Active-low chip-select for device
FLASH.BAA†O−Active-low burst advance acknowledge for Advanced Micro Devices
(AMD) burst flash
FLASH.OE O−Active-low output enable
FLASH.WE O−Active-low write enable
FLASH.ADV O−Active-low address valid
FLASH.D[15:0] I/O 15−0Flash data bus from external device
†FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu-
ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default.