Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
Enhanced Direct Memory Access (EDMA) Controller
Reference Guide
Literature Number: SPRU234B
March 2005

iiiRead This FirstSPRU234B
Preface
Read This First
About This Manual
This document describes the operation of the enhanced direct memory access
(EDMA) controller in the digital signal processors (DSPs) of the
TMS320C6000™DSP family. This document also describes the quick DMA
(QDMA) used for fast data requests by the CPU. For operation and registers
unique to the TMS320C621x/C671x EDMA, see Chapter 3. For operation and
registers unique to the TMS320C64x™EDMA, see Chapter 4.
Notational Conventions
This document uses the following conventions.
Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Registers in this document are shown in figures and described in tables.
Each register figure shows a rectangle divided into fields that represent
the fields of the register. Each field is labeled with its bit name, its
beginning and ending bit numbers above, and its read/write properties
below. A legend explains the notation used for the properties.
Reserved bits in a register figure designate a bit that is used for future
device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the C6000 devices, related periph-
erals, and other technical collateral, is available in the C6000 DSP product
folder at: www.ti.com/c6000.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000™CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.

Trademarks
iv SPRU234BRead This First
TMS320C6000 DSP Peripherals Overview Reference Guide (literature
number SPRU190) describes the peripherals available on the
TMS320C6000™DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62x™and TMS320C67x™DSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64x™DSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI™.
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000™DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studio™integrated develop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studio™application programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000™peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
number SPRU401) describes a set of application programming interfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
vContentsSPRU234B
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provides an overview and describes the common operation of the enhanced direct-memory
access (EDMA) controller in the digital signal processors (DSPs) of the TMS320C6000 DSP
family. Also describes the quick DMA (QDMA) used for fast data requests by the CPU.
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EDMA Terminology 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Parameter RAM Overview 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Types of EDMA Transfers 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 1-Dimensional Transfers 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 2-Dimensional Transfers 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Initiating an EDMA Channel Controller Transfer 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 Event-Triggered Transfer Request 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 Chain-Triggered Transfer Request 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3 CPU-Triggered Transfer Request 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 EDMA Channel Controller Event-to-Channel Mapping 1-19. . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Element Size and Alignment 1-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Fixed-Mode Transfer Considerations 1-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Parameter Set Updates 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.1 Element and Frame/Array Count Updates 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.2 Source/Destination Address Updates 1-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Channel Completion Conditions 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Linking EDMA Transfers 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.12 Terminating an EDMA Transfer 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13 Chaining EDMA Channels 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.14 Transfer Complete Code (TCC) Generation 1-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.14.1 Alternate Transfer Complete Code (ATCC) Generation
(C64x EDMA only) 1-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15 EDMA Interrupt Generation Based on Completion Code 1-37. . . . . . . . . . . . . . . . . . . . . . . .
1.15.1 EDMAINT Servicing by the CPU 1-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16 Quick DMA (QDMA) 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16.1 Initiating a QDMA Transfer 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16.2 QDMA Stalls and Priority 1-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.17 Emulation Operation 1-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18 Transfer Examples 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18.1 Block Move Example 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18.2 Subframe Extraction Example 1-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18.3 Data Sorting Example 1-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18.4 Peripheral Servicing Examples 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18.5 Transfer Chaining Examples 1-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
vi SPRU234BContents
2 EDMA Transfer Controller 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the EDMA transfer controller (EDMATC).
2.1 EDMA Transfer Controller Performance 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Transfer Request Submission 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Request Chain 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Transfer Crossbar 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Address Generation/Transfer Logic 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 TMS320C621x/C671x EDMA 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EDMA controller in the
TMS320C621x/C671x DSP. Also describes the quick DMA (QDMA) registers that the CPU
uses for fast data requests.
3.1 Event Service Priority 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Parameter RAM (PaRAM) 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Chaining EDMA Channels by an Event 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 EDMA Transfer Controller Priority 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Transfer Controller Transfer Request Queue Length 3-6. . . . . . . . . . . . . . . . . . . . .
3.5 EDMA Control Registers 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 EDMA Event Selector Registers (ESEL0, 1, 3) 3-8. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Priority Queue Status Register (PQSR) 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 EDMA Channel Interrupt Pending Register (CIPR) 3-15. . . . . . . . . . . . . . . . . . . . . .
3.5.4 EDMA Channel Interrupt Enable Register (CIER) 3-16. . . . . . . . . . . . . . . . . . . . . . .
3.5.5 EDMA Channel Chain Enable Register (CCER) 3-17. . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 EDMA Event Register (ER) 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 EDMA Event Enable Register (EER) 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.8 Event Clear Register (ECR) 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.9 EDMA Event Set Register (ESR) 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 EDMA Channel Parameter Entries 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 EDMA Channel Options Parameter (OPT) 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 EDMA Channel Source Address Parameter (SRC) 3-25. . . . . . . . . . . . . . . . . . . . .
3.6.3 EDMA Channel Transfer Count Parameter (CNT) 3-26. . . . . . . . . . . . . . . . . . . . . .
3.6.4 EDMA Channel Destination Address Parameter (DST) 3-27. . . . . . . . . . . . . . . . . .
3.6.5 EDMA Channel Index Parameter (IDX) 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.6 EDMA Channel Count Reload/Link Address Parameter (RLD) 3-29. . . . . . . . . . . .
3.7 QDMA Registers 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 QDMA Channel Options Register (QOPT, QSOPT) 3-32. . . . . . . . . . . . . . . . . . . . .
3.7.2 QDMA Channel Source Address Register (QSRC, QSSRC) 3-33. . . . . . . . . . . . .
3.7.3 QDMA Channel Transfer Count Register (QCNT, QSCNT) 3-33. . . . . . . . . . . . . . .
3.7.4 QDMA Channel Destination Address Register (QDST, QSDST) 3-33. . . . . . . . . .
3.7.5 QDMA Channel Index Register (QIDX, QSIDX) 3-33. . . . . . . . . . . . . . . . . . . . . . . .

Contents
viiContentsSPRU234B
4 TMS320C64x EDMA 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EDMA controller in the TMS320C64x DSP. Also
describes the quick DMA (QDMA) registers that are used for fast data requests by the CPU.
4.1 Event Service Priority 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Parameter RAM (PaRAM) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Chaining EDMA Channels With a Single Event 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Alternate Transfer Chaining 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Peripheral Device Transfers 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 EDMA Transfer Controller Priority 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Transfer Controller Transfer Request Queue Length 4-9. . . . . . . . . . . . . . . . . . . . .
4.5.2 Modifying Default Queue Usage and Queue Allocation 4-11. . . . . . . . . . . . . . . . . .
4.6 EDMA Access Into L2 Control 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 EDMA Control Registers 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1 Priority Queue Status Register (PQSR) 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Priority Queue Allocation Registers (PQAR0−3) 4-15. . . . . . . . . . . . . . . . . . . . . . . .
4.7.3 EDMA Channel Interrupt Pending Registers (CIPRL, CIPRH) 4-16. . . . . . . . . . . .
4.7.4 EDMA Channel Interrupt Enable Registers (CIERL, CIERH) 4-18. . . . . . . . . . . . .
4.7.5 EDMA Channel Chain Enable Registers (CCERL, CCERH) 4-20. . . . . . . . . . . . . .
4.7.6 EDMA Event Registers (ERL, ERH) 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.7 EDMA Event Enable Registers (EERL, EERH) 4-24. . . . . . . . . . . . . . . . . . . . . . . . .
4.7.8 Event Clear Registers (ECRL, ECRH) 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.9 Event Set Registers (ESRL, ESRH) 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.10 Event Polarity Registers (EPRL, EPRH) 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 EDMA Channel Parameter Entries 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 EDMA Channel Options Parameter (OPT) 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 EDMA Channel Source Address Parameter (SRC) 4-37. . . . . . . . . . . . . . . . . . . . .
4.8.3 EDMA Channel Transfer Count Parameter (CNT) 4-38. . . . . . . . . . . . . . . . . . . . . .
4.8.4 EDMA Channel Destination Address Parameter (DST) 4-39. . . . . . . . . . . . . . . . . .
4.8.5 EDMA Channel Index Parameter (IDX) 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.6 EDMA Channel Count Reload/Link Address Parameter (RLD) 4-41. . . . . . . . . . . .
4.9 QDMA Registers 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1 QDMA Channel Options Register (QOPT, QSOPT) 4-44. . . . . . . . . . . . . . . . . . . . .
4.9.2 QDMA Channel Source Address Register (QSRC, QSSRC) 4-45. . . . . . . . . . . . .
4.9.3 QDMA Channel Transfer Count Register (QCNT, QSCNT) 4-45. . . . . . . . . . . . . . .
4.9.4 QDMA Channel Destination Address Register (QDST, QSDST) 4-45. . . . . . . . . .
4.9.5 QDMA Channel Index Register (QIDX, QSIDX) 4-45. . . . . . . . . . . . . . . . . . . . . . . .
A EDMA Transfers A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes all of the different types of EDMA transfers.
A.1 Element Synchronized 1D-to-1D Transfers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Frame Synchronized 1D-to-1D Transfers A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Array Synchronized 2D-to-2D Transfers A-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4 Block Synchronized 2D-to-2D Transfers A-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.5 Array Synchronized 1D-to-2D Transfers A-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.6 Block Synchronized 1D-to-2D Transfers A-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7 Array Synchronized 2D-to-1D Transfers A-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.8 Block Synchronized 2D-to-1D Transfers A-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
viii SPRU234BFigures
Figures
1−1 TMS320C621x/C671x/C64x DSP Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 EDMA Channel Controller Block Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 EDMA Channel Parameter Entries for Each EDMA Event—C6416 DSP 1-10. . . . . . . . . . . . .
1−4 1-Dimensional Transfer Data Frame 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 1D Transfer with Element Synchronization (FS = 0) 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 1D Transfer With Frame Synchronization (FS = 1) 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 2-Dimensional Transfer Data Block 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8 2D Transfer with Array Synchronization (FS = 0) 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−9 2D Transfer with Block Synchronization (FS = 1) 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−10 Linked EDMA Transfer 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−11 Terminating EDMA Transfers 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−12 Block Move Example Diagram 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−13 Block Move Example QDMA Registers Content 1-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−14 Subframe Extraction Example Diagram 1-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−15 Subframe Extraction Example QDMA Registers Content 1-44. . . . . . . . . . . . . . . . . . . . . . . . . .
1−16 Data Sorting Example Diagram 1-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−17 Data Sorting Example QDMA Registers Content 1-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−18 Servicing Incoming McBSP Data Example Diagram 1-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−19 Servicing Incoming McBSP Data Example EDMA Parameters Content 1-49. . . . . . . . . . . . . .
1−20 Servicing Peripheral Bursts Example Diagram 1-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−21 Servicing Peripheral Bursts Example EDMA Parameters Content 1-51. . . . . . . . . . . . . . . . . .
1−22 Servicing Continuous McBSP Data Example Diagram 1-52. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−23 Servicing Continuous McBSP Data Example EDMA Parameters Content 1-53. . . . . . . . . . . .
1−24 Servicing Continuous McBSP Data Example EDMA Reload Parameters Content 1-54. . . . .
1−25 Ping-Pong Buffering for McBSP Data Example Diagram 1-56. . . . . . . . . . . . . . . . . . . . . . . . . .
1−26 Ping-Pong Buffering Example EDMA Parameters Content 1-57. . . . . . . . . . . . . . . . . . . . . . . . .
1−27 Ping-Pong Buffering Example EDMA Pong Parameters Content 1-58. . . . . . . . . . . . . . . . . . .
1−28 Ping-Pong Buffering Example EDMA Ping Parameters Content 1-59. . . . . . . . . . . . . . . . . . . .
1−29 Alternate Transfer Complete Chaining Example 1-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−30 Single Large Block Data Transfer Example 1-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−31 Smaller Packet Data Transfers Example 1-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 EDMA Transfer Request Block Diagram 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Address Generation/Transfer Logic Block Diagram 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 EDMA Channel Parameter Entries for Each EDMA Event—C621x/C671x DSP 3-4. . . . . . . .
3−2 EDMA Event Selector Register 0 (ESEL0) 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 EDMA Event Selector Register 1 (ESEL1) 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 EDMA Event Selector Register 3 (ESEL3) 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
ixFiguresSPRU234B
3−5 Priority Queue Status Register (PQSR) 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 EDMA Channel Interrupt Pending Register (CIPR) 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 EDMA Channel Interrupt Enable Register (CIER) 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 EDMA Channel Chain Enable Register (CCER) 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 EDMA Event Register (ER) 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 EDMA Event Enable Register (EER) 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 EDMA Event Clear Register (ECR) 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 EDMA Event Set Register (ESR) 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 EDMA Channel Options Parameter (OPT) 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 EDMA Channel Source Address Parameter (SRC) 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 EDMA Channel Transfer Count Parameter (CNT) 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 EDMA Channel Destination Address Parameter (DST) 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 EDMA Channel Index Parameter (IDX) 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 EDMA Channel Count Reload/Link Address Parameter (RLD) 3-30. . . . . . . . . . . . . . . . . . . . .
3−19 QDMA Registers 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−20 QDMA Channel Options Register (QOPT) 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−21 QDMA Channel Source Address Register (QSRC) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−22 QDMA Channel Transfer Count Register (QCNT) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−23 QDMA Channel Destination Address Register (QDST) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−24 QDMA Channel Index Register (QIDX) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 EDMA Channel Parameter Entries for Each EDMA Event—C64x DSP 4-4. . . . . . . . . . . . . . .
4−2 L2 EDMA Access Control Register (EDMAWEIGHT) 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Priority Queue Status Register (PQSR) 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Priority Queue Allocation Register (PQAR) 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 EDMA Channel Interrupt Pending Low Register (CIPRL) 4-16. . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 EDMA Channel Interrupt Pending High Register (CIPRH) 4-17. . . . . . . . . . . . . . . . . . . . . . . . .
4−7 EDMA Channel Interrupt Enable Low Register (CIERL) 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 EDMA Channel Interrupt Enable High Register (CIERH) 4-19. . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 EDMA Channel Chain Enable Low Register (CCERL) 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 EDMA Channel Chain Enable High Register (CCERH) 4-21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 EDMA Event Low Register (ERL) 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 EDMA Event High Register (ERH) 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 EDMA Event Enable Low Register (EERL) 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 EDMA Event Enable High Register (EERH) 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 EDMA Event Clear Low Register (ECRL) 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 EDMA Event Clear High Register (ECRH) 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 EDMA Event Set Low Register (ESRL) 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 EDMA Event Set High Register (ESRH) 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 EDMA Event Polarity Low Register (EPRL) 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 EDMA Event Polarity High Register (EPRH) 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 EDMA Channel Options Parameter (OPT) 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 EDMA Channel Source Address Parameter (SRC) 4-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−23 EDMA Channel Transfer Count Parameter (CNT) 4-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 EDMA Channel Destination Address Parameter (DST) 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−25 EDMA Channel Index Parameter (IDX) 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−26 EDMA Channel Count Reload/Link Address Parameter (RLD) 4-42. . . . . . . . . . . . . . . . . . . . .

Figures
xSPRU234BFigures
4−27 QDMA Registers 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 QDMA Channel Options Register (QOPT) 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−29 QDMA Channel Source Address Register (QSRC) 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 QDMA Channel Transfer Count Register (QCNT) 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 QDMA Channel Destination Address Register (QDST) 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−32 QDMA Channel Index Register (QIDX) 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−1 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 00) A-3. . . . . . . . . . . . . . . . . . .
A−2 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 01) A-4. . . . . . . . . . . . . . . . . . .
A−3 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 10) A-5. . . . . . . . . . . . . . . . . . .
A−4 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 11) A-6. . . . . . . . . . . . . . . . . . .
A−5 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 00) A-7. . . . . . . . . . . . . . . . . . .
A−6 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 01) A-8. . . . . . . . . . . . . . . . . . .
A−7 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 10) A-9. . . . . . . . . . . . . . . . . . .
A−8 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 11) A-10. . . . . . . . . . . . . . . . . .
A−9 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 00) A-11. . . . . . . . . . . . . . . . . .
A−10 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 01) A-12. . . . . . . . . . . . . . . . . .
A−11 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 10) A-13. . . . . . . . . . . . . . . . . .
A−12 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 11) A-14. . . . . . . . . . . . . . . . . .
A−13 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 00) A-15. . . . . . . . . . . . . . . . . .
A−14 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 01) A-16. . . . . . . . . . . . . . . . . .
A−15 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 10) A-17. . . . . . . . . . . . . . . . . .
A−16 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 11) A-18. . . . . . . . . . . . . . . . . .
A−17 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 00) A-20. . . . . . . . . . . . . . . . . . . .
A−18 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 01) A-21. . . . . . . . . . . . . . . . . . . .
A−19 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 10) A-22. . . . . . . . . . . . . . . . . . . .
A−20 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 11) A-23. . . . . . . . . . . . . . . . . . . .
A−21 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 00) A-24. . . . . . . . . . . . . . . . . . . .
A−22 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 01) A-25. . . . . . . . . . . . . . . . . . . .
A−23 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 10) A-26. . . . . . . . . . . . . . . . . . . .
A−24 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 11) A-27. . . . . . . . . . . . . . . . . . . .
A−25 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 00) A-28. . . . . . . . . . . . . . . . . . . .
A−26 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 01) A-29. . . . . . . . . . . . . . . . . . . .
A−27 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 10) A-30. . . . . . . . . . . . . . . . . . . .
A−28 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 11) A-31. . . . . . . . . . . . . . . . . . . .
A−29 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 00) A-32. . . . . . . . . . . . . . . . . . . .
A−30 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 01) A-33. . . . . . . . . . . . . . . . . . . .
A−31 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 10) A-34. . . . . . . . . . . . . . . . . . . .
A−32 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 11) A-35. . . . . . . . . . . . . . . . . . . .
A−33 Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) A-37. . . . . . . . . . . . . . . . . . . .
A−34 Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) A-38. . . . . . . . . . . . . . . . . . . .
A−35 Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 10) A-39. . . . . . . . . . . . . . . . . . . .
A−36 Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 00) A-40. . . . . . . . . . . . . . . . . . . .
A−37 Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 01) A-41. . . . . . . . . . . . . . . . . . . .
A−38 Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 10) A-42. . . . . . . . . . . . . . . . . . . .
A−39 Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 00) A-43. . . . . . . . . . . . . . . . . . . .
A−40 Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 01) A-44. . . . . . . . . . . . . . . . . . . .
A−41 Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 10) A-45. . . . . . . . . . . . . . . . . . . .

Figures
xiFiguresSPRU234B
A−42 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) A-47. . . . . . . . . . . . . . . . . . . .
A−43 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) A-48. . . . . . . . . . . . . . . . . . . .
A−44 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 10) A-49. . . . . . . . . . . . . . . . . . . .
A−45 Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 00) A-50. . . . . . . . . . . . . . . . . . . .
A−46 Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 01) A-51. . . . . . . . . . . . . . . . . . . .
A−47 Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 10) A-52. . . . . . . . . . . . . . . . . . . .
A−48 Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 00) A-53. . . . . . . . . . . . . . . . . . . .
A−49 Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 01) A-54. . . . . . . . . . . . . . . . . . . .
A−50 Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 10) A-55. . . . . . . . . . . . . . . . . . . .
A−51 Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 00) A-57. . . . . . . . . . . . . . . . . . . .
A−52 Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 01) A-58. . . . . . . . . . . . . . . . . . . .
A−53 Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 10) A-59. . . . . . . . . . . . . . . . . . . .
A−54 Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 00) A-60. . . . . . . . . . . . . . . . . . . .
A−55 Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 01) A-61. . . . . . . . . . . . . . . . . . . .
A−56 Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 10) A-62. . . . . . . . . . . . . . . . . . . .
A−57 Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 00) A-63. . . . . . . . . . . . . . . . . . . .
A−58 Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 01) A-64. . . . . . . . . . . . . . . . . . . .
A−59 Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 10) A-65. . . . . . . . . . . . . . . . . . . .
A−60 Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 00) A-67. . . . . . . . . . . . . . . . . . . .
A−61 Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 01) A-68. . . . . . . . . . . . . . . . . . . .
A−62 Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 10) A-69. . . . . . . . . . . . . . . . . . . .
A−63 Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 00) A-70. . . . . . . . . . . . . . . . . . . .
A−64 Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 01) A-71. . . . . . . . . . . . . . . . . . . .
A−65 Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 10) A-72. . . . . . . . . . . . . . . . . . . .
A−66 Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 00) A-73. . . . . . . . . . . . . . . . . . . .
A−67 Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 01) A-74. . . . . . . . . . . . . . . . . . . .
A−68 Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 10) A-75. . . . . . . . . . . . . . . . . . . .
A−69 Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 00) A-77. . . . . . . . . . . . . . . . . . . .
A−70 Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 01) A-78. . . . . . . . . . . . . . . . . . . .
A−71 Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 10) A-79. . . . . . . . . . . . . . . . . . . .
A−72 Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 00) A-80. . . . . . . . . . . . . . . . . . . .
A−73 Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 01) A-81. . . . . . . . . . . . . . . . . . . .
A−74 Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 10) A-82. . . . . . . . . . . . . . . . . . . .
A−75 Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 00) A-83. . . . . . . . . . . . . . . . . . . .
A−76 Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 01) A-84. . . . . . . . . . . . . . . . . . . .
A−77 Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 10) A-85. . . . . . . . . . . . . . . . . . . .
A−78 Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 00) A-87. . . . . . . . . . . . . . . . . . . .
A−79 Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 01) A-88. . . . . . . . . . . . . . . . . . . .
A−80 Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 10) A-89. . . . . . . . . . . . . . . . . . . .
A−81 Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 00) A-90. . . . . . . . . . . . . . . . . . . .
A−82 Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 01) A-91. . . . . . . . . . . . . . . . . . . .
A−83 Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 10) A-92. . . . . . . . . . . . . . . . . . . .
A−84 Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 00) A-93. . . . . . . . . . . . . . . . . . . .
A−85 Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 01) A-94. . . . . . . . . . . . . . . . . . . .
A−86 Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 10) A-95. . . . . . . . . . . . . . . . . . . .

Tables
xii SPRU234BTables
Tables
1−1 Differences Between the C621x/C671x and C64x EDMA 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 EDMA Parameter RAM Contents—C6416 DSP 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 EDMA Channel Parameter Descriptions—C6416 DSP 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 EDMA Channel Synchronization Events—C6211 DSP 1-20. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 EDMA Channel Synchronization Events—C6416 DSP 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 EDMA Element and Frame/Array Count Updates 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 Source/Destination Address Update Modes 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8 EDMA Source Address Parameter Updates 1-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−9 EDMA Destination Address Parameter Updates 1-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−10 Channel Completion Conditions For Transfer Type 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−11 Transfer Complete Code (TCC) to EDMA Interrupt Mapping (C621x/C671x DSP) 1-35. . . . .
1−12 Transfer Complete Code (TCC) to EDMA Interrupt Mapping (C64x DSP) 1-35. . . . . . . . . . . .
1−13 Channel Completion Conditions For Alternate Transfer Complete Codes 1-37. . . . . . . . . . . .
1−14 QDMA Transfer Length 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 Cache Controller Data Transfers—C621x/C671x DSP 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 EDMA Parameter RAM Contents—C621x/C671x DSP 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 EDMA Channel Parameter Descriptions—C621x/C671x DSP 3-4. . . . . . . . . . . . . . . . . . . . . . .
3−3 Programmable Priority Levels for Data Requests—C621x/C671x DSP 3-6. . . . . . . . . . . . . . .
3−4 Transfer Request Queues—C621x/C671x DSP 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 EDMA Control Registers—C621x/C671x DSP 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 EDMA Event Selector Register 0 (ESEL0) Field Descriptions 3-9. . . . . . . . . . . . . . . . . . . . . . .
3−7 EDMA Event Selector Register 0 (ESEL1) Field Descriptions 3-10. . . . . . . . . . . . . . . . . . . . . .
3−8 EDMA Event Selector Register 0 (ESEL3) Field Descriptions 3-11. . . . . . . . . . . . . . . . . . . . . .
3−9 Default EDMA Event for EDMA Channel—C6713 DSP 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 EDMA Event for EDMA Event Selector Value—C6713 DSP 3-12. . . . . . . . . . . . . . . . . . . . . . .
3−11 Priority Queue Status Register (PQSR) Field Descriptions 3-14. . . . . . . . . . . . . . . . . . . . . . . . .
3−12 EDMA Channel Interrupt Pending Register (CIPR) Field Descriptions 3-15. . . . . . . . . . . . . . .
3−13 EDMA Channel Interrupt Enable Register (CIER) Field Descriptions 3-16. . . . . . . . . . . . . . . .
3−14 EDMA Channel Chain Enable Register (CCER) Field Descriptions 3-17. . . . . . . . . . . . . . . . .
3−15 EDMA Event Register (ER) Field Descriptions 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 EDMA Event Enable Register (EER) Field Descriptions 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 EDMA Event Clear Register (ECR) Field Descriptions 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 EDMA Event Set Register (ESR) Field Descriptions 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−19 EDMA Parameter Entries—C621x/C671x DSP 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−20 EDMA Channel Options Parameter (OPT) Field Descriptions 3-23. . . . . . . . . . . . . . . . . . . . . .
3−21 EDMA Channel Source Address Parameter (SRC) Field Descriptions 3-25. . . . . . . . . . . . . . .

Tables
xiiiTablesSPRU234B
3−22 EDMA Channel Transfer Count Parameter (CNT) Field Descriptions 3-26. . . . . . . . . . . . . . . .
3−23 EDMA Channel Destination Address Parameter (DST) Field Descriptions 3-27. . . . . . . . . . .
3−24 EDMA Channel Index Parameter (IDX) Field Descriptions 3-28. . . . . . . . . . . . . . . . . . . . . . . . .
3−25 EDMA Channel Count Reload/Link Address Parameter (RLD) Field Descriptions 3-30. . . . .
4−1 EDMA Parameter RAM Contents—C64x DSP 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 EDMA Channel Parameter Descriptions—C64x DSP 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Programmable Priority Levels for Data Requests—C64x DSP 4-8. . . . . . . . . . . . . . . . . . . . . .
4−4 Transfer Request Queues—C6416 DSP 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 L2 EDMA Access Control Register (EDMAWEIGHT) Field Descriptions 4-12. . . . . . . . . . . . .
4−6 EDMA Control Registers—C64x DSP 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Priority Queue Status Register (PQSR) Field Descriptions 4-14. . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Priority Queue Allocation Register (PQAR) Field Descriptions 4-15. . . . . . . . . . . . . . . . . . . . . .
4−9 EDMA Channel Interrupt Pending Low Register (CIPRL) Field Descriptions 4-16. . . . . . . . . .
4−10 EDMA Channel Interrupt Pending High Register (CIPRH) Field Descriptions 4-17. . . . . . . . .
4−11 EDMA Channel Interrupt Enable Low Register (CIERL) Field Descriptions 4-18. . . . . . . . . . .
4−12 EDMA Channel Interrupt Enable High Register (CIERH) Field Descriptions 4-19. . . . . . . . . .
4−13 EDMA Channel Chain Enable Low Register (CCERL) Field Descriptions 4-20. . . . . . . . . . . .
4−14 EDMA Channel Chain Enable High Register (CCERH) Field Descriptions 4-21. . . . . . . . . . .
4−15 EDMA Event Low Register (ERL) Field Descriptions 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 EDMA Event High Register (ERH) Field Descriptions 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 EDMA Event Enable Low Register (EERL) Field Descriptions 4-25. . . . . . . . . . . . . . . . . . . . . .
4−18 EDMA Event Enable High Register (EERH) Field Descriptions 4-25. . . . . . . . . . . . . . . . . . . . .
4−19 EDMA Event Clear Low Register (ECRL) Field Descriptions 4-27. . . . . . . . . . . . . . . . . . . . . . .
4−20 EDMA Event Clear High Register (ECRH) Field Descriptions 4-27. . . . . . . . . . . . . . . . . . . . . .
4−21 EDMA Event Set Low Register (ESRL) Field Descriptions 4-29. . . . . . . . . . . . . . . . . . . . . . . . .
4−22 EDMA Event Set High Register (ESRH) Field Descriptions 4-29. . . . . . . . . . . . . . . . . . . . . . . .
4−23 EDMA Event Polarity Low Register (EPRL) Field Descriptions 4-30. . . . . . . . . . . . . . . . . . . . .
4−24 EDMA Event Polarity High Register (EPRH) Field Descriptions 4-31. . . . . . . . . . . . . . . . . . . .
4−25 EDMA Parameter Entries—C64x DSP 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−26 EDMA Channel Options Parameter (OPT) Field Descriptions 4-33. . . . . . . . . . . . . . . . . . . . . .
4−27 EDMA Channel Source Address Parameter (SRC) Field Descriptions 4-37. . . . . . . . . . . . . . .
4−28 EDMA Channel Transfer Count Parameter (CNT) Field Descriptions 4-38. . . . . . . . . . . . . . . .
4−29 EDMA Channel Destination Address Parameter (DST) Field Descriptions 4-39. . . . . . . . . . .
4−30 EDMA Channel Index Parameter (IDX) Field Descriptions 4-40. . . . . . . . . . . . . . . . . . . . . . . . .
4−31 EDMA Channel Count Reload/Link Address Parameter (RLD) Field Descriptions 4-42. . . . .
A−1 Element Synchronized (FS = 0) 1D-to-1D Transfers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−2 Frame Synchronized (FS = 1) 1D-to-1D Transfers A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−3 Array Synchronized (FS = 0) 2D-to-2D Transfers A-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−4 Block Synchronized (FS = 1) 2D-to-2D Transfers A-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−5 Array Synchronized (FS = 0) 1D-to-2D Transfers A-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−6 Block Synchronized (FS = 1) 1D-to-2D Transfers A-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−7 Array Synchronized (FS = 0) 2D-to-1D Transfers A-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−8 Block Synchronized (FS = 1) 2D-to-1D Transfers A-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−1 Document Revision History B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1OverviewSPRU234B
Overview
This chapter provides an overview and describes the common operation of the
enhanced direct memory access channel controller (EDMACC) in the digital
signal processors (DSPs) of the TMS320C6000™DSP family. This chapter
also describes the quick DMA (QDMA) used for direct data requests by the
CPU. For an overview and description of the enhanced direct memory access
transfer controller (EDMATC), see Chapter 2.
For operation and registers unique to the TMS320C621x/C671x EDMA, see
Chapter 3. For operation and registers unique to the TMS320C64x™EDMA,
see Chapter 4.
Topic Page
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EDMA Terminology 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Parameter RAM Overview 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Types of EDMA Transfers 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Initiating an EDMA Channel Controller Transfer 1-17. . . . . . . . . . . . . . . .
1.6 EDMA Channel Controller Event-to-Channel Mapping 1-19. . . . . . . . . .
1.7 Element Size and Alignment 1-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Fixed-Mode Transfer Considerations 1-23. . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Parameter Set Updates 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Channel Completion Conditions 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Linking EDMA Transfers 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.12 Terminating an EDMA Transfer 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13 Chaining EDMA Channels 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.14 Transfer Complete Code (TCC) Generation 1-34. . . . . . . . . . . . . . . . . . . .
1.15 EDMA Interrupt Generation Based on Completion Code 1-37. . . . . . . .
1.16 Quick DMA (QDMA) 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.17 Emulation Operation 1-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.18 Transfer Examples 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Overview
Overview1-2 SPRU234B
1.1 Overview
The enhanced direct memory access (EDMA) controller handles all data
transfers between the level-two (L2) cache/memory controller and the device
peripherals on the C621x/C671x/C64x DSP, as shown in Figure 1−1. These
data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses.
The EDMA controller in the C621x/C671x/C64x DSP has a different
architecture from the previous DMA controller in the C620x/C670x devices.
The EDMA includes several enhancements to the DMA, such as 64 channels
for the C64x DSP or 16 channels for the C621x/C671x DSP, with
programmable priority, and the ability to link and chain data transfers. The
EDMA allows movement of data to/from any addressable memory spaces,
including internal memory (L2 SRAM), peripherals, and external memory.
The enhanced direct memory access consists of two primary components:
1) Transfer controller (EDMATC) handles all data transfers between the
level-two (L2) cache/memory controller and the device peripherals on the
C621x/C671x/C64x DSP, as shown in Figure 1−1 These data transfers
include EDMA channel controller transfers, cache accesses to/from EMIF
range, noncacheable memory accesses, and master peripheral
accesses.
2) Channel controller (EDMACC) is the user-programmable portion of the
EDMA that supports a flexible and powerful set of transfers, including 1D
and 2D transfers; flexible triggering including event triggered transfers,
chained transfers, and CPU triggered transfers; and flexible reload and
addressing modes that support ping-pong buffers, circular buffering,
frame extraction, and sorting.

Overview
1-3OverviewSPRU234B
Figure 1−1. TMS320C621x/C671x/C64x DSP Block Diagram
Data path 2
External
memory
interface
(EMIF)
Other
Peripherals
Power down logic
EDMA
transfer
controller
(EDMATC)
Timers
L1P cache direct mapped
L1 S1 M1 D1 D2 M2 S2 L2
A register file
Data path 1
B register file
Interrupt control
CPU core
Instruction fetch
Instruction dispatch
Instruction decode In-circuit emulation
Control registers
L2 memory
4 banks
L1D
controller
L1D cache
2-way set
associative
L1P
controller
EDMA
channel
controller
(EDMACC)
Figure 1−2 shows a block diagram of the EDMA channel controller. The EDMA
channel controller (EDMACC) comprises:
Parameter RAM (PaRAM): Maintains parameter entries for channel and
reload parameter sets. You write to the PaRAM to setup transfer context
for desired channels and link parameter sets. EDMACC processes entries
based on a trigger event and submits transfer request (TR) to the EDMA
transfer controller (EDMATC).
Event and interrupt processing registers: Allows you to enable/disable
events; enable trigger types; enable/disable interrupt conditions; and
clear and process interrupts based on completion of DMAs.
Completion detect: Completion detect block detects completion of trans-
fers within EDMATC. Completion of transfers can optionally be used to
cause submission of new transfers (chaining) or generate interrupts to the
CPU via EDMA_INT.
Table 1−1 summarizes the difference between the C6000 EDMAs.

Overview
Overview1-4 SPRU234B
Figure 1−2. EDMA Channel Controller Block Diagram
Ch0 parameter set
Ch1 parameter set
Ch3 parameter set
Ch2 parameter set
Link2 parameter set
Link1 parameter set
Link0 parameter set
ChN parameter set
LinkM parameter set
Transfer
request
(TR)
(to EDMA
transfer
controller)
CPU
trigger Chain trigger
or
Event 0
Event 1
Event 2
Event 3
Event N
Completion
detect
Channel interrupt
pending (CIPR)
enable (CIER)
Channel interrupt
Event
trigger
Parameter RAM
(PaRAM)
NTransfer
completion
code (TCC/ATCC)
(from EDMA
transfer
controller)
From
peripheral
s
or external
events
EDMA_INT
(to CPU)
TR processing
and submission
Event set (ESR)
Channel chain
enable (CCER)
Event enable (EER)
Event (ER)
or

Overview
1-5OverviewSPRU234B
Table 1−1. Differences Between the C621x/C671x and C64x EDMA
Features C621x/C671x EDMA C64x EDMA
Alternate transfer complete
chaining and interrupt
Does not apply. Supported
CIPR, CIER, CCER, ER, EER,
ECR, ESR
Each of these registers supports
16 channels.
Each of these registers supports
64 channels and is expanded into
two registers (low and high).
EDMA clock rate EDMA clock rate equals
CPU clock rate.
EDMA clock rate equals one half of
CPU clock rate (CPU/2).
EDMA transfers possible on all
priority queues
EDMA cannot transfer on Q0. EDMA transfers possible on all
priority queues.
Event polarity selection Does not apply. Supported.
L2 controller transfers possible
on all priority queues
L2 controller transfers on Q0 only. L2 controller transfers possible on all
priority queues.
Number of channels 16 channels. 64 channels.
Programmable priority queue
allocation (PQAR0−3)
Does not apply. Supported.
Programmable event polarity
(EPRL, EPRH)
Does not apply. Supported.
Supports peripheral device
transfers
Does not apply. Supported.
Transfer chaining on channels Only channels 8 to 11 can be
chained.
All channels can be chained.

EDMA Terminology
Overview1-6 SPRU234B
1.2 EDMA Terminology
The following definitions help in understanding some of the terms used in this
document:
Enhanced Direct Memory Access (EDMA) Controller: Consists of the
EDMA transfer controller (EDMATC) and the EDMA channel controller
(EDMACC).
EDMA Transfer Controller (EDMATC): The central data transfer engine
of the EDMA. The EDMATC concurrently performs data transfers for the
first queued transfer request (TR) of each transfer controller priority
queue. The number of TR queues (and thus concurrent transfers) is
device dependent.
EDMA Channel Controller (EDMACC): The user-programmable portion
of the EDMA. The EDMACC consists of a parameter RAM (PaRAM) (and
associated enable/disable registers) that can be programmed with many
active (channel parameter sets) and reload parameter sets that can be
initiated via external events, peripheral events, or CPU synchronization.
The number of channel/link parameter sets is device dependent.
Transfer Request (TR): A request for data movement that is submitted
by all transfer controller requestors to the transfer controller. A TR includes
source address, destination address, element count, options, etc. For the
EDMA channel controller, a TR is submitted based on a synchronization
event.
Quick DMA (QDMA): A programmable DMA parameter set that is local
to the CPU, rather than located in the EDMA channel controller. QDMA
allows direct (and quick) CPU-initiated DMA submission without having to
submit requests to the EDMA channel controller.
Element-Synchronized Transfer: An element-synchronized transfer
submits a transfer request (TR) for a single element when a synchroniza-
tion event is received. The EDMA channel controller updates the source
address, destination address, element count, and frame count after each
TR.
Frame-Synchronized Transfer: A frame-synchronized transfer submits
a transfer request (TR) for a single frame of element count elements when
a synchronization event is received. The EDMA channel controller
updates the source address, destination address, and frame count after
each TR. Elements and frames are spaced by a programmable index.

EDMA Terminology
1-7OverviewSPRU234B
Array-Synchronized Transfer: An array-synchronized transfer submits
a transfer request (TR) for a single array of element count elements when
a synchronization event is received. The EDMA channel controller
updates the source address, destination address, and array count after
each TR. Elements are always contiguous and frames are spaced by a
programmable index.
Block-Synchronized Transfer: A block-synchronized transfer submits a
transfer request (TR) for an array count arrays of element count elements
when a synchronization event is received. The EDMA channel controller
does not perform any address or count updates. Elements are always
contiguous and frames are spaced by a programmable index.
Parameter RAM (PaRAM): User-programmable RAM that stores
channel parameter sets and link parameter sets.
Parameter Set: A 24-byte long EDMA channel transfer definition. Each
parameter set consists of six 4-byte parameter set entries.
Parameter Set Entry: One of the 4-byte components of a parameter set.
This includes source address, destination address, options, count, index,
and reload entries.
Channel Parameter Set: One of the 16 (621x/671x DSP) or 64 (64x DSP)
parameter sets that can be initiated via a synchronization event. Note that
unused channel parameter sets can also be used for linking.
Link Parameter Set: One of the parameter sets that are strictly used for
linking and are not one of the channel parameter sets.
Trigger Event: Action that causes the EDMA channel controller to submit
a transfer request (TR). Synchronization events include CPU-trigger,
event-trigger, and chain-trigger.
Element: The smallest unit of a DMA transfer. An element can be 8-bit,
16-bit, or 32-bit.
Frame: A group of elements comprise a frame. A frame can have
staggered or contiguous elements. Frame is used in context with
1-dimensional (1D) transfer.
Array: A group of contiguous elements comprise an array. The elements
in an array cannot be spaced by an element index. Array is used in context
with 2-dimensional (2D) transfer.
Block: A group of arrays or frames form a block. For 1-dimensional (1D)
transfers, a group of frames form a block. For 2-dimensional (2D) trans-
fers, a group of arrays form a block.

Parameter RAM Overview
Overview1-8 SPRU234B
1-dimensional (1D) transfer: A group of frames comprise a 1D block.
The number of frames (FRMCNT) in a block can range from 1 to 65536.
The number of elements (ELECNT) per frame can range from 1 to 65535.
Either elements or full frames can be transferred at a time.
2-dimensional (2D) transfer: A group of arrays comprise a 2D block. The
first dimension is the number of contiguous elements in an array, and the
second dimension is the number of such arrays. The number of arrays
(FRMCNT) in a block can range from 1 to 65536. Either arrays or the entire
block can be transferred at a time.
1.3 Parameter RAM Overview
Unlike the C620x/C670x DMA controller, which is a register-based
architecture, the EDMA channel controller (EDMACC) is a RAM-based archi-
tecture. The parameter RAM (PaRAM) consists of a device-dependent
number of parameter sets, ranging from 85 parameter sets (2-KByte RAM) to
213 parameter sets (5-KByte RAM).
Parameter sets are further defined as channel parameter sets or link parame-
ter sets. The C621x/C671x EDMA supports 16 channels; thus providing
16 channel parameter sets. The C64x EDMA supports 64 channels; thus
providing 64 channel parameter sets. The remaining PaRAM sets are link
parameter sets.
Channel parameter sets can be triggered by various methods, including event
trigger, chain trigger, or CPU trigger. Channel parameter sets that are not used
as an active channel can also be used as a link entry. This is detailed in
section 1.11. Link parameter sets cannot be directly submitted via a trigger.
Instead, the link parameter sets can be automatically copied (or linked) onto
one of the channel parameter sets upon completion of the parameter set for
the given channel. This allows the CPU to setup and manage ping-pong
buffers, circular buffers, etc, while a transfer is ongoing by updating the link
parameter sets as necessary.
Table 1−2 shows the PaRAM format for a C6416 DSP, which consists of
64 channels and 85 total parameter RAM entries (64 channel parameter sets
and 21 link parameter sets). Each parameter entry of an EDMA event is
organized into six 32-bit words or 24 bytes, as shown in Figure 1−3 and
described in Table 1−3.
EDMA Terminology / Parameter RAM Overview