Texas Instruments TPS65981 User manual

Host
SEL EN
External FET Sense and CTRL
Alternate Mode Mux Ctrl
TPS65981
POL
D±
D±
SBU1/2
CC/VCONN
VBUS
GND
CC1/2
USB_TP/TN
USB_BP/BN
SBU1/2
3 A
3 A
SuperSpeed Mux
3.3 V
5 to 20 V
5 A
5 V
2
Type-
and
USB PD Controller
C Cable
Detection
2
2
2
USB2.0 and
Sideband-Use
Data
5 to 20 V
High
Speed
Mux
Host
Interface USB
Type-C
Connector
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65981
SLVSDC2B –FEBRUARY 2016–REVISED AUGUST 2016
TPS65981 USB Type-C and USB PD Controller, Power Switch, and High Speed Multiplexer
1
1 Features
1• USB Power Delivery (PD) Controller
– Mode Configuration for Source (Host), Sink
(Device), or Source-Sink
– Bi-Phase Marked Encoding and Decoding
(BMC)
– Physical Layer (PHY) Protocol
– Policy Engine
– Configurable at Boot and Host-Controlled
• USB Type-C Specification Compliant
– Detect USB Cable Plug Attach
– Cable Orientation and Role Detection
– Assign CC and VCONN Pins
– Advertise Default, 1.5 A or 3 A for Type-C
Power
• Port-Power Switch
– 5-V, 3-A Switch to VBUS for Type-C Power
– 5-V to 20-V, 3-A Bidirectional Switch to or from
VBUS for USB PD Power
– 5-V, 600-mA Switches for VCONN
– Overcurrent Limiter, Overvoltage Protector
– Slew-Rate Control
– Hard Reset Support
• Port Data Multiplexer
– USB 2.0 HS Data and Low Speed Endpoint
– Sideband-Use Data for Alternate Modes
(DisplayPort, for Example)
• Power Management
– Gate Control and Current Sense for External
5-V to 20-V, 5-A Bidirectional Switch (Back-to-
Back NFETs)
– Power Supply from 3.3-V or VBUS Source
– 3.3-V LDO Output for Dead Battery Support
• QFN Package for Reliable Manufacturing
– 0.5-mm Pitch
– 2-Layer PCB Compatibility
2 Applications
• After-Market Automotive Infotainment
• Industrial Equipment
• Medical Equipment
• Notebooks, Tablets, and Ultrabooks
• Monitors and TVs
• USB PD Hosts, Devices, and Dual-Role Ports
3 Description
The TPS65981 device is a stand-alone, USB Type-C,
and power-delivery (PD) controller providing cable-
plug and orientation detection at the USB Type-C
connector. Upon cable detection, the TPS65981
device communicates on the CC wire using the USB
PD protocol. When cable detection and USB PD
negotiation are complete, the TPS65981 device
enables the appropriate power path and configures
alternate mode settings for internal and (optional)
external multiplexers.
The mixed-signal front end on the CC pins provides
default (900 mA), 1.5-A, or 3-A current for Type-C
power sources, detects a plug event, determines the
USB Type-C cable orientation, and autonomously
negotiates USB PD contracts by adhering to the
specified biphase-marked coding (BMC) and
physical-layer (PHY) protocol.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65981 VQFN (56) 8.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Diagram

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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Power Supply Requirements and Characteristics..... 9
7.6 Power Supervisor Characteristics........................... 10
7.7 Power Consumption Characteristics....................... 10
7.8 Cable Detection Characteristics.............................. 11
7.9 USB-PD Baseband Signal Requirements and
Characteristics ......................................................... 12
7.10 USB-PD TX Driver Voltage Adjustment
Parameter ................................................................ 13
7.11 Port Power Switch Characteristics........................ 13
7.12 Port Data Multiplexer Switching Characteristics... 16
7.13 Port Data Multiplexer Clamp Characteristics........ 17
7.14 Port Data Multiplexer SBU Detection
Requirements........................................................... 18
7.15 Port Data Multiplexer Signal Monitoring Pullup and
Pulldown Characteristics.......................................... 18
7.16 Port Data Multiplexer USB Endpoint Requirements
and Characteristics .................................................. 18
7.17 Port Data Multiplexer BC1.2 Detection
Requirements and Characteristics........................... 18
7.18 Analog-to-Digital Converter (ADC)
Characteristics ......................................................... 19
7.19 Input-Output (I/O) Requirements and
Characteristics ......................................................... 19
7.20 I2C Slave Requirements and Characteristics........ 20
7.21 SPI Master Characteristics ................................... 21
7.22 BUSPOWERZ Configuration Requirements......... 22
7.23 Single-Wire Debugger (SWD) Timing
Requirements........................................................... 22
7.24 Thermal Shutdown Characteristics....................... 22
7.25 HPD Timing Requirements and Characteristics ... 22
7.26 Oscillator Requirements and Characteristics........ 23
7.27 Typical Characteristics ......................................... 23
8 Parameter Measurement Information ................ 24
9 Detailed Description............................................ 27
9.1 Overview................................................................. 27
9.2 Functional Block Diagram....................................... 28
9.3 Feature Description................................................. 29
9.4 Device Functional Modes........................................ 64
9.5 Programming .......................................................... 70
10 Application and Implementation........................ 74
10.1 Application Information.......................................... 74
10.2 Typical Applications .............................................. 74
11 Power Supply Recommendations ..................... 81
11.1 3.3 V Power .......................................................... 81
11.2 1.8 V Core Power.................................................. 81
11.3 VDDIO................................................................... 82
12 Layout................................................................... 83
12.1 Layout Guidelines ................................................. 83
12.2 Layout Example .................................................... 86
13 Device and Documentation Support................. 91
13.1 Device Support...................................................... 91
13.2 Documentation Support ........................................ 91
13.3 Receiving Notification of Documentation Updates 91
13.4 Community Resources.......................................... 91
13.5 Trademarks........................................................... 91
13.6 Electrostatic Discharge Caution............................ 91
13.7 Glossary................................................................ 91
14 Mechanical, Packaging, and Orderable
Information........................................................... 92
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2016) to Revision B Page
• Changed the device status from Product Preview to Production Data ................................................................................. 1

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5 Description (continued)
The port-power switch provides up to 3 A downstream at 5 V for legacy and Type-C USB power. An additional
bidirectional switch path provides USB PD power up to 3 A at a maximum of 20 V as either a source (host), sink
(device), or source-sink.
The TPS65981 device is also an upstream-facing port (UFP), downstream-facing port (DFP), or dual-role port for
data. The port-data multiplexer passes data to or from the top or bottom D+/D– signal pair at the port for USB 2.0
HS and has a USB 2.0 low-speed endpoint. Additionally, the sideband-use (SBU) signal pair is used for auxiliary
or alternate modes of communication (DisplayPort, for example).
The power-management circuitry uses 3.3 V inside the system and also uses VBUS to start up and negotiate
power for a dead-battery or no-battery condition.

Thermal
Pad
56 LDO_1V8A15C_CC2
1GPIO8 42 VDDIO
55 AUX_N16RPD_G2
2DEBUG1 41 GPIO0
54 AUX_P17VBUS
3SS 40 LDO_1V8D
53 VIN_3V318VBUS
4USB_RP_P 39 SPI_SSZ
52 R_OSC19GPIO3
5USB_RP_N 38 GPIO7
51 LDO_3V320GPIO6
6C_USB_TP 37 SPI_CLK
50 SWD_CLK21RESETZ
7C_USB_TN 36 SPI_MOSI
49 SWD_DATA22BUSPOWERZ
8C_USB_BP 35 SPI_MISO
48 LDO_BMC23GPIO5
9C_USB_BN 34 PP_HV
47 I2C_SCL24MRESET
10C_SBU1 33 PP_HV
46 I2C_SDA25GPIO2
11C_SBU2 32 HV_GATE2
45 DEBUG_CTL126GPIO4
12RPD_G1 31 HV_GATE1
44 DEBUG_CTL227PP_5V0
13C_CC1 30 SENSEP
43 I2C_IRQZ28PP_5V0
14PP_CABLE 29 SENSEN
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6 Pin Configuration and Functions
RTQ Package
56-Pin VQFN With Exposed Thermal Pad
Top View
Pin Functions
PIN CATEGORY I/O TYPE POR STATE DESCRIPTION
NAME NO.
AUX_N 55 Port Multiplexer Analog I/O Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩand 5-MΩresistance when
unused.
AUX_P 54 Port Multiplexer Analog I/O Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩand 5-MΩresistance when
unused.
BUSPOWERZ 22 Digital Core I/O
and Control Analog Input Input (Hi-Z)
General-purpose digital I/O 10. Sampled by ADC at boot. Tie pin
to LDO_3V3 through a 100-kΩresistor to disable PP_HV and
PP_EXT power paths during dead-battery or no-battery boot
conditions. Refer to the BUSPOWERZ table for more details.
C_CC1 13 Type-C Port Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with
capacitance CC_CC1 to GND.
C_CC2 15 Type-C Port Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with
capacitance CC_CC2 to GND.
C_SBU1 10 Type-C Port Analog I/O Hi-Z Port side-sideband use connection of port multiplexer.
C_SBU2 11 Type-C Port Analog I/O Hi-Z Port side-sideband use connection of port multiplexer.
C_USB_BN 9 Type-C Port Analog I/O Hi-Z Port-side bottom USB D– connection to the port multiplexer.
C_USB_BP 8 Type-C Port Analog I/O Hi-Z Port-side bottom USB D+ connection to the port multiplexer.
C_USB_TN 7 Type-C Port Analog I/O Hi-Z Port-side top USB D– connection to the port multiplexer.
C_USB_TP 6 Type-C Port Analog I/O Hi-Z Port-side top USB D+ connection to the port multiplexer.

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Pin Functions (continued)
PIN CATEGORY I/O TYPE POR STATE DESCRIPTION
NAME NO.
DEBUG_CTL1 45 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address.
DEBUG_CTL2 44 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 17. At power-up, pin state is sensed
to determine bit 5 of the I2C address.
DEBUG1 2 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 15. Ground pin with a 1-MΩresistor when unused in the application.
GPIO0 41 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 0. Float pin if it is configured as a
push-pull output in the application. Ground pin with a 1-MΩ
resistor when unused in the application.
GPIO2 25 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 2. Float pin if it is configured as a
push-pull output in the application. Ground pin with a 1-MΩ
resistor when unused in the application.
GPIO3 19 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 3. Float pin if it is configured as a
push-pull output in the application. Ground pin with a 1-MΩ
resistor when unused in the application.
GPIO4 26 Digital Core I/O
and Control Digital I/O Hi-Z
General-purpose digital I/O 4. Configured as a hot-plug detect
(HPD) transistor, HPD receiver, or both when DisplayPort mode is
supported. Ground pin with a 1-MΩresistor when unused in the
application.
GPIO5 23 Digital Core I/O
and Control Digital I/O Hi-Z
General-purpose digital I/O 5. Can be configured as a HPD
receiver when DisplayPort mode is supported. Must be tied high
or low through a 1-kΩpull-up or pull-down resistor when used as
a configuration input. Ground pin with a 1-MΩresistor when
unused in the application.
GPIO6 20 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 6. Float pin if it is configured as a
push-pull output in the application. Ground pin with a 1-MΩ
resistor when unused in the application.
GPIO7 38 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 7. Float pin if it is configured as a
push-pull output in the application. Ground pin with a 1-MΩ
resistor when unused in the application.
GPIO8 1 Digital Core I/O
and Control Digital I/O Hi-Z General-purpose digital I/O 8. Float pin if it is configured as a
push-pull output in the application. Ground pin with a 1-MΩ
resistor when unused in the application.
HV_GATE1 31 External HV FET
Control and Sense Analog Output Short to SENSEP External NFET gate control for high voltage power path. Float pin when unused.
HV_GATE2 32 External HV FET
Control and Sense Analog Output Short to VBUS External NFET gate control for high voltage power path. Float pin when unused.
I2C_IRQZ 43 Digital Core I/O
and Control Digital Output Hi-Z I2C port interrupt. Active low. Implement externally as an open-
drain with a pull-up resistance. Float pin when unused.
I2C_SCL 47 Digital Core I/O
and Control Digital I/O Digital Input I2C port serial clock. Open-drain output. Tie pin to LDO_3V3 or
VDDIO (depending on configuration) through a 10-kΩresistor
when used or unused.
I2C_SDA 46 Digital Core I/O
and Control Digital I/O Digital Input I2C port serial data. Open-drain output. Tie pin to LDO_3V3 or
VDDIO (depending on configuration) through a 10-kΩresistor
when used or unused.
LDO_1V8A 56 Low Current Power N/A Output of the 1.8-V LDO for core analog circuits. Bypass with
capacitance CLDO_1V8A to GND.
LDO_1V8D 40 Low Current Power N/A Output of the 1.8-V LDO for core digital circuits. Bypass with
capacitance CLDO_1V8D to GND.
LDO_3V3 51 Low Current Power N/A Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash
memory. Bypass with capacitance CLDO_3V3 to GND.
LDO_BMC 48 Low Current Power N/A Output of the USB-PD BMC transceiver output level LDO. Bypass
with capacitance CLDO_BMC to GND.
MRESET 24 Digital Core I/O
and Control Digital I/O Hi-Z
General-purpose digital I/O 11. Forces RESETZ to assert. By
default, this pin asserts RESETZ when pulled high. The pin can
be programmed to assert RESETZ when pulled low. Ground pin
with a 1-MΩresistor when unused in the application.
PP_5V0 27 High Current Power N/A 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to
GND. Tie pin to GND when unused
28
PP_CABLE 14 High Current Power N/A 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when
unused.

6
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Pin Functions (continued)
PIN CATEGORY I/O TYPE POR STATE DESCRIPTION
NAME NO.
PP_HV 33 High Current Power N/A HV supply for VBUS. Bypass with capacitance CPP_HV to GND.
Tie pin to GND when unused
34
R_OSC 52 Digital Core I/O
and Control Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
RESETZ 21 Digital Core I/O
and Control Digital I/O Push-Pull Output (Low) General-purpose digital I/O 9. Active low reset output when VIN_3V3 is low (driven low on start-up). Float pin when unused.
RPD_G1 12 Type-C Port Analog I/O Hi-Z Tie pin to C_CC1 when configured to receive power in dead-
battery or no-power condition. Tie pin to GND otherwise.
RPD_G2 16 Type-C Port Analog I/O Hi-Z Tie pin to C_CC2 when configured to receive power in dead-
battery or no-power condition. Tie pin to GND otherwise.
SENSEN 29 External HV FET
Control and Sense Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused.
SENSEP 30 External HV FET
Control and Sense Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused.
SPI_CLK 37 Digital Core I/O
and Control Digital Output Digital Input SPI serial clock. Connect pin directly to SPI Flash IC. Refer to the Boot Code section for more details on the SPI Flash.
SPI_MISO 35 Digital Core I/O
and Control Digital Input Digital Input SPI serial master input from slave. Tie pin to LDO_3V3 through a 3.3-kΩresistor.
SPI_MOSI 36 Digital Core I/O
and Control Digital Output Digital Input SPI serial master output to slave. Connect pin directly to SPI flash IC.
SPI_SSZ 39 Digital Core I/O
and Control Digital Output Digital Input SPI slave select. Tie pin to LDO_3V3 through a 3.3-kΩresistor.
SS 3 External HV FET
Control and Sense Analog Output Driven Low Soft Start. Tie pin to capacitance CSS to ground.
SWD_CLK 50 Port Multiplexer Digital Input Resistive Pull
High SWD serial clock. Float pin when unused.
SWD_DATA 49 Port Multiplexer Digital I/O Resistive Pull
High SWD serial data. Float pin when unused.
USB_RP_N 5 Port Multiplexer Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩand 5-MΩresistance
when unused.
USB_RP_P 4 Port Multiplexer Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩand 5-MΩresistance
when unused.
VBUS 17 High Current Power N/A 5-V output from PP_5V0. Input or output from PP_HV up to 20 V.
Bypass with capacitance CVBUS to GND.
18
VDDIO 42 Low Current Power N/A
VDD for I/O. Some I/Os are reconfigurable to be powered from
VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to
LDO_3V3. When not tied to LDO_3V3 and used as a supply
input, bypass with capacitance CVDDIO to GND.
VIN_3V3 53 Low Current Power N/A Supply for core circuitry and I/O. Bypass with capacitance
CVIN_3V3 to GND.
GND (Thermal Pad) Ground Ground Hi-Z Ground. Connect directly to ground plane in accordance with the guidelines listed in the Layout Guidelines section to achieve the
measured values in the Thermal Information table.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(3) The 24 V maximum is based on keeping HV_GATE1/2 at or below 30 V. Fast voltage transitions (<100 ns) can occur up to 30 V.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIInput voltage(2)
PP_CABLE, PP_5V0 –0.3 6
V
VIN_3V3 –0.3 3.6
SENSEP, SENSEN(3) –0.3 24
VDDIO –0.3 LDO_3V3 + 0.3
VIO Output voltage(2)
LDO_1V8A, LDO_1V8D, LDO_BMC, SS –0.3 2
V
LDO_3V3 –0.3 3.45
RESETZ, I2C _IRQ1Z, SPI_MOSI, SPI_CLK, SPI_SSZ, SWD_CLK –0.3 LDO_3V3 + 0.3
HV_GATE1, HV_GATE2 –0.3 30
HV_GATE1 (relative to SENSEP) –0.3 6
HV_GATE2 (relative to VBUS) –0.3 6
VIO I/O voltage(2)
PP_HV, VBUS (2) –0.3 24
V
I2C_SDA1, I2C_SCL1, SWD_DATA, SPI_MISO, USB_RP_P, USB_RP_N, AUX_N,
AUX_P, DEBUG1, DEBUG_CTL1, DEBUG_CTL2, GPIOn, MRESET, BUSPOWERZ,
GPIO0-8 –0.3 LDO_3V3 + 0.3
R_OSC –0.3 2
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches
Open) –2 6
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches
Closed) –0.3 6
C_CC1, C_CC2, RPD_G1, RPD_G2 –0.3 6
TJOperating junction temperature –40 125 °C
Tstg Storage temperature –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

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(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIInput voltage(1)
VIN_3V3 2.85 3.45
V
PP_5V0 4.75 5.5
PP_CABLE 2.95 5.5
PP_HV 4.5 22
VDDIO 1.7 3.45
VIO I/O voltage(1) VBUS 4 22 VC_USB_PT, C_USB_NT, C_USB_PB, C_USB_NB, C_SBU1, C_SBU2 –2 5.5
C_CC1, C_CC2 0 5.5
TAAmbient operating temperature –40 105 °C
TBOperating board temperature –40 120 °C
TJOperating junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC(1) TPS65981 UNITRTQ (VQFN)
56 PINS
RθJA Junction-to-ambient thermal resistance 25.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 9.3 °C/W
RθJB Junction-to-board thermal resistance 3.6 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3.5 °C/W
RθJC(bottom) Junction-to-case (bottom) thermal resistance 0.5 °C/W

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(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3,
the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.
7.5 Power Supply Requirements and Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL
VIN_3V3 Input 3.3-V supply 2.85 3.3 3.45 V
PP_CABLE Input voltage to power C_CC pins. This input is
also available to power core circuitry 2.95 5 5.5 V
VBUS Bidirection DC bus voltage. Output from the
TPS65981 or input to the TPS65981 4 5 22 V
PP_5V0 5-V supply input to power VBUS. This supply
does not power the TPS65981 4.75 5 5.5 V
VDDIO(1) Optional supply for I/O cells 1.7 3.45 V
INTERNAL
VLDO_3V3 DC 3.3 V generated internally by either a switch from VIN_3V3, an LDO from PP_CABLE, or an
LDO from VBUS 2.7 3.3 3.45 V
VDO_LDO3V3 Dropout voltage of LDO_3V3 from PP_CABLE ILOAD = 50 mA 250 mV
Dropout voltage of LDO_3V3 from VBUS 250 500 750 mV
VLDO_1V8D DC 1.8 V generated for internal digital circuitry 1.7 1.8 1.9 V
VLDO_1V8A DC 1.8 V generated for internal analog circuitry 1.7 1.8 1.9 V
VLDO_BMC DC voltage generated on LDO_BMC. Setting for
USB-PD 1.05 1.125 1.2 V
ILDO_3V3 DC current supplied by the 3.3-V LDOs. This includes internal core power and external load on
LDO_3V3 70 mA
ILDO_3V3EX External DC current supplied by LDO_3V3 30 mA
ILDO_1V8D DC current supplied by LDO_1V8D. This is intended for internal loads only but small external
loads may be added. 50 mA
ILDO_1V8DEX External DC current supplied by LDO_1V8D. 5 mA
ILDO_1V8A DC current supplied by LDO_1V8A. This is intended for internal loads only but small external
loads may be added. 20 mA
ILDO_1V8AEX External DC current supplied by LDO_1V8A. 5 mA
ILDO_BMC DC current supplied by LDO_BMC. This is
intended for internal loads only 5 mA
ILDO_BMCEX External DC current supplied by LDO_BMC 0 mA
VFWD_DROP Forward voltage drop across VIN_3V3 to
LDO_3V3 switch ILOAD = 50 mA 25 60 90 mV
RIN_3V3 Input switch resistance from VIN_3V3 to
LDO_3V3 VVIN_3V3 – VLDO_3V3 > 50 mV 0.5 1.1 1.75 Ω

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7.6 Power Supervisor Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UV_LDO3V3 Undervoltage threshold for LDO_3V3. Locks out 1.8-V
LDOs LDO_3V3 rising 2.2 2.325 2.45 V
UVH_LDO3V3 Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling 20 80 150 mV
UV_VBUS_LDO Undervoltage threshold for VBUS to enable LDO VBUS rising 3.35 3.75 3.95 V
UVH_VBUS_LDO Undervoltage hysteresis for VBUS to enable LDO VBUS falling 20 80 150 mV
UV_PCBL Undervoltage threshold for PP_CABLE PP_CABLE rising 2.5 2.625 2.75 V
UVH_PCBL Undervoltage hysteresis for PP_PCABLE PP_CABLE falling 20 50 80 mV
UV_5V0 Undervoltage threshold for PP_5V0 PP_5V0 rising 3.5 3.725 3.95 V
UVH_5V0 Undervoltage hysteresis for PP_P5V0 PP_5V0 falling 20 80 150 mV
OV_VBUS Overvoltage threshold for VBUS. This value is a 6-bit
programmable threshold VBUS rising 5 24 V
OVLSB_VBUS Overvoltage threshold step for VBUS. This value is the
LSB of the programmable threshold VBUS rising 328 mV
OVH_VBUS Overvoltage hysteresis for VBUS VBUS falling, % of OV_VBUS 0.9% 1.3% 1.7%
UV_VBUS Undervoltage threshold for VBUS. This value is a 6-bit
programmable threshold VBUS falling 2.5 18.21 V
UVLSB_VBUS Undervoltage threshold step for VBUS. This value is the
LSB of the programmable threshold VBUS falling 249 mV
UVH_VBUS Undervoltage hysteresis for VBUS VBUS rising, % of UV_VBUS 0.9% 1.3% 1.7%
UVR_RST3V3 Configurable under-voltage threshold for VRSTZ_3V3
rising. De-asserts RESETZ VIN_3V3 and VRSTZ_3V3 rising (default setting) 2.613 2.75 2.888 V
UVRH_RST3V3 Under-voltage hysteresis for VRST_3V3 falling. Asserts
RESETZ VIN_3V3 and VRSTZ_3V3 falling 30 50 mV
TUVRASSERT Delay from falling or MRESET assertion to RESETZ
asserting low 75 μs
TUVRDELAY Configurable delay from to RESETZ de-assertion 0 161.3 ms
(1) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code
also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity).
(2) Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active.
(3) Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and the
digital core is clocked at 4 MHz.
(4) Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all
core functionality active, and the digital core is clocked at 12 MHz.
7.7 Power Consumption Characteristics
Recommended operating conditions; TA= 25°C (Room temperature) unless otherwise noted(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVIN_3V3
Sleep(2) VIN_3V3 = VDDIO = 3.45 V, VBUS = 0,
PPCABLE = 0; 100-kHz oscillator running 62 µA
Idle (3) VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE = 0; 100-kHz oscillator running,
48-MHz oscillator running 2.5 mA
Active(4) VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz oscillator running,
48-MHz oscillator running 6.0 mA

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7.8 Cable Detection Characteristics
Recommended operating conditions; TA= -40 to 105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IH_CC_USB Source current through each C_CC pin when in a disconnected state and configured as a DFP advertising Default USB current to
a peripheral device 73.6 80 86.4 μA
IH_CC_1P5 Source current through each C_CC pin when in a disconnected
state when configured as a DFP advertising 1.5 A to a UFP 169 180 191 μA
IH_CC_3P0 Source current through each C_CC pin when in a disconnected
state and configured as a DFP advertising 3 A to a UFP. VIN_3V3 ≥3.135 V 303 330 356 μA
VD_CCH_USB Voltage threshold for detecting a DFP attach when configured as a UFP and the DFP is advertising Default USB current source
capability 0.15 0.2 0.25 V
VD_CCH_1P5 Voltage threshold for detecting a DFP advertising 1.5-A source
capability when configured as a UFP 0.61 0.66 0.7 V
VD_CCH_3P0 Voltage threshold for detecting a DFP advertising 3 A source
capability when configured as a UFP 1.169 1.23 1.29 V
VH_CCD_USB Voltage threshold for detecting a UFP attach when configured as a
DFP and advertising default USB current source capability. IH_CC = IH_CC_USB 1.473 1.55 1.627 V
VH_CCD_1P5 Voltage threshold for detecting a UFP attach when configured as a
DFP and advertising 1.5-A source capability IH_CC = IH_CC_1P5 1.473 1.55 1.627 V
VH_CCD_3P0 Voltage threshold for detecting a UFP attach when configured as a
DFP and advertising 3-A source capability. IH_CC = IH_CC_3P0
VIN_3V3 ≥3.135 V 2.423 2.55 2.67 V
VH_CCA_USB Voltage threshold for detecting an active cable attach when configured as a DFP and advertising default USB current
capability. 0.15 0.2 0.25 V
VH_CCA_1P5 Voltage threshold for detecting active cables attach when
configured as a DFP and advertising 1.5-A capability. 0.35 0.4 0.45 V
VH_CCA_3P0 Voltage threshold for detecting active cables attach when
configured as a DFP and advertising 3-A capability. 0.76 0.8 0.84 V
RD_CC Pull-down resistance through each C_CC pin when in a
disconnect state and configured as a UFP. LDO_3V3 powered. V = 1 V, 1.5 V 4.85 5.1 5.35 kΩ
RD_CC_OPEN Pull-down resistance through each C_CC pin when in a
disconnect state and configured as a UFP. LDO_3V3 powered. V = 0 V to LDO_3V3 500 kΩ
RD_DB Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when configured for
dead battery (RPD_Gn tied to C_CCn). LDO_3V3 unpowered
V = 1.5 V, 2 V
RPD_Gn tied to C_CCn 4.08 5.1 6.12 kΩ
RD_DB_OPEN Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when not configured for
dead battery (RPD_Gn tied to GND). LDO_3V3 unpowered
V = 1.5 V, 2 V
RPD_Gn tied to GND 500 kΩ
VTH_DB Threshold voltage of the pull-down FET in series with RD during
dead battery I_CC = 80 μA 0.5 0.9 1.2 V
R_RPD Resistance between RPD_Gn and the gate of the pull-down FET 25 50 85 MΩ

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(1) UI denotes the time to transmit an un-encoded data bit not the shortest high or low times on the wire after encoding with BMC. A single
data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the
transition at the start of the cell.
(2) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends to add capacitance to
bring the total pin capacitance to 300 pF for improved TX behavior.
(4) BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of NCOUNT
transitions occur at the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions,
the bus is declared idle.
(5) Broadband noise ingression is because of coupling in the cable interconnect.
7.9 USB-PD Baseband Signal Requirements and Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
PD_BITRATE PD data-bit rate 270 300 330 Kbps
UI(1) Unit interval (1/PD_BITRATE) 3.03 3.33 3.7 μs
CCBLPLUG(2) Capacitance for a cable plug (each plug on a cable can have up
to this value) 25 pF
ZCABLE Cable characteristic impedance 32 65 Ω
CRECEIVER(3) Receiver capacitance. Capacitance looking into C_CCn pin
when in receiver mode. 70 120 pF
TRANSMITTER
ZDRIVER TX output impedance. Source output impedance at the Nyquist frequency of USB2.0 low speed (750 kHz) while the source is
driving the C_CCn line. 33 75 Ω
TRISE Rise time. 10% to 90% amplitude points, minimum is under an
unloaded condition. Maximum set by TX mask. 300 ns
TFALL Fall time. 90% to 10% amplitude points, minimum is under an
unloaded condition. Maximum set by TX mask. 300 ns
RECEIVER
VRXTR Rx receive rising input threshold 605 630 655 mV
VRXTF Rx receive falling input threshold 450 470 490 mV
NCOUNT(4) Number of transitions for signal detection (number to count to
detect non-idle bus). 3
TTRANWIN(4) Time window for detecting non-idle bus. 12 20 μs
ZBMCRX Receiver input impedance
Does not include pull-up or
pull-down resistance from
cable detect. Transmitter is
Hi-Z.
10 MΩ
TRXFILTER(5) Rx bandwidth limiting filter. Time constant of a single pole filter
to limit broadband noise ingression 100 ns

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(1) VTXP voltage settings are determined by application code and the setting used must meet the needs of the application and adhere to
the USB-PD Specifications.
7.10 USB-PD TX Driver Voltage Adjustment Parameter
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted(1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VTXP0
TX transmit peak voltage
1.615 1.7 1.785 V
VTXP1 1.52 1.6 1.68 V
VTXP2 1.425 1.5 1.575 V
VTXP3 1.33 1.4 1.47 V
VTXP4 1.235 1.3 1.365 V
VTXP5 1.188 1.25 1.312 V
VTXP6 1.14 1.2 1.26 V
VTXP7 1.116 1.175 1.233 V
VTXP8 1.092 1.15 1.208 V
VTXP9 1.068 1.125 1.181 V
VTXP10 1.045 1.1 1.155 V
VTXP11 1.021 1.075 1.128 V
VTXP12 0.998 1.05 1.102 V
VTXP13 0.974 1.025 1.076 V
VTXP14 0.95 1 1.05 V
VTXP15 0.903 0.95 0.997 V
7.11 Port Power Switch Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS,
when configured as a source, must not exceed 12 µF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RPPCC PP_CABLE to C_CCn power switch resistance 312 mΩ
RPP5V PP_5V0 to VBUS power switch resistance 55 75 mΩ
RPPHV PP_HV to VBUS power switch resistance 95 135 mΩ
IHVACT Active quiescent current from PP_HV pin EN_HV = 1 1 mA
IHVSD Shutdown quiescent current from PP_HV pin EN_HV = 0 100 μA
IHVEXTACT Active quiescent current from SENSEP pin, Configured as source; EN_HV = 1 1 mA
Active quiescent current from VBUS pin Configured as sink; EN_HV = 1 3.5 mA
IHVEXTSD Shutdown quiescent current from SENSEP pin EN_HV = 0 40 μA
IPP5VACT Active quiescent current from PP_5V0 1 mA
IPP5VSD Shutdown quiescent current from PP_5V0 100 μA

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Port Power Switch Characteristics (continued)
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS,
when configured as a source, must not exceed 12 µF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) The settings are selected automatically by application code for the current limit required in the application.
(2) Specified for a 10-mΩRSENSE resistor and 10-mΩRSENSE application code setting. The values scale with a different RSENSE
resistance and application code setting.
ILIMHV(1)
PP_HV current limit, setting 0 1.007 1.118 1.330 A
PP_HV current limit, setting 1 1.258 1.398 1.638 A
PP_HV current limit, setting 2 1.51 1.678 1.945 A
PP_HV current limit, setting 3 1.761 1.957 2.153 A
PP_HV current limit, setting 5 2.013 2.237 2.46 A
PP_HV current limit, setting 6 2.265 2.516 2.768 A
PP_HV current limit, setting 7 2.516 2.796 3.076 A
PP_HV current limit, setting 8 2.768 3.076 3.383 A
PP_HV current limit, setting 9 3.02 3.355 3.691 A
PP_HV current limit, setting 10 3.271 3.635 3.998 A
PP_HV current limit, setting 11 3.523 3.914 4.306 A
PP_HV current limit, setting 12 3.775 4.194 4.613 A
PP_HV current limit, setting 13 4.026 4.474 4.921 A
PP_HV current limit, setting 14 4.278 4.753 5.228 A
PP_HV current limit, setting 15 4.529 5.033 5.536 A
PP_HV current limit, setting 16 5.033 5.592 6.151 A
ILIMHVEXT(2)(1)
PP_EXT current limit, setting 0 0.986 1.12 1.254 A
PP_EXT current limit, setting 1 1.231 1.399 1.567 A
PP_EXT current limit, setting 2 1.477 1.678 1.879 A
PP_EXT current limit, setting 3 1.761 1.957 2.153 A
PP_EXT current limit, setting 4 2.012 2.236 2.46 A
PP_EXT current limit, setting 5 2.263 2.515 2.767 A
PP_EXT current limit, setting 6 2.514 2.794 3.074 A
PP_EXT current limit, setting 7 2.765 3.073 3.381 A
PP_EXT current limit, setting 8 3.016 3.352 3.688 A
PP_EXT current limit, setting 9 3.267 3.631 3.995 A
PP_EXT current limit, setting 10 3.519 3.91 4.301 A
PP_EXT current limit, setting 11 3.77 4.189 4.608 A
PP_EXT current limit, setting 12 4.021 4.468 4.915 A
PP_EXT current limit, setting 13 4.272 4.747 5.222 A
PP_EXT current limit, setting 14 4.523 5.026 5.529 A
PP_EXT current limit, setting 15 5.025 5.584 6.143 A

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Port Power Switch Characteristics (continued)
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS,
when configured as a source, must not exceed 12 µF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(3) The current sense in the ADC does not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the
reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
(4) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ωto provide adequate response time to short circuit
events.
ILIMPP5V(1)
PP_5V0 current limit, setting 0 1.006 1.118 1.330 A
PP_5V0 current limit, setting 1 1.132 1.258 1.484 A
PP_5V0 current limit, setting 2 1.258 1.398 1.638 A
PP_5V0 current limit, setting 3 1.384 1.538 1.691 A
PP_5V0 current limit, setting 4 1.51 1.677 1.845 A
PP_5V0 current limit, setting 5 1.636 1.817 1.999 A
PP_5V0 current limit, setting 6 1.761 1.957 2.153 A
PP_5V0 current limit, setting 7 1.887 2.097 2.307 A
PP_5V0 current limit, setting 8 2.013 2.237 2.46 A
PP_5V0 current limit, setting 9 2.139 2.376 2.614 A
PP_5V0 current limit, setting 10 2.265 2.516 2.768 A
PP_5V0 current limit, setting 11 2.39 2.656 2.922 A
PP_5V0 current limit, setting 12 2.516 2.796 3.075 A
PP_5V0 current limit, setting 13 2.642 2.936 3.229 A
PP_5V0 current limit, setting 14 2.768 3.075 3.383 A
PP_5V0 current limit, setting 15 3.019 3.355 3.69 A
ILIMPPCC PP_CABLE current limit (highest setting) 0.6 0.75 0.9 A
PP_CABLE current limit (lowest setting) 0.35 0.45 0.55 A
IHV_ACC(3) PP_HV current sense accuracy
I = 100 mA, Reverse current
blocking disabled 3.25 5 6.75 A/V
I = 200 mA 4 5 6 A/V
I = 500 mA 4.4 5 5.6 A/V
I≥1 A 4.5 5 5.5 A/V
IHVEXT_ACC PP_EXT current sense accuracy (excluding
RSENSE accuracy)
I = 100 mA, RSENSE = 10 mΩ,
Reverse current blocking disabled 3.5 5 6.5 A/V
I = 200 mA, RSENSE = 10 mΩ4 5 6 A/V
I = 500 mA, RSENSE = 10 mΩ4.4 5 5.6 A/V
I≥1 A, RSENSE = 10 mΩ4.5 5 5.5 A/V
IPP5V_ACC(3) PP_5V0 current sense accuracy
I = 100 mA, Reverse current
blocking disabled 1.95 3 4.05 A/V
I = 200 mA 2.4 3 3.6 A/V
I = 500 mA 2.64 3 3.36 A/V
I≥1 A 2.7 3 3.3 A/V
IPPCBL_ACC PP_CABLE current sense accuracy
I = 100 mA 1 A/V
I = 200 mA 1 A/V
I = 500 mA 1 A/V
IGATEEXT(4) External gate-drive current on HV_GATE1 and
HV_GATE2 456μA
VGSEXT VGS voltage driving external FETs 4.5 7.5 V
TON_HV PP_HV path turn on time from enable to VBUS
= 95% of PP_HV voltage
Configured as a source or as a
sink with soft start disabled.
PP_HV = 20 V, CVBUS = 10 μF,
ILOAD = 100 mA
8 ms
TON_5V PP_5V0 path turn on time from enable to
VBUS = 95% of PP_5V0 voltage
Configured as a source or as a
sink with soft start disabled.
PP_5V0 = 5 V, CVBUS = 10 μF,
ILOAD = 100 mA
2.5 ms
TON_CC PP_CABLE path turn on time from enable to
C_CCn = 95% of the PP_CABLE voltage PP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA 2 ms

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Port Power Switch Characteristics (continued)
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS,
when configured as a source, must not exceed 12 µF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISS Soft-start charging current 5.5 7 8.5 μA
RSS_DIS Soft-start discharge resistance 0.6 1 1.4 kΩ
VTHSS Soft-start complete threshold 1.35 1.5 1.65 V
TSSDONE Soft-start complete time CSS = 220 nF 31.9 46.2 60.5 ms
VREVPHV Reverse current blocking voltage threshold for
PP_HV switch 2 6 10 mV
VREVPEXT Reverse current blocking voltage Threshold for
PP_EXT external switches 2 6 10 mV
VREV5V0 Reverse current blocking voltage threshold for
PP_5V0 switches 2 6 10 mV
VHVDISPD Voltage threshold above VIN at which the pull- down RHVDISPD on VBUS will disable during
a transition from PHV to 5V0
45 200 250 mV
VSAFE0V Voltage that is a safe 0 V per USB-PD
Specifications 0 0.8 V
TSAFE0V Voltage transition time to VSAFE0V 650 ms
VSO_HV Voltage on PP_HV or PP_HVEXT above which the PP_HV or PP_EXT to PP_5V0 transition on
VBUS will meet transition requirements
9.9 V
SRPOS Maximum slew rate for positive voltage
transitions 0.03 V/μs
SRNEG Maximum slew rate for negative voltage
transitions –0.03 V/μs
TSTABLE EN to stable time for both positive and negative
voltage transitions 275 ms
VSRCVALID Supply output tolerance beyond VSRCNEW
during time TSTABLE –0.5 0.5 V
VSRCNEW Supply output tolerance –5 5 %
(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum
difference between the two switches in a pair. ROND does not add to RON.
7.12 Port Data Multiplexer Switching Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWD MULTIPLEXER PATH(1)
SWD_RON_U On resistance of SWD_DATA/CLK to
C_USB_TP/TN/BP/BN Vi= 3.3 V, IO= 20 mA 35 55 Ω
Vi= 1 V, IO= 20 mA 30 46
SWD_ROND_U On resistance difference between P and N paths of
SWD_DATA/CLK to C_USB_ TP/TN/BP/BN Vi= 1 V to 3.3 V, IO= 20 mA –2.5 2.5 Ω
SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2 Vi= 3.3 V, IO= 20 mA 26 42 Ω
Vi= = 1 V, IO= 20 mA 24 37
SWD_ROND_S On resistance difference between P and N paths of
SWD_DATA/CLK to C_SBU1/2 Vi= 1 V to 3.3 V, IO= 20 mA –1.5 1.5 Ω
SWD_TON Switch-on time from enable of SWD path
Time from enable bit with charge
pump off 150
μs
Time from enable bit at charge-
pump steady state 10
SWD_TOFF Switch-off time from disable of SWD path Time from disable bit at charge-
pump steady state 500 ns
SWD_BW 3-dB bandwidth of SWD path CL= 10 pF 200 MHz
DEBUG1 MULTIPLEXER PATH
DB1_RON_U On resistance DEBUG1 to C_USB_TP/BP Vi= 3.3 V, IO= 20 mA 14 26 Ω
Vi= 1 V, IO= 20 mA 10 17
DB1_RON_S On resistance of DEBUG1 to C_SBU1 Vi= 3.3 V, IO= 20 mA 9.5 17 Ω
Vi= 1 V, IO= 20 mA 6.5 12

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Port Data Multiplexer Switching Characteristics (continued)
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(2) See Port Data Multiplexer USB Endpoint Requirements and Characteristics for the USB_EP specifications.
DB1_TON Switch-on time from enable of DEBUG path
Time from enable bit with charge
pump off 150
μs
Time from enable bit at charge-
pump steady state 10
DB1_TOFF Switch-off time from disable of DEBUG path Time from disable bit at charge-
pump steady state 500 ns
DB1_BW 3-dB bandwidth of DEBUG path CL= 10 pF 200 MHz
AUX MULTIPLEXER PATH(1)
AUX_RON On resistance of AUX_P/N to C_SBU1/2 Vi= 3.3 V, IO= 20 mA 3.5 7 Ω
Vi= 1 V, IO= 20 mA 2.5 5
AUX_ROND On resistance difference between P and N paths of
AUX_P/N to C_SBU1/2 Vi= 1 V to 3.3 V, IO= 20 mA –0.25 0.25 Ω
AUX_TON Switch-on time from enable of AUX_P/N to C_SBU1/2
Time from enable bit with charge
pump off 150
μs
Time from enable bit at charge-
pump steady state 15
AUX_TOFF Switch-off time from disable of AUX_P/N to C_SBU1/2 Time from disable bit at charge-
pump steady state 500 ns
AUX_BW 3-dB bandwidth of AUX_P/N to C_SBU1/2 path CL= 10 pF 200 MHz
USB_RP MULTIPLEXER PATH(1)(2)
USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN Vi= 3 V, IO= 20 mA 4.5 10 Ω
Vi= 400 mV, IO= 20 mA 3 7
USB_ROND On resistance difference between P and N paths of
USB_RP to C_USB_TP/TN/BP/BN Vi= 0.4 V to 3 V, IO= 20 mA –0.15 0.15 Ω
USB_TON Switch-on time from enable of USB USB_RP path
Time from enable bit with charge
pump off 150 µs
Time from enable bit at charge-
pump steady state 15
USB_TOFF Switch-off time from disable of USB_RP path Time from disable bit at charge-
pump steady state 500 ns
USB_BW 3-dB bandwidth of USB_RP path CL= 10 pF 850 MHz
USB_ISO Off isolation of USB_RP path RL= 50 Ω, VI= 800 mV, f = 240
MHz –19 dB
USB_XTLK Channel to channel crosstalk of USB_RP path RL= 50 Ω, f = 240 MHz –26 dB
C_SBU1/2 OUTPUT
R_SBU_OPEN Resistance of the open C_SBU1/2 paths Vi= 0 V to LDO_3V3 1 MΩ
R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths Vi= 0 V to LDO_3V3 1 MΩ
(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time
may be longer.
7.13 Port Data Multiplexer Clamp Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCLMP_IND Clamp voltage triggering indicator to digital core 3.8 3.95 4.1 V
ICLMP_IND Clamp current at VCLMP_IND 10 250 μA
TCLMP_PRT(1) Time from clamp current crossing ICLMP_IND to
interrupt signal assertion I≥ICLMP_IND rising 0 4 μs
ICLMP USB_EP and USB_RP port clamp current V = LDO_3V3 250 nA
V = VCLMP_IND + 500 mV 3.5 15 mA

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7.14 Port Data Multiplexer SBU Detection Requirements
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH_PORT Port-switch detect input-high voltage LDO_3V3 = 3.3 V 2. v
VIL_PORT Port-switch detect input-low voltage LDO_3V3 = 3.3 V 0.8 V
7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RPU05 500-Ωpull-up and pull-down resistance LDO_3V3 = 3.3 V 350 500 650 Ω
RTPU5 5-kΩpull-up and pull-down resistance LDO_3V3 = 3.3 V 3.5 5 6.5 kΩ
RPU100 100-kΩpull-up and pull-down resistance LDO_3V3 = 3.3 V 70 100 130 kΩ
(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for
VIN_3V3 ≥3.135 V
7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSMITTER(1)
T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns
T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns
T_RRM_EP Rise and fall time matching Low-speed (1.5 Mbps) data rate only –20% 25%
V_XOVER_EP Output crossover voltage 1.3 2 V
RS_EP Source resistance of driver including 2nd-stage port-
data multiplexer 34 Ω
DIFFERENTIAL RECEIVER (1)
VOS_DIFF_EP Input offset –100 100 mV
VIN_CM_EP Common-mode range 0.8 2.5 V
RPU_EP D–bias resistance Receiving 1.425 1.575 kΩ
SINGLE ENDED RECEIVER(1)
VTH_SE_EP Single ended threshold Signal rising and falling 0.8 2 V
VHYS_SE_EP Single ended threshold hysteresis Signal falling 200 mV
7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA CONTACT DETECT
IDP_SRC DCD source current LDO_3V3 = 3.3 V 7 10 13 μA
RDM_DWN DCD pull-down resistance 14.25 20 24.8 kΩ
VLGC_HI Threshold for no connection VC_USB_TP/BP ≥ VLGC_HILDO_3V3 = 3.3 V
LDO_3V3 = 3.3 V 2 V
VLGC_LO Threshold for connection VC_USB_TP/BP ≤VLGC_LO
LDO_3V3 = 3.3 V 0.8 V
PRIMARY AND SECONDARY DETECT
VDX_SRC Source voltage 0.55 0.6 0.65 V
VDX_RSRC Total series resistance because of port data
multiplexer VDX_SRC = 0.65 V 65 Ω
VDX_ILIM VDX_SRC current limit 250 400 μA
IDX_SNK Sink current VC_USB_TN/BN ≥250 mV 25 75 125 μA

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7.18 Analog-to-Digital Converter (ADC) Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RES_ADC ADC current 10 bits
F_ADC ADC clock frequency 1.477 1.5 1.523 MHz
T_ENA ADC enable time 42.14 43 43.86 μs
T_SAMPLEA ADC input sample time 10.5 10.67 10.9 μs
T_CONVERTA ADC conversion time 7.88 8 8.12 μs
T_INTA ADC interrupt time 1.31 1.33 1.45 μs
LSB Least significant bit 1.152 1.17 1.188 mV
DNL Differential non-linearity –0.65 0.65 LSB
INL Integral non-linearity –1.2 1.2 LSB
GAIN_ERR Gain error (divider) –1.5% 1.5%
Gain error (no divider) –1 1
VOS_ERR Buffer offset error –10 10 mV
THERM_ACC Thermal sense accuracy –8 8 °C
THERM_GAIN Thermal slope 3.095 mV/°C
THERM_V0 Zero degree voltage 0.823 V
7.19 Input-Output (I/O) Requirements and Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SPI
SPI_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SPI_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SPI_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
SPI_ILKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 1 μA
SPI_VOH SPI output-high voltage IO= –8 mA, LDO_3V3=3.3 V 2.9 V
IO= –15 mA, LDO_3V3=3.3 V 2.5
SPI_VOL SPI output-low voltage IO= 10 mA 0.4 V
IO= 20 mA 0.8
SWDIO
SWDIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SWDIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SWDIO_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
SWDIO_ILKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 1 μA
SWDIO_VOH Output high voltage IO= –8 mA, LDO_3V3 = 3.3 V 2.9 V
IO= –15 mA, LDO_3V3 = 3.3 V 2.5
SWDIO_VOL Output low voltage IO= 10 mA 0.4 V
IO= 20 mA 0.8
SWDIO_RPU Pull-up resistance 2.8 4 5.2 kΩ
SWDIO_TOS SWDIO output skew to falling edge SWDCLK –5 5 ns
SWDIO_TIS Input setup time required between SWDIO and rising
edge of SWCLK 6 ns
SWDIO_TIH Input hold time required between SWDIO and rising edge
of SWCLK 1 ns
SWDCLK
SWDCL_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SWDCL_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SWDCL_THI SWDIOCLK HIGH period 0.05 500 μs
SWDCL_TLO SWDIOCLK LOW period 0.05 500 μs
SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

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Product Folder Links: TPS65981
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Input-Output (I/O) Requirements and Characteristics (continued)
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) DEBUG_CTL1/2 do not have an internal pull-down resistance path.
SWDCL_RPU Pull-up resistance 2.8 4 5.2 kΩ
GPIO (GPIO0, GPIO2-8, DEBUG1, DEBUG_CTL1/2, MRESET, RESETZ, BUSPOWERZ)
GPIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
VDDDIO = 1.8 V 1.25
GPIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
VDDIO = 1.8 V 0.63
GPIO_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
VDDIO = 1.8 V 0.09
GPIO_ILKG I/O leakage current Pin is Hi-Z; VIN = 0 V to VDD (VDDIO or
LDO_3V3) –1 1 μA
GPIO_RPU Pull-up resistance (GPIO0, GPIO2-8, DEBUG1,
MRESET, RESETZ, BUSPOWERZ) Pull-up enabled 50 100 150 kΩ
Pull-up resistance (DEBUG_CTL1/2) 2.5 5 7.5
GPIO_RPD Pull-down resistance (GPIO0, GPIO2-8, DEBUG1,
MRESET, RESETZ, BUSPOWERZ)(1) Pull-down enabled 50 100 150 kΩ
GPIO_DG Digital input path de-glitch 20 ns
GPIO_VOH GPIO output-high voltage IO= –2 mA, LDO_3V3 = 3.3 V 2.9 V
IO= –2 mA, VDDIO = 1.8 V 1.35
GPIO_VOL GPIO output-low voltage IO= 2 mA, LDO_3V3 = 3.3 V 0.4 V
IO= 2 mA, VDDIO = 1.8 V 0.45
I2C_IRQZ
OD_VOL Low-level output voltage IOL = 2 mA 0.4 V
OD_LKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 1 μA
SBU
SBU_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SBU_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SBU_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
7.20 I2C Slave Requirements and Characteristics
Recommended operating conditions; TA= –40°C to +105°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA AND SCL COMMON CHARACTERISTICS
ILEAK Input leakage current Voltage on Pin = LDO_3V3 -3 3 μA
VOL SDA output low voltage IOL = 3 mA, LDO_3V3 = 3.3 V 0.4 V
IOL = 3 mA, VDDIO = 1.8 V 0.36
IOL SDA max output low current VOL = 0.4 V 3 mA
VOL = 0.6 V 6
VIL Input low signal LDO_3V3 = 3.3 V 0.99 V
VDDIO = 1.8 V 0.54
VIH Input high signal LDO_3V3 = 3.3 V 2.31 V
VDDIO = 1.8 V 1.26
VHYS Input Hysteresis LDO_3V3 = 3.3 V 0.17 V
VDDIO = 1.8 V 0.09
TSP I2C pulse width suppressed 50 ns
CI Pin Capacitance 10 pF
SDA AND SCL STANDARD MODE CHARACTERISTICS
FSCL I2C clock frequency 0 100 kHz
THIGH I2C clock high time 4μs