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  9. Texas Instruments TPS65987D User manual

Texas Instruments TPS65987D User manual

TPS65987D USB Type-C® and USB PD Controller with Integrated Source and Sink
Power Path Supporting USB3 and Alternate Mode
1 Features
• This device is certified by the USB-IF for PD3.0
– PD3.0 silicon is required for certification of new
USB PD designs
• TID#: 1067
– Article on PD2.0 vs. PD3.0
• TPS65987D is a fully configurable USB PD device
controller:
– Ability to source and sink up to 20 V/5 A
– Alternate mode support
• DisplayPort
– Control for external DC/DC supplies, high
speed data muxes, and other peripheral
devices through either GPIO or I2C
• Ex: TPS65987EVM
• Ex: TIDA-050012
– GUI tool to easily configure TPS65987D for
various applications: TPS65988X-CONFIG
– Power management
• Power supply from 3.3 V or VBUS source
• 3.3-V LDO output for dead battery support
– For a more extensive selection guide and
getting started information, please refer to
www.ti.com/usb-c and E2E guide
• Integrated fully managed power paths:
– Two integrated 20-V, 5-A, 25-mΩ source or sink
load switch
– UL 2367 cert #: 20190107-E169910
– IEC 62368-1 cert #: US-34617-UL
• Integrated robust power path protection
– Integrated reverse current protection,
undervoltage protection, overvoltage protection,
and slew rate control for both 20-V/5-A power
paths when configured to Sink
– Integrated undervoltage protection, overvoltage
protection, and current limiting for inrush
current protection for both 20-V/5-A power
paths when configured to Source
• USB Type-C® Power Delivery (PD) controller
– 13 configurable GPIOs
– BC1.2 charging support
– USB PD 3.0 certified
– USB Type-C specification certified
– Cable attach and orientation detection
– Integrated VCONN switch
– Physical layer and policy engine
– 3.3-V LDO output for dead battery support
– Power supply from 3.3 V or VBUS source
– 1 I2C primary or secondary port
– 1 I2C primary only port
– 1 I2C secondary only port
2 Applications
•Single board computer
•Power tools, power banks, retail automation and
payment
•Wireless speakers, headphones
• Other personal electronics and industrial
applications
•Docking station
•Flat panel monitor
3 Description
The TPS65987D is a stand-alone USB Type-C and
Power Delivery (PD) controller providing cable plug
and orientation detection for a single USB Type-C
connector. Upon cable detection, the TPS65987D
communicates on the CC wire using the USB
PD protocol. When cable detection and USB PD
negotiation are complete, the TPS65987D enables
the appropriate power path and configures alternate
mode settings for external multiplexers.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS65987D QFN (RSH56) 7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Host Host
Interface
Alternate Mode Mux Ctrl
TPS65987D
CC
VCONN
VBUS
GND
CC1/2
5 A
5 A
SuperSpeed Mux/Retimer
3.3 V
5-20 V
5-20 V
2
Type-C Cable Detection
and
USB PD Controller USB
Type-C
Connector
D+/-
2
USB P/N
BC1.2
GPIO or I2C
Simplified Schematic
TPS65987D
SLVSES1D – MAY 2018 – REVISED OCTOBER 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................8
6.5 Power Supply Requirements and Characteristics.......8
6.6 Power Consumption Characteristics...........................9
6.7 Power Switch Characteristics..................................... 9
6.8 Cable Detection Characteristics................................11
6.9 USB-PD Baseband Signal Requirements and
Characteristics.............................................................12
6.10 BC1.2 Characteristics............................................. 13
6.11 Thermal Shutdown Characteristics......................... 14
6.12 Oscillator Characteristics........................................ 14
6.13 I/O Characteristics.................................................. 14
6.14 PWM Driver Characteristics....................................15
6.15 I2C Requirements and Characteristics....................15
6.16 SPI Controller Timing Requirements.......................16
6.17 HPD Timing Requirements..................................... 16
6.18 Typical Characteristics............................................ 17
7 Parameter Measurement Information.......................... 18
8 Detailed Description......................................................19
8.1 Overview................................................................... 19
8.2 Functional Block Diagram......................................... 20
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................42
9 Application and Implementation.................................. 45
9.1 Application Information............................................. 45
9.2 Typical Application.................................................... 45
10 Power Supply Recommendations..............................55
10.1 3.3-V Power............................................................ 55
10.2 1.8-V Power............................................................ 55
10.3 Recommended Supply Load Capacitance..............55
11 Layout........................................................................... 56
11.1 Layout Guidelines................................................... 56
11.2 Layout Example...................................................... 56
11.3 Component Placement............................................57
11.4 Routing PP_HV1/2, VBUS, PP_CABLE,
VIN_3V3, LDO_3V3, LDO_1V8.................................. 58
11.5 Routing CC and GPIO.............................................59
11.6 Thermal Dissipation for FET Drain Pads.................60
11.7 USB2 Recommended Routing For BC1.2
Detection/Advertisement............................................. 62
12 Device and Documentation Support..........................65
12.1 Device Support....................................................... 65
12.2 Receiving Notification of Documentation Updates..65
12.3 Support Resources................................................. 65
12.4 Trademarks............................................................. 65
12.5 Electrostatic Discharge Caution..............................65
12.6 Glossary..................................................................65
13 Mechanical, Packaging, and Orderable
Information.................................................................... 66
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2021) to Revision D (October 2022) Page
• Updated pin image to read Pin 36: SPI_POCI (GPIO8) and Pin 37: SPI_PICO (GPIO9).................................. 3
Changes from Revision B (January 2019) to Revision C (August 2021) Page
• Updated the Features list....................................................................................................................................1
• Updated the numbering format for tables, figures and cross-references throughout the document ..................1
• Globally changed instances of legacy terminology to controller and peripheral where SPI is mentioned.......... 1
• Updated the Applications section....................................................................................................................... 1
Changes from Revision A (August 2018) to Revision B (January 2019) Page
• Changed Pin Description to better clarify that VBUS1 and VBUS2 should be tied together ............................. 3
• Changed Figure 9-1 and Figure 11-1 to use the Correct Pin Numbers ........................................................... 45
Changes from Revision * (May 2018) to Revision A (August 2018) Page
• Changed status from Advance Information to Production Data..........................................................................1
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5 Pin Configuration and Functions
PP_HV2 -1
PP_HV2 -2
VBUS2 -3
VBUS2 -4
VIN_3V3 -5
ADCIN1 -6
DRAIN2 -7
DRAIN1 -8
LDO_3V3 -9
ADCIN2 -10
PP_HV1 -11
PP_HV1 -12
VBUS1 -13
VBUS1 -14
42- GPIO14 (PWM)
41- GPIO13
40- GPIO12
39- SPI_CS (GPIO11)
38- SPI_CLK (GPIO10)
37- SPI_PICO (GPIO9)
36- SPI_POCI (GPIO8)
35- LDO_1V8
34- I2C2_IRQ
33- I2C2_SDA
32- I2C2_SCL
31- HPD2 (GPIO4)
30- HPD1 (GPIO3)
29- I2C1_IRQ
28- I2C1_SDA
27- I2C1_SCL
26- C1_CC2
25- PP1_CABLE
24- C1_CC1
23- I2C3_IRQ (GPIO7)
22- I2C3_SDA (GPIO6)
21- I2C3_SCL (GPIO5)
20- GND
19- DRAIN1
18- GPIO2
17- GPIO1
16- GPIO0
15- DRAIN1
43- GPIO15 (PWM)
44- HRESET
45- C2_CC1
46- PP2_CABLE
47- C2_CC2
48- GPIO16 (PEXT1)
49- GPIO17 (PEXT2)
50- C1_USB_P (GPIO18)
51- GND
52- DRAIN2
53- C1_USB_N (GPIO19)
54- C2_USB_P (GPIO20)
55- C2_USB_N (GPIO21)
56- DRAIN2
57
DRAIN2
58
DRAIN1
59
GND
Figure 5-1. RSH Package 56-Pin QFN Top View
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Table 5-1. Pin Functions
PIN TYPE(2) RESET STATE(1) DESCRIPTION
NAME NO.
ADCIN1 6 I Input Boot configuration Input. Connect to resistor
divider between LDO_3V3 and GND.
ADCIN2 10 I Input I2C address configuration Input. Connect to
resistor divider between LDO_3V3 and GND.
C_CC1 24 I/O High-Z Output to Type-C CC or VCONN pin . Filter noise
with capacitor to GND
C_CC2 26 I/O High-Z Output to Type-C CC or VCONN pin . Filter noise
with capacitor to GND
C_USB_N (GPIO19) 53 I/O Input (High-Z) USB D– connection for BC1.2 support
C_USB_P (GPIO18) 50 I/O Input (High-Z) USB D+ connection for BC1.2 support
DRAIN1 8, 15, 19, 58 — —
Drain of internal power path 1. Connect thermal
pad 58 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad
DRAIN2 7, 52, 56, 57 — —
Drain of internal power path 2. Connect thermal
pad 57 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad
GND 20, 45 , 46, 47, 51 — — Unused pin. Tie to GND.
GPIO0 16 I/O Input (High-Z)
General Purpose Digital I/O 0. Float pin
when unused. GPIO0 is asserted low during
the TPS65987D boot process. Once device
configuration and patches are loaded GPIO0 is
released
GPIO1 17 I/O Input (High-Z) General Purpose Digital I/O 1. Ground pin with a
1-MΩ resistor when unused in the application
GPIO2 18 I/O Input (High-Z) General Purpose Digital I/O 2. Float pin when
unused
GPIO3 (HPD) 30 I/O Input (High-Z)
General Purpose Digital I/O 3. Configured as Hot
Plug Detect (HPD) TX and RX when DisplayPort
alternate mode is enabled. Float pin when unused
GPIO4 31 I/O Input (High-Z) General Purpose Digital I/O 4. Float pin when
unused
I2C3_SCL (GPIO5) 21 I/O Input (High-Z)
I2C port 3 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used. Float pin when unused
I2C3_SDA (GPIO6) 22 I/O Input (High-Z)
I2C port 3 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used.
Float pin when unused
I2C3_IRQ (GPIO7) 23 I/O Input (High-Z)
I2C port 3 interrupt detection (port 3 operates
as an I2C Master Only). Active low detection.
Connect to the I2C slave's interrupt line to detect
when the slave issues an interrupt. Float pin when
unused
GPIO12 40 I/O Input (High-Z) General Purpose Digital I/O 12. Float pin when
unused
GPIO13 41 I/O Input (High-Z) General Purpose Digital I/O 13. Float pin when
unused
GPIO14 (PWM) 42 I/O Input (High-Z) General Purpose Digital I/O 14. May also function
as a PWM output. Float pin when unused
GPIO15 (PWM) 43 I/O Input (High-Z) General Purpose Digital I/O 15. May also function
as a PWM output. Float pin when unused
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Table 5-1. Pin Functions (continued)
PIN TYPE(2) RESET STATE(1) DESCRIPTION
NAME NO.
GPIO16 (PP_EXT1) 48 I/O Input (High-Z)
General Purpose Digital I/O 16. May also function
as single wire enable signal for external power
path 1. Pull-down with external resistor when used
for external path control. Float pin when unused
GPIO17 (PP_EXT2) 49 I/O Input (High-Z)
General Purpose Digital I/O 17. May also function
as single wire enable signal for external power
path 2. Pull-down with external resistor when used
for external path control. Float pin when unused
GPIO20 54 I/O Input (High-Z) General Purpose Digital I/O 20. Float pin when
unused
GPIO21 55 I/O Input (High-Z) General Purpose Digital I/O 21. Float pin when
unused
HRESET 44 I/O Input
Active high hardware reset input. Will reinitialize
all device settings. Ground pin when HRESET
functionality will not be used
I2C1_IRQ 29 O High-Z
I2C port 1 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused
I2C1_SCL 27 I/O High-Z
I2C port 1 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used or unused
I2C1_SDA 28 I/O High-Z
I2C port 1 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used
or unused
I2C2_IRQ 34 O High-Z
I2C port 2 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused
I2C2_SCL 32 I/O High-Z
I2C port 2 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used or unused
I2C2_SDA 33 I/O High-Z
I2C port 2 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used
or unused
LDO_1V8 35 PWR — Output of the 1.8-V LDO for internal circuitry.
Bypass with capacitor to GND
LDO_3V3 9 PWR —
Output of the VBUS to 3.3-V LDO or connected
to VIN_3V3 by a switch. Main internal supply rail.
Used to power external flash memory. Bypass with
capacitor to GND
PP_CABLE 25 PWR — 5-V supply input for port 1 C_CC pins. Bypass with
capacitor to GND
PP_HV1 11, 12 PWR —
System side of first VBUS power switch. Bypass
with capacitor to ground. Tie to ground when
unused
PP_HV2 1, 2 PWR —
System side of second VBUS power switch.
Bypass with capacitor to ground. Tie to ground
when unused
SPI_CLK 38 I/O Input SPI serial clock. Ground pin when unused
SPI_POCI 36 I/O Input SPI serial controller input from peripheral. Ground
pin when unused
SPI_PICO 37 I/O Input SPI peripheral serial controller output to slave.
Ground pin when unused
SPI_CS 39 I/O Input SPI chip select. Ground pin when unused
VBUS1 13, 14 PWR — Port side of first VBUS power switch. Bypass with
capacitor to ground. Tie to VBUS2
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Table 5-1. Pin Functions (continued)
PIN TYPE(2) RESET STATE(1) DESCRIPTION
NAME NO.
VBUS2 3, 4 PWR — Port side of second VBUS power switch. Bypass
with capacitor to ground. Tie to VBUS1
VIN_3V3 5 PWR — Supply for core circuitry and I/O. Bypass with
capacitor to GND
Thermal Pad (PPAD) 59 GND —
Ground reference for the device as well as thermal
pad used to conduct heat from the device. This
connection serves two purposes. The first purpose
is to provide an electrical ground connection for
the device. The second purpose is to provide a
low thermal-impedance path from the device die to
the PCB. This pad must be connected to a ground
plane
(1) Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.
(2) I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage(2) PP_CABLE –0.3 6 V
VIN_3V3 –0.3 3.6
Output voltage(2)
LDO_1V8 –0.3 2
VLDO_3V3 –0.3 3.6
I2Cx _IRQ, SPI_PICO, SPI_CLK, SPI_CS, SWD_CLK –0.3 LDO_3V3 + 0.3 (3)
I/O voltage (2)
PP_HVx, VBUSx –0.3 24
V
I2Cx_SDA, I2Cx_SCL, SPI_POCI, GPIOn, HRESET, ADCINx –0.3 LDO_3V3 + 0.3 (3)
C_USB_P, C_USB_N –0.5 6
C_CC1, C_CC2 –0.5 6
Operating junction temperature, TJ–10 125 °C
Operating junction temperature PPHV switch, TJ–10 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to underside power pad. The underside power pad should be directly connected to the ground plane
of the board.
(3) Not to exceed 3.6V
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1) ±1500
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
Input voltage, VI (1)
VIN_3V3 3.135 3.45
VPP_CABLE 2.95 5.5
PP_HV 4.5 22
I/O voltage, VIO (1)
VBUS 4 22
V
C_USB_P, C_USB_N 0 LDO_3V3
C_CC1, C_CC2 0 5.5
GPIOn, I2Cx_SDA, I2Cx_SCL, SPI, ADCIN1, ADCIN2 0 LDO_3V3
Operating ambient temperature, TA–10 75 °C
Operating junction temperature, TJ–10 125
(1) All voltage values are with respect to underside power pad. Underside power pad must be directly connected to ground plane of the
board.
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6.4 Thermal Information
THERMAL METRIC(1)
TPS65987
UNITRSH (QFN)
48 PINS
RθJA (2) Junction-to-ambient thermal resistance 57.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 65.4 °C/W
RθJB (2) Junction-to-board thermal resistance 30 °C/W
ψJT (2) Junction-to-top characterization parameter 34.1 °C/W
ψJB (2) Junction-to-board characterization parameter 29.9 °C/W
Rθ
JC(bot_Controller)
Junction-to-case (bottom GND pad) thermal resistance 0.7 °C/W
RθJC(bot_FET) Junction-to-case (bottom DRAIN 1/2 pad) thermal resistance 5.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal metrics are not JDEC standard values and are based on the TPS65988 evaluation board.
6.5 Power Supply Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL
VIN_3V3 Input 3.3-V supply 3.135 3.3 3.45 V
PP_CABLE Input to power Vconn output on C_CC
pins 2.95 5 5.5 V
PP_HV Source power from PP_HV to VBUS 4.5 5 22 V
VBUS Sink power from VBUS to PP_HV 4 5 22 V
CVIN_3V3 Recommended capacitance on the
VIN_3V3 pin
5 10 µF
CPP_CABLE Recommended capacitance on
PPx_CABLE pins
2.5 4.7 µF
CPP_HV_SRC Recommended capacitance on
PP_HVx pin when configured as a
source
2.5 4.7 µF
CPP_HV_SNK Recommended capacitance on
PP_HVx pin when configured as a
sink
1 47 120 μF
CVBUS Recommended capacitance on
VBUSx pins
0.5 1 12 μF
INTERNAL
VLDO_3V3
Output voltage of LDO from VBUS to
LDO_3V3
VIN_3V3 = 0 V, VBUS1 ≥ 4 V, 0 ≤
ILOAD ≤ 50mA 3.15 3.3 3.45 V
VDO_LDO_3V3
Drop out voltage of LDO_3V3 from
VBUS ILOAD = 50mA 250 500 850 mV
ILDO_3V3_EX
Allowed External Load current on
LDO_3V3 pin 25 mA
VLDO_1V8 Output voltage of LDO_1V8 0 ≤ ILOAD ≤ 20mA 1.75 1.8 1.85 V
VFWD_DROP
Forward voltage drop across VIN_3V3
to LDO_3V3 switch ILOAD = 50 mA 200 mV
CLDO_3V3 Recommended capacitance on
LDO_3V3 pin
5 10 25 μF
CLDO_1V8 Recommended capacitance on
LDO_1V8 pin
2.2 4.7 6 μF
SUPERVISORY
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6.5 Power Supply Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UV_LDO3V3 Undervoltage threshold for LDO_3V3.
Locks out 1.8-V LDOs LDO_3V3 rising 2.2 2.325 2.45 V
UVH_LDO3V3 Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling 20 80 150 mV
UV_PCBL Undervoltage threshold for
PP_CABLE PP_CABLE rising 2.5 2.625 2.75 V
UVH_PCBL Undervoltage hysteresis for
PP_PCABLE PP_CABLE falling 20 50 80 mV
OV_VBUS
Overvoltage threshold for VBUS.
This value is a 6-bit programmable
threshold
VBUS rising 5 24 V
OVLSB_VBUS
Overvoltage threshold step for VBUS.
This value is the LSB of the
programmable threshold
VBUS rising 328 mV
OVH_VBUS Overvoltage hysteresis for VBUS VBUS falling, % of OV_VBUS 1.4 1.65 1.9 %
UV_VBUS
Undervoltage threshold for VBUS.
This value is a 6-bit programmable
threshold
VBUS falling 2.5 18.21 V
UVLSB_VBUS
Undervoltage threshold step for
VBUS. This value is the LSB of the
programmable threshold
VBUS falling 249 mV
UVH_VBUS Undervoltage hysteresis for VBUS VBUS rising, % of UV_VBUS 0.9 1.3 1.7 %
6.6 Power Consumption Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVIN_3V3 (1)
Sleep (Sink) VIN_3V3 = 3.3 V, VBUS = 0 V, No
cable connected, Tj = 25C, configured
as sink, BC1.2 disabled
45 µA
Sleep (Source/DRP)
VIN_3V3 = 3.3 V, VBUS = 0 V, No
cable connected, Tj = 25C, configured
as source or DRP, BC1.2 disabled
55 µA
IVIN_3V3 (1) Idle (Attached) VIN_3V3 = 3.3 V, Cable connected,
No active PD communication, Tj = 25C
5 mA
IVIN_3V3 (1) Active VIN_3V3 = 3.3 V, Tj = 25C 8 mA
(1) Does not include current draw due to GPIO loading
6.7 Power Switch Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RPPCC
PP_CABLE to C_CCn power switch
resistance
4.7 ≤ PP_CABLE ≤ 5.5 222 325 mΩ
2.95 ≤ PP_CABLE < 4.7 269 414 mΩ
RPPHV
PP_HVx to VBUSx power switch
resistance Tj = 25C 25 33 mΩ
IPPHV
Continuous current capabillity of
power path from PP_HVx to VBUSx 5 A
IPPCC
Continuous current capabillity of
power path from PP_CABLE to
C_CCn
TJ = 125C 320 mA
TJ = 85C 600 mA
IHVACT
Active quiescent current from PP_HV
pin, EN_HV = 1
Source Configuration, Comparator
RCP function enabled, ILOAD = 100mA 1 mA
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6.7 Power Switch Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IHVSD
Shutdown quiescent current from
PP_HV pin, EN_HV = 0 VPPHV = 20V 100 µA
IOCC
Over Current Clamp Firmware
Selectable Settings
1.140 1.267 1.393 A
1.380 1.533 1.687 A
1.620 1.800 1.980 A
1.860 2.067 2.273 A
2.100 2.333 2.567 A
2.34 2.600 2.860 A
2.580 2.867 3.153 A
2.820 3.133 3.447 A
3.060 3.400 3.74 A
3.300 3.667 4.033 A
3.540 3.933 4.327 A
3.780 4.200 4.620 A
4.020 4.467 4.913 A
4.260 4.733 5.207 A
4.500 5.00 5.500 A
4.740 5.267 5.793 A
4.980 5.533 6.087 A
5.220 5.800 6.380 A
5.460 6.067 6.673 A
5.697 6.330 6.963 A
IOCP PP_HV Quick Response Current
Limit 10 A
ILIMPPCC PP_CABLE current limit 0.6 0.75 0.9 A
IHV_ACC 1 PP_HV current sense accuracy I = 100 mA, Reverse current blocking
disabled 3.9 6 8.1 A/V
IHV_ACC 1 PP_HV current sense accuracy I = 200 mA 4.8 6 7.2 A/V
IHV_ACC 1 PP_HV current sense accuracy I = 500 mA 5.28 6 6.72 A/V
IHV_ACC 1 PP_HV current sense accuracy I ≥ 1 A 5.4 6 6.6 A/V
tON_HV
PP_HV path turn on time from
enable to VBUS = 95% of PP_HV
voltage
Configured as a source or as a sink
with soft start disabled. PP_HV = 20 V,
CVBUS = 10 µF, ILOAD = 100 mA
8 ms
tON_FRS
PP_HV path turn on time from
enable to VBUS = 95% of PP_HV
voltage during an FRS enable
Configured as a source. PP_HV = 5 V,
CVBUS = 10 µF, ILOAD = 100 mA 150 μs
tON_CC
PP_CABLE path turn on time from
enable to C_CCn = 95% of the
PP_CABLE voltage
PP_CABLE = 5 V, C_CCn = 500 nF,
ILOAD = 100 mA 2 ms
SS Configurable soft start slew rate for
sink configuration
ILOAD = 100mA, setting 0 0.270 0.409 0.45 V/ms
ILOAD = 100mA, setting 1 0.6 0.787 1 V/ms
ILOAD = 100mA, setting 2 1.2 1.567 1.7 V/ms
ILOAD = 100mA, setting 3 2.3 3.388 3.6 V/ms
VREVPHV
Reverse current blocking voltage
threshold for PP_HV switch
Diode Mode 6 10 mV
Comparator Mode 3 6 mV
VSAFE0V
Voltage that is a safe 0 V per USB-
PD specification 0 0.8 V
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6.7 Power Switch Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSAFE0V Voltage transition time to VSAFE0V 650 ms
SRPOS Maximum slew rate for positive
voltage transitions 0.03 V/µs
SRNEG Maximum slew rate for negative
voltage transitions –0.03 V/µs
tSTABLE
EN to stable time for both positive
and negative voltage transitions 275 ms
VSRCVALID
Supply output tolerance beyond
VSRCNEW during time tSTABLE
–0.5 0.5 V
VSRCNEW Supply output tolerance –5 5 %
tVCONNDIS
Time from cable detach to
VVCONNDIS 250 ms
VVCONNDIS
Voltage at which VCONN is
considered discharged 150 mV
6.8 Cable Detection Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IH_CC_USB
Source Current through each C_CC pin when
in a disconnected state and Configured as a
Source advertising Default USB current to a
peripheral device
73.6 80 86.4 µA
IH_CC_1P5
Source Current through each C_CC pin when
in a disconnected state when Configured as a
Source advertising 1.5A to a UFP
165.6 180 194.4 µA
IH_CC_3P0
Source Current through each C_CC pin when
in a disconnected state and Configured as a
Source advertising 3.0A to a UFP.
VIN_3V3 ≥ 3.135 V, VCC < 2.6
V303.6 330 356.4 µA
VD_CCH_USB
Voltage Threshold for detecting a Source
attach when configured as a Sink and the
Source is advertising Default USB current
source capability
0.15 0.2 0.25 V
VD_CCH_1P5
Voltage Threshold for detecting a Source
advertising 1.5A source capability when
configured as a Sink
0.61 0.66 0.7 V
VD_CCH_3P0
Voltage Threshold for detecting a Source
advertising 3A source capability when
configured as a Sink
1.16 1.23 1.31 V
VH_CCD_USB
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
Default USB current source capability.
IH_CC = IH_CC_USB 1.5 1.55 1.65 V
VH_CCD_1P5
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
1.5A source capability
IH_CC = IH_CC_1P5 1.5 1.55 1.65 V
VH_CCD_3P0
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
3.0A source capability.
IH_CC = IH_CC_3P0
VIN_3V3 ≥ 3.135V 2.45 2.55 2.615 V
VH_CCA_USB
Voltage Threshold for detecting an active cable
attach when configured as a Source and
advertising Default USB current capability.
0.15 0.2 0.25 V
VH_CCA_1P5
Voltage Threshold for detecting active cables
attach when configured as a Source and
advertising 1.5A capability.
0.35 0.4 0.45 V
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6.8 Cable Detection Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VH_CCA_3P0
Voltage Threshold for detecting active cables
attach when configured as a Source and
advertising 3A capability.
0.75 0.8 0.85 V
RD_CC
Pulldown resistance through each C_CC pin
when in a disconnect state and configured as a
Sink. LDO_3V3 powered.
V = 1V, 1.5V 4.59 5.1 5.61 kΩ
RD_CC_OPEN
Pulldown resistance through each C_CC pin
when in a disabled state. LDO_3V3 powered. V = 0V to LDO_3V3 500 kΩ
RD_DB
Pulldown resistance through each C_CC pin
when LDO_3V3 unpowered V = 1.5V, 2.0V 4.08 5.1 6.12 kΩ
RFRSWAP Fast Role Swap signal pull down 5 Ω
VTH_FRS
Fast role swap request detection voltage
threshold 490 520 550 mV
6.9 USB-PD Baseband Signal Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
PD_BITRATE PD data bit rate 270 300 330 Kbps
UI (2) Unit interval (1/PD_BITRATE) 3.03 3.33 3.7 µs
CCBLPLUG (1)
Capacitance for a cable plug (each
plug on a cable may have up to this
value)
25 pF
ZCABLE Cable characteristic impedance 32 65 Ω
CRECEIVER (3)
Receiver capacitance. Capacitance
looking into C_CCn pin when in
receiver mode.
100 pF
TRANSMITTER
ZDRIVER
TX output impedance. Source
output impedance at the Nyquist
frequency of USB2.0 low speed
(750kHz) while the source is driving
the C_CCn line.
33 75 Ω
tRISE
Rise time. 10 % to 90 % amplitude
points, minimum is under an
unloaded condition. Maximum set
by TX mask.
300 ns
tFALL
Fall time. 90 % to 10 % amplitude
points, minimum is under an
unloaded condition. Maximum set
by TX mask.
300 ns
VTX Transmit high voltage 1.05 1.125 1.2 V
RECEIVER
VRXTR Rx receive rising input threshold Port configured as Source 840 875 910 mV
VRXTR Rx receive rising input threshold Port configured as Sink 504 525 546 mV
VRXTF Rx receive falling input threshold Port configured as Sink 240 250 260 mV
VRXTF Rx receive falling input threshold Port configured as Source 576 600 624 mV
NCOUNT
Number of transitions for signal
detection (number to count to
detect non-idle bus).
3
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6.9 USB-PD Baseband Signal Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TTRANWIN Time window for detecting non-idle
bus. 12 20 µs
ZBMCRX Receiver input impedance
Does not include pull-up or
pulldown resistance from cable detect.
Transmitter is Hi-Z.
5 MΩ
TRXFILTER (4)
Rx bandwidth limiting filter. Time
constant of a single pole filter to
limit broadband noise ingression
100 ns
(1) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(2) UI denotes the time to transmit an unencoded data bit not the shortest high or low times on the wire after encoding with BMC. A single
data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the
transition at the start of the cell.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends adding capacitance
to bring the total pin capacitance to 300 pF for improved TX behavior.
(4) Broadband noise ingression is because of coupling in the cable interconnect.
6.10 BC1.2 Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA CONTACT
DETECT
IDP_SRC DCD source current LDO_3V3 = 3.3 V 7 10 13 µA
RDM_DWN DCD pulldown resistance 14.25 20 24.8 kΩ
RDP_DWN DCD pulldown resistance 14.25 20 24.8 kΩ
VLGC_HI Threshold for no connection C_USB_P ≥ VLGC_HI, LDO_3V3 =
3.3 V 2 V
VLGC_LO Threshold for connection C_USB_P ≤ VLGC_LO 0.8 V
PRIMARY AND SECONDARY
DETECT
VDX_SRC Source voltage 0.55 0.6 0.65 V
VDX_ILIM VDX_SRC current limit 250 400 µA
IDX_SNK Sink Current VC_USB_TN/BN ≥ 250 mV 25 75 125 µA
RDCP_DAT Dedicated Charging Port Resistance 200 Ω
DIVIDER MODE
VCx_USB_P
_2.7V
Cx_USB_P Output Voltage No load on Cx_USB_P 2.57 2.7 2.79 V
VCx_USB_N
_2.7V
Cx_USB_N Output Voltage No load on Cx_USB_N 2.57 2.7 2.79 V
RCx_USB_P
_30k
Cx_USB_P Output Impedance 5µA pulled from Cx_USB_P pin 24 30 36 kΩ
RCx_USB_N
_30k
Cx_USB_N Output Impedance 5µA pulled from Cx_USB_N pin 24 30 36 kΩ
1.2V MODE
RCx_USB_N
_102k
Cx_USB_N Output Impedance 5µA pulled from Cx_USB_N pin 80 102 130 kΩ
VCx_USB_P
_1.2V
Cx_USB_P Output Voltage No load on Cx_USB_P 1.12 1.2 1.28 V
VCx_USB_N
_1.2V
Cx_USB_N Output Voltage No load on Cx_USB_N 1.12 1.2 1.28 V
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over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RCx_USB_P
_102k
Cx_USB_P Output Impedance 5µA pulled from Cx_USB_P pin 80 102 130 kΩ
6.11 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSD_MAIN
Thermal Shutdown Temperature of the
main thermal shutdown Temperature rising 145 160 175 °C
TSDH_MAIN
Thermal Shutdown hysteresis of the
main thermal shutdown Temperature falling 20 °C
TSD_PWR
Thermal Shutdown Temperature of the
power path block Temperature rising 145 160 175 °C
TSDH_PWR
Thermal Shutdown hysteresis of the
power path block Temperature falling 20 °C
6.12 Oscillator Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ƒOSC_24M 24-MHz oscillator 22.8 24 25.2 MHz
ƒOSC_100K 100-kHz oscillator 95 100 105 kHz
6.13 I/O Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SPI
SPI_VIH High-level input voltage LDO_1V8 = 1.8V 1.3 V
SPI_VIL Low input voltage LDO_1V8 = 1.8V 0.63 V
SPI_HYS Input hysteresis voltage LDO_1V8 = 1.8V 0.09 V
SPI_ILKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 -1 1 µA
SPI_VOH SPI output high voltage IO = –2 mA, LDO_3V3 = 3.3 V 2.88 V
SPI_VOL SPI output low voltage IO = 2 mA 0.4 V
SWDIO
SWDCLK
GPIO
GPIO_VIH High-level input voltage LDO_1V8 = 1.8 V 1.3 V
GPIO_VIL Low input voltage LDO_1V8 = 1.8 V 0.63 V
GPIO_HYS Input hysteresis voltage LDO_1V8 = 1.8 V 0.09 V
GPIO_ILKG I/O leakage current INPUT = 0 V to VDD –1 1 µA
GPIO_RPU Pullup resistance Pullup enabled 50 100 150 kΩ
GPIO_RPD Pulldown resistance Pulldown enabled 50 100 150 kΩ
GPIO_DG Digital input path deglitch 20 ns
GPIO_VOH GPIO output high voltage IO = –2 mA, LDO_3V3 = 3.3 V 2.88 V
GPIO_VOL GPIO output low voltage IO = 2 mA, LDO_3V3 = 3.3 V 0.4 V
I2C_IRQx
OD_VOL Low-level output voltage IOL = 2 mA 0.4 V
OD_LKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 1 µA
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6.14 PWM Driver Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
F_PWM PWM frequency PWM clock = 100kHz 391 6250 Hz
PWM clock = 24MHz 94 1500 kHz
FLSB_PWM
Frequency step for PWM driver. This
value is the LSB of the programmable
frequency
PWM clock = OSC_100K 391 Hz
PWM clock = OSC_24M 94 kHz
6.15 I2C Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA AND SCL COMMON
CHARACTERISTICS
ILEAK Input leakage current Voltage on Pin = LDO_3V3 –3 3 µA
VOL SDA output low voltage IOL = 3 mA, LDO_3V3 = 3.3 V 0.4 V
IOL SDA max output low current VOL = 0.4 V 3 mA
VOL = 0.6 V 6 mA
VIL Input low signal LDO_3V3 = 3.3 V 0.99 V
LDO_1V8 = 1.8 V 0.54 V
VIH Input high signal LDO_3V3 = 3.3 V 2.31 V
LDO_1V8 = 1.8 V 1.3 V
VHYS Input hysteresis LDO_3V3 = 3.3 V 0.17 V
LDO_1V8 = 1.8 V 0.09 V
tSP I2C pulse width suppressed 50 ns
CIPin capacitance 10 pF
SDA AND SCL STANDARD
MODE CHARACTERISTICS
ƒSCL I2C clock frequency 0 100 kHz
tHIGH I2C clock high time 4 µs
tLOW I2C clock low time 4.7 µs
tSU;DAT I2C serial data setup time 250 ns
tHD;DAT I2C serial data hold time 0 ns
tVD;DAT I2C valid data time SCL low to SDA output valid 3.45 µs
tVD;ACK I2C valid data time of ACK condition ACK signal from SCL low to SDA (out)
low 3.45 µs
tOCF I2C output fall time 10 pF to 400 pF bus 250 ns
tBUF
I2C bus free time between stop and
start 4.7 µs
tSU;STA
I2C start or repeated Start condition
setup time 4.7 µs
tHD;STA
I2C Start or repeated Start condition
hold time 4 µs
tSU;STO I2C Stop condition setup time 4 µs
SDA AND SCL FAST MODE
CHARACTERISTICS
ƒSCL I2C clock frequency Configured as Slave 0 400 kHz
ƒSCL_MASTER I2C clock frequency Configured as Master 0 320 400 kHz
tHIGH I2C clock high time 0.6 µs
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6.15 I2C Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLOW I2C clock low time 1.3 µs
tSU;DAT I2C serial data setup time 100 ns
tHD;DAT I2C serial data hold time 0 ns
tVD;DAT I2C Valid data time SCL low to SDA output valid 0.9 µs
tVD;ACK I2C Valid data time of ACK condition ACK signal from SCL low to SDA (out)
low 0.9 µs
tOCF I2C output fall time 10 pF to 400 pF bus, VDD = 3.3 V 12 250 ns
10 pF to 400 pF bus, VDD = 1.8 V 6.5 250 ns
tBUF
I2C bus free time between stop and
start 1.3 µs
tSU;STA
I2C start or repeated Start condition
setup time 0.6 µs
tHD;STA
I2C Start or repeated Start condition
hold time 0.6 µs
tSU;STO I2C Stop condition setup time 0.6 µs
6.16 SPI Controller Timing Requirements
MIN NOM MAX UNIT
ƒSPI Frequency of SPI_CLK 11.4 12 12.6 MHz
tPER Period of SPI_CLK (1/F_SPI) 79.36 83.33 87.72 ns
tWHI SPI_CLK high width 30 ns
tWLO SPI_CLK low width 30 ns
tDACT SPI_SZZ falling to SPI_CLK rising delay time 30 50 ns
tDINACT SPI_CLK falling to SPI_CSZ rising delay time 158 180 ns
tDPICO SPI_CLK falling to SPI_PICO Valid delay time –10 10 ns
tSUPOCI SPI_POCI valid to SPI_CLK falling setup time 33 ns
tHDMSIO SPI_CLK falling to SPI_POCI invalid hold time 0 ns
tRIN SPI_POCI input rise time 5 ns
tRSPI SPI_CSZ/CLK/PICO rise time 10% to 90%, CL = 5 to 50 pF, LDO_3V3 =
3.3 V 1 25 ns
tFSPI SPI_CSZ/CLK/PICO fall time 90% to 10%, CL = 5 to 50 pF, LDO_3V3 =
3.3 V 1 25 ns
6.17 HPD Timing Requirements
MIN NOM MAX UNIT
DP SOURCE SIDE (HPD
TX)
tIRQ_MIN HPD IRQ minimum assert time 675 750 825 µs
t2 MS_MIN HPD assert 2-ms min time 3 3.33 3.67 ms
DP SINK SIDE (HPD
RX)
tHPD_HDB HPD high debounce time HPD_HDB_SEL = 0 300 375 450 µs
HPD_HDB_SEL = 1 100 111 122 ms
tHPD_LDB HPD low debounce time 300 375 450 µs
tHPD_IRQ HPD IRQ limit time 1.35 1.5 1.65 ms
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6.18 Typical Characteristics
Temperature (°C)
Resistance (m:)
-20 0 20 40 60 80 100 120 140
22
24
26
28
30
32
D004
Figure 6-1. PPHVx Rdson vs Junction Temperature
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7 Parameter Measurement Information
002aac938
tf
70 %
30 %
SDA
tf
70 %
30 %
S
tr
70 %
30 %
70 %
30 %
t
SCL
HD;DAT
1 / f
1 clock cycle
SCL
st
70 %
30 %
70 %
30 %
tr
t
cont.
VD;DAT
cont.
SDA
SCL
tSU;STA tHD;STA
Sr
tSP tSU;STO
tBUF
P S
tHIGH
9 clock
th
tHD;STA tLOW
70 %
30 %
tVD;ACK
9 clock
th
tSU;DAT
Figure 7-1. I2C Slave Interface Timing
Valid Data
Valid Data
tdact
tper
tdpico tdpico
twhigh twlow
tsupoci
thdpoci
tdinact
SPI_CSZ
SPI_CLK
SPI_PICO
SPI_POCI
Figure 7-2. SPI Controller Timing
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8 Detailed Description
8.1 Overview
The TPS65987D is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug
and orientation detection for a USB Type-C and PD plug or receptacles. The TPS65987D communicates with the
cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power
switch, controls an external high current port power switch, and negotiates alternate modes . The TPS65987D
may also control an attached super-speed multiplexer via GPIO or I2C to simultaneously support USB3.0/3.1
data rates and DisplayPort video.
The TPS65987D is divided into five main sections: the USB-PD controller, the cable plug and orientation
detection circuitry, the port power switches, the power management circuitry, and the digital core.
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible
USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, see the USB-PD Physical Layer section.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and
orientation detection, a description of its features and more detailed circuitry, see the Cable Plug and Orientation
Detection section.
The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or
C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a
description of its features and more detailed circuitry, see the Port Power Switches section.
The power management circuitry receives and provides power to the TPS65987D internal circuitry and to the
LDO_3V3 output. For a high-level block diagram of the power management circuitry, a description of its features
and more detailed circuitry, see the Power Management section.
The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as
handling control of all other TPS65987D functionality. A portion of the digital core contains ROM memory which
contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the
ROM, called boot code, is capable of initializing the TPS65987D, loading of device configuration information, and
loading any code patches into volatile memory in the digital core. For a high-level block diagram of the digital
core, a description of its features and more detailed circuitry, see the Digital Core section.
The TPS65987D is an I2C slave to be controlled by a host processor (see the I2 Interfaces section), and an SPI
controller to write to and read from an optional external flash memory (see the SPI Controller Interface section).
The TPS65987D also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs off
of accurate clocks provided by the integrated oscillators (see the Oscillators section).
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8.2 Functional Block Diagram
Cable Detect &
USB-PD Phy
Cable Power
Core
&
Other Digital
Power & Supervisor
Charger
Detection &
Advertisement
6
2
3
5
2C_USB_P/N
C_CC1
C_CC2
VBUS1
PP_HV2
VIN_3V3
HRESET
LDO_3V3
LDO_1V8
ADCIN1
ADCIN2
GPIO0-4
GPIO12-17
GPIO20-21
I2C2_SDA/SCL/IRQ
PP_HV1
5 A
5 A
PPAD
VBUS2
PP_CABLE
600 mA
3
I2C3_SDA/SCL/IRQ
3
I2C1_SDA/SCL/IRQ
4
SPI_PICO/POCI/CS/CLK
8.3 Feature Description
8.3.1 USB-PD Physical Layer
Figure 8-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block.
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