Texas Instruments UCC28600 User manual

1
2
3
4
8
7
6
5
VCC
DRV
GND
ZCD
VO_SNS
COMP
MULTIN
CS
UCC28051
CBULK
1
2
3
4
8
7
6
5
STATUS
OVP
VDD
OUT
SS
FB
CS
GND
UCC28600
CSS
CBP RPL
RSU
RCS
CVDD
Primary Secondary
TL431
Feedback
ROVP2
ROVP1
18 V
CB
NPNS
NB
M1
UCC28600
www.ti.com SLUS646J –NOVEMBER 2005–REVISED JULY 2011
8-Pin Quasi-Resonant Flyback Green-Mode Controller
Check for Samples: UCC28600
1FEATURES APPLICATIONS
2•Green-Mode Controller With Advanced Energy •Bias Supplies for LCD-Monitors, LCD-TV,
Saving Features PDP-TV, and Set Top Boxes
•Quasi-Resonant Mode Operation for Reduced •AC/DC Adapters and Offline Battery Chargers
EMI and Low Switching Losses (Low Voltage •Energy Efficient Power Supplies up to 200 W
Switching)
•Low Standby Current for System No-Load DESCRIPTION
Power Consumption The UCC28600 is a PWM controller with advanced
•Low Startup Current: 25 μA Maximum energy features to meet stringent world-wide energy
efficiency requirements.
•Programmable Overvoltage Protection, Line
and Load UCC28600 integrates built-in advanced energy
•Internal Overtemperature Protection saving features with high level protection features to
•Current Limit Protection provide cost effective solutions for energy efficient
power supplies. UCC28600 incorporates frequency
–Cycle-by-Cycle Power Limit fold back and green mode operation to reduce the
–Primary-Side Overcurrent Hiccup Restart operation frequency at light load and no load
Mode operations.
•1-A Sink TrueDrive™, -0.75-A Source Gate UCC28600 is offered in the 8-pin SOIC (D) package.
Drive Output Operating junction temperature range is -40°C to
•Programmable Soft-Start 105°C.
•Green-Mode Status Pin (PFC Disable Function)
.
.
TYPICAL APPLICATION
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2TrueDrive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2005–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

UCC28600
SLUS646J –NOVEMBER 2005–REVISED JULY 2011 www.ti.com
DESCRIPTION (CONT.)
The Design Calculator, (Texas Instruments Literature number SLVC104), located in the Tools and Software
section of the UCC28600 product folder, provides a user-interactive iterative process for selecting recommended
component values for an optimal design.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UCC28600 UNIT
VDD Supply voltage range IDD <20 mA 32 V
IDD Supply current 20 mA
IOUT(sink) Output sink current (peak) 1.2 A
IOUT(source) Output source current (peak) -0.8
Analog inputs FB, CS, SS -0.3 to 6.0 V
VOVP -1.0 to 6.0
IOVP(source) -1.0 mA
VSTATUS VDD = 0 V to 30 V 30 V
Power dissipation SOIC-8 package, TA= 25°C 650 mW
TJOperating junction temperature range –55 to 150
Tstg Storage temperature –65 to 150 °C
TLEAD Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the databook
for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VDD Input voltage 21 V
IOUT Output sink current 0 A
TJOperating junction temperature -40 105 °C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX UNIT
Human body model 2000 V
CDM 1500
2Copyright ©2005–2011, Texas Instruments Incorporated

UCC28600
www.ti.com SLUS646J –NOVEMBER 2005–REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ωresistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA= -40°C to 105°C,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overall
ISTARTUP Startup current VDD = VUVLO -0.3 V 12 25 μA
ISTANDBY Standby current VFB = 0 V 350 550
Not switching 2.5 3.5
IDD Operating current mA
130 kHz, QR mode 5.0 7.0
VDD clamp FB = GND, IDD = 10 mA 21 26 32 V
Undervoltage Lockout
VDD(uvlo) Startup threshold 10.3 13.0 15.3
Stop threshold 6.3 8 9.3 V
ΔVDD(uvlo) Hysteresis 4.0 5.0 6.0
PWM (Ramp)(1)
DMIN Minimum duty cycle VSS = GND, VFB = 2 V 0%
DMAX Maximum duty cycle QR mode, fS= max, (open loop) 99%
Oscillator (OSC)
fQR(max) Maximum QR and DCM frequency 117 130 143
fQR(min) Minimum QR and FFM frequency VFB = 1.3 V 32 40 48 kHz
fSS Soft start frequency VSS = 2.0 V 32 40 48
dTS/dFB VCO gain TSfor 1.6 V <VFB <1.8 V -38 -30 -22 μs/V
Feedback (FB)
RFB Feedback pullup resistor 12 20 28 kΩ
VFB FB, no load QR mode 3.30 4.87 6.00
Green-mode ON threshold VFB threshold 0.3 0.5 0.7
Green-mode OFF threshold VFB threshold 1.2 1.4 1.6
Green-mode hysteresis VFB threshold 0.7 0.9 1.1 V
FB threshold burst-ON VFB during green mode 0.3 0.5 0.7
FB threshold burst-OFF VFB during green mode 0.5 0.7 0.9
Burst Hysteresis VFB during green mode 0.13 0.25 0.42
Status
RDS(on) STATUS on resistance VSTATUS = 1 V 1.0 2.4 3.8 kΩ
ISTATUS(leakage) STATUS leakage/off current VFB = 0.44 V, VSTATUS = 15 V -0.1 2.0 μA
(1) RSCT and CCST are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
Copyright ©2005–2011, Texas Instruments Incorporated 3

UCC28600
SLUS646J –NOVEMBER 2005–REVISED JULY 2011 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ωresistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA= -40°C to 105°C,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Sense (CS)(2)
ACS(FB) Gain, FB = ΔVFB /ΔVCS QR mode 2.5 V/V
Shutdown threshold VFB = 2.4 V, VSS = 0 V 1.13 1.25 1.38 V
CS to output delay time (power limit) CS = 1.0 VPULSE 100 175 300 ns
CS to output delay time (over current CS = 1.45 VPULSE 50 100 150
fault)
CS discharge impedance CS = 0.1 V, VSS = 0 V 25 115 250 Ω
VCS(os) CS offset SS mode, VSS ≤2.0 V, via FB 0.35 0.40 0.45 V
Power Limit (PL)(2)
IPL(cs) CS current OVP = -300 μA -165 -150 -135 μA
CS working range QR mode, peak CS voltage 0.70 0.81 0.92 V
VPL PL threshold Peak CS voltage + CS offset 1.05 1.20 1.37
Soft Start (SS)
ISS(chg) Softstart charge current VSS = GND -8.3 -6.0 -4.5 μA
ISS(dis) Softstart discharge current VSS = 0.5 V 2.0 5.0 10 mA
VSS Switching ON threshold Output switching start 0.8 1.0 1.2 V
Overvoltage Protection (OVP)
IOVP(line) Line overvoltage protection IOVP threshold, OUT = HI -512 -450 -370 μA
VFB = 4.8 V, VSS = 5.0 V, IOVP(on), = -300
VOVP(on) OVP voltage at OUT = HIGH -125 -25 mV
μA
VOVP(load) Load overvoltage protection VOVP threshold, OUT = LO 3.37 3.75 4.13 V
Thermal Protection (TSP)
Thermal shutdown (TSP) temperature(3) 130 140 150 °C
Thermal shutdown hysteresis 15
OUT
tRISE Rise time 10% to 90% of 13 V typical out clamp 50 75 ns
tFALL Fall time 10 20
(2) RSCT and CCST are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
(3) Ensured by design. Not production tested.
4Copyright ©2005–2011, Texas Instruments Incorporated

STATUS
GND
VFB
VCS
VOVP
VOUT
VDD
IDD
IOVP
ROVP
500 Ω
COUT
1.0 nF
ROUT
10 Ω
CBIAS 1 µF
CDD 100 nF
ICS
CFB
47 pF
CSS
3.3 nF
CCST
560 pF
See Note
RCST
37.4 kΩ
See Note SS
VDD
GND OUT
FB
CS
OVP
STATUS
UCC28600
+
1
2
3
4 5
6
7
8
5 V
2
1
6
5.0
VREF
SS
VDD
4GND
5OUT
FB
1.5R
8
3
CS
UVLO +
CBULK
Feedback 20 kW
CSS
7
OVP
On-Chip
Thermal
Shutdown
REF
26 V
R
STATUS
13/8 V
RCS
ROVP1
ROVP2
CVDD
+
400 mV
REF
RSU
+Q
Q
SET
CLR
D
REF
GAIN = 1/2.5
+
Modulation
Comparison
UCC28600
Fault Logic
LINE_OVP
LOAD_OVP
REF_OK
RUN
UVLO
CS
OVR_T
STATUS
SS_DIS
GREEN MODE
FB_CLAMP
OSC_CL
FB
QR DETECT
LOAD_OVP
LINE_OVP
QR_DONE
____
OUT
CS
OSCILLATOR
QR_DONE
CLK
RUN
SS_OVR
OSC_CL
RPL
PL
1.2 V
SS_OVR BURST BURST
RVDD
VDD
UCC28600
www.ti.com SLUS646J –NOVEMBER 2005–REVISED JULY 2011
OPEN LOOP TEST CIRCUIT
NOTE
RCST and CCST are not connected for maximum and minimum duty cycle tests, current
sense tests and power limit tests.
BLOCK DIAGRAM/TYPICAL APPLICATION
Copyright ©2005–2011, Texas Instruments Incorporated 5

1
2
3
4
8
7
6
5
SS
FB
CS
GND
STATUS
OVP
VDD
OUT
UCC28600
D PACKAGE
(TOP VIEW)
UCC28600
SLUS646J –NOVEMBER 2005–REVISED JULY 2011 www.ti.com
ORDERING INFORMATION
TAPACKAGES PART NUMBER
-40°C to 105°C SOIC (D)(1) UCC28600D
(1) SOIC (D) package is available taped and reeled by adding “R”to the above part numbers. Reeled quantities for UCC28600DR is 2,500
devices per reel.
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
Current sense input. Also programs power limit, and used to control modulation and activate overcurrent
CS 3 I protection. The CS voltage input originates across a current sense resistor and ground. Power limit is
programmed with an effective series resistance between this pin and the current sense resistor.
Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current
in the power MOSFET. An internal 20-kΩresistor is between this pin and the internal 5-V regulated voltage.
FB 2 I Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the emitter
of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the three
modes: quasi resonant (QR), frequency foldback mode (FFM) and green mode (GM).
Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the
GND 4 - capacitor as close to these two pins as possible.
1-A sink (TrueDrive™) and 0.75-A source gate drive output. This output drives the power MOSFET and
OUT 5 O switches between GND and the lower of VDD or the 13-V internal output clamp.
Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on.
OVP 7 I Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity
with resistors connected to this pin.
Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the
capacitance and the internal soft-start charge current. Placement of the soft-start capacitor is critical and should
SS 1 I be placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge
the SS pin to GND through an internal MOSFET with an RDS(on) of approximately 100 Ω. The internal modulator
comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit.
ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to
STATUS 8 O disable the PFC control circuit (high impedance = green mode). STATUS pin is high during UVLO, (VDD <
startup threshold), and softstart, (SS <FB).
Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD
VDD 6 I pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To
prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.
6Copyright ©2005–2011, Texas Instruments Incorporated

RCS +ǒVPL *VCS(os)ǓǒICS(2) *ICS(1)Ǔ
ICS(2)IP(1) *ICS(1)IP(2)
RPL +ǒVPL *VCS(os)ǓǒIP(2) *IP(1)Ǔ
ICS(1)IP(2) *ICS(2)IP(1)
ROVP1 +1
IOVP(line)ǒNB
NPVBULK(ov)Ǔ
ROVP2 +ROVP1
ȧ
ȧ
ȡ
Ȣ
VOVP(load)
NB
NSǒVOUT(shutdown) )VFǓ*VOVP(load)
ȧ
ȧ
ȣ
Ȥ
UCC28600
www.ti.com SLUS646J –NOVEMBER 2005–REVISED JULY 2011
TERMINAL COMPONENTS
TERMINAL I/O DESCRIPTION(1) (2) (3)
NAME NO.
(1)
CS 3 I
where:
•IP1 is the peak primary current at low line, full load (3)
•IP2 is the peak primary current at high line, full load(3)
•ICS1 is the power limit current that is sourced at the CS pin at low-line voltage(3)
•ICS2 is the power limit current that is sourced at the CS pin at high-line voltage(3)
•VPL is the Power Limit (PL) threshold(2)
•VCS(os) is the CS offset voltage(2)
FB 2 I Opto-isolator collector
GND 4 - Bypass capacitor to VDD, CBP = 0.1 μF
OUT 5 O Power MOSFET gate
OVP 7 I where:
•IOVP(line) is OVPline current threshold(2)
•VBULK(ov) is the allowed input over- voltage level (3)
•VOVP(load) is OVPload (2)
•VOUT(shutdown) is the allowed output over-voltage level(3)
•VFis the forward voltage of the secondary rectifier
•NBis the number of turns on the bias winding(3)
•NSis the number of turns on the secondary windings(3)
•NPis the number of turns on the primary windings(3)
(1) Refer to Figure 1 for all reference designators in the Terminal Components Table.
(2) Refer to the Electrical Characteristics Table for constant parameters.
(3) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
Copyright ©2005–2011, Texas Instruments Incorporated 7

CSS uISS tSS(min)(due power limit)
ACS(FB) ǒVPL *VCS(os)Ǔ
tSS(min) +ȧ
ȧ
ȱ
Ȳ
*RLOAD(ss)COUT
2ȏn
ȧ
ȡ
Ȣ
1*ǒVOUT *DVOUT(step)Ǔ2
RLOAD(ss)POUT(max)limitȧ
ȣ
Ȥ
ȧ
ȧ
ȳ
ȴ
tSS(min) +ȧ
ȱ
Ȳ
COUTVOUT2
2 PLIM ȧ
ȳ
ȴ
RST2 +VBE(off)
ISTATUS(leakage)
RST1 +
RST2 ƪVDD(uvlo*on) *VBE(sat) *RDS(on) ǒICC
bsatǓƫ*RDS(on)VBE(sat)
ǒǒICC
bsatǓ RST2Ǔ)VBE(sat)
UCC28600
SLUS646J –NOVEMBER 2005–REVISED JULY 2011 www.ti.com
TERMINAL COMPONENTS (continued)
TERMINAL I/O DESCRIPTION(1) (2) (3)
NAME NO.
where tSS(min) is the greater of:
or
SS 1 I
(2)
•RLOAD(ss) is the effective load impedance during soft-start(4)
• ΔVOUT(step) is the allowed change in VOUT due to a load step(4)
•POUT(max limit) Programmed power limit level, in W (4)
•ACS(FB) is the current sense gain(5)
•VCS(os) is the CS offset voltage(5)
•ISS is the soft-start charging current(5)
•VPL is the power limit threshold(5)
STATUS 8 O
where:
• βSAT is the gain of transistor QST in saturation
•VBE(sat) is the base-emitter voltage of transistor QST in saturation
•VDD(uvlo-on) is the startup threshold(5)
•ICC is the collector current of QST
•ISTATUS(leakage) is the maximum leakage/off current of the STATUS pin(5)
•VBE(off) is the maximum allowable voltage across the base emitter junction that will not turn QST on
•RDS(on) is the RDS(on) of STATUS(5)
(4) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
(5) Refer to the Electrical Characteristics Table for constant parameters.
8Copyright ©2005–2011, Texas Instruments Incorporated

CVDD +ƪǒIDD )CISSVOUT(hi)fQR(max)ǓTBURST
DVDD(burst)ƫ
CVDD +ƪǒIDD )CISSVOUT(hi)fQR(max)ǓtSS
DVDD(uvlo)ƫ
RVDD +ǒp
4ǓǒNB
NPǓȧ
ȡ
Ȣ
ǒVDS1(os) fQR(max) LLEAKAGEǒCD)CSNUBǓ
Ǹ
IDD )CISS VOUT(hi) fQR(max) ȧ
ȣ
Ȥ
RSU +VBULK(min)
ISTARTUP
UCC28600
www.ti.com SLUS646J –NOVEMBER 2005–REVISED JULY 2011
TERMINAL COMPONENTS (continued)
TERMINAL I/O DESCRIPTION(1) (2) (3)
NAME NO.
CVDD is the greater of:
or
(3)
VDD 6 I
where:
•IDD is the operating current of the UCC28600(6)
•CISS is the input capacitance of MOSFET M1
•VOUT(hi) is VOH of the OUT pin, either 13 V (typ) VOUT clamp or less as measured
•fQR(max) is fSat high line, maximum load(6)
•TBURST is the measured burst mode period
• ΔVDD(burst) is the allowed VDD ripple during burst mode
• ΔVDD(uvlo) is the UVLO hysteresis(6)
•VDS1(os) is the amount of drain-source overshoot voltage
•LLEAKAGE is the leakage inductance of the primary winding
•CDis the total drain node capacitance of MOSFET M1
•ISTARTUP is IDD start-up current of the UCC28600(6)
•CSNUB is the snubber capacitor value
•tSS is the soft start charge time(7)
(6) Refer to the Electrical Characteristics Table for constant parameters.
(7) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
Copyright ©2005–2011, Texas Instruments Incorporated 9

CBULK
FEEDBACK
CSS
RCS
ROVP1
ROVP2
CVDD
D1
RSU
RPL
TL431
2
1
6
SS
VDD
4 GND 5OUT
FB
8
3 CS
7OVP
STATUS
UCC28600
CBP
100nF
RST2
RST1
COUT
PRIMARY SECONDARY
N1
NB
N2VOUT
+
-
+
-
VBULK
ICC
RVDD
QST
ROUT
RSNUB CSNUB
M1
PFC OUTPUT
or
BRIDGE RECTIFIER
PFC CONTROLLER BIAS
(if used)
CBIAS
D2
UCC28600
SLUS646J –NOVEMBER 2005–REVISED JULY 2011 www.ti.com
Figure 1. Pin Termination Schematic
10 Copyright ©2005–2011, Texas Instruments Incorporated