Texas Instruments TMS320x281 series User manual

TMS320x281x
Enhanced Controller Area Network (eCAN)
Reference Guide
Literature Number: SPRU074FMay 2002 – Revised January 2009

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Contents
Preface ............................................................................................................................... 7
1 Architecture ............................................................................................................... 91.1 CAN Overview .............................................................................................................. 101.1.1 Features ............................................................................................................ 101.1.2 Block Diagram ..................................................................................................... 111.1.3 eCAN Compatibility With Other TI CAN Modules ............................................................. 111.2 The CAN Network and Module ........................................................................................... 121.2.1 CAN Protocol Overview .......................................................................................... 121.3 eCAN Controller Overview ................................................................................................ 131.3.1 Standard CAN Controller (SCC) Mode ......................................................................... 141.3.2 Memory Map ....................................................................................................... 151.3.3 eCAN Control and Status Registers ............................................................................ 181.4 Message Objects ........................................................................................................... 191.5 Message Mailbox ........................................................................................................... 191.5.1 Transmit Mailbox .................................................................................................. 231.5.2 Receive Mailbox ................................................................................................... 241.5.3 CAN Module Operation in Normal Configuration.............................................................. 24
2 eCAN Registers ........................................................................................................ 252.1 Mailbox Enable Register (CANME) ...................................................................................... 262.2 Mailbox-Direction Register (CANMD) .................................................................................... 272.3 Transmission-Request Set Register (CANTRS) ....................................................................... 282.4 Transmission-Request-Reset Register (CANTRR) .................................................................... 292.5 Transmission-Acknowledge Register (CANTA) ........................................................................ 302.6 Abort-Acknowledge Register (CANAA) .................................................................................. 312.7 Received-Message-Pending Register (CANRMP) ..................................................................... 322.8 Received-Message-Lost Register (CANRML) .......................................................................... 332.9 Remote-Frame-Pending Register (CANRFP) .......................................................................... 342.9.1 Handling of Remote Frames ..................................................................................... 342.10 Global Acceptance Mask Register (CANGAM)......................................................................... 362.11 Master Control Register (CANMC) ....................................................................................... 372.11.1 CAN Module Action in SUSPEND ............................................................................. 392.12 Bit-Timing Configuration Register (CANBTC) .......................................................................... 402.13 Error and Status Register (CANES) ..................................................................................... 422.14 CAN Error Counter Registers (CANTEC/CANREC) ................................................................... 442.15 Interrupt Registers.......................................................................................................... 452.15.1 Global Interrupt Flag Registers (CANGIF0/CANGIF1) ...................................................... 452.15.2 Global Interrupt Mask Register (CANGIM) .................................................................... 482.15.3 Mailbox Interrupt Mask Register (CANMIM) .................................................................. 502.15.4 Mailbox Interrupt Level Register (CANMIL) ................................................................... 512.16 Overwrite Protection Control Register (CANOPC) ..................................................................... 522.17 eCAN I/O Control Registers (CANTIOC, CANRIOC) .................................................................. 53
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2.18 Timer Management Unit ................................................................................................... 552.18.1 Time Stamp Functions ........................................................................................... 552.18.2 Time-Out Functions .............................................................................................. 582.18.3 Behavior/Usage of MTOF0/1 Bit in User Applications....................................................... 602.19 Mailbox Layout .............................................................................................................. 612.19.1 Message Identifier Register (MSGID) ......................................................................... 612.19.2 CPU Mailbox Access ............................................................................................ 622.19.3 Message-Control Register (MSGCTRL)....................................................................... 632.19.4 Message Data Registers (CANMDL, CANMDH) ............................................................. 642.20 Acceptance Filter ........................................................................................................... 652.20.1 Local-Acceptance Masks (CANLAM) .......................................................................... 65
3 eCAN Configuration .................................................................................................. 673.1 CAN Module Initialization.................................................................................................. 683.1.1 CAN Bit-Timing Configuration ................................................................................... 693.1.2 CAN Bit Rate Calculation ........................................................................................ 693.1.3 Bit Configuration Parameters for 150-MHz CAN Clock ...................................................... 703.1.4 Bit Configuration Parameters for 100-MHz CAN Clock ...................................................... 713.1.5 EALLOW Protection ............................................................................................... 723.2 Steps to Configure eCAN ................................................................................................. 723.2.1 Configuring a Mailbox for Transmit ............................................................................. 733.2.2 Transmitting a Message .......................................................................................... 733.2.3 Configuring Mailboxes for Receive.............................................................................. 733.2.4 Receiving a Message ............................................................................................. 743.2.5 Handling of Overload Situations ................................................................................. 743.3 Handling of Remote Frame Mailboxes .................................................................................. 743.3.1 Requesting Data From Another Node .......................................................................... 743.3.2 Answering a Remote Request ................................................................................... 753.3.3 Updating the Data Field .......................................................................................... 753.4 Interrupts .................................................................................................................... 753.4.1 Interrupts Scheme ................................................................................................. 773.4.2 Mailbox Interrupt ................................................................................................... 773.4.3 Interrupt Handling ................................................................................................. 783.5 CAN Power-Down Mode .................................................................................................. 803.5.1 Entering and Exiting Local Power-Down Mode ............................................................... 803.5.2 Precautions for Entering and Exiting Device Low-Power Modes (LPM) ................................... 803.5.3 Enabling/Disabling Clock to the CAN Module ................................................................. 813.5.4 Possible Failure Modes External to the CAN Controller Module ............................................ 81
A Revision History ....................................................................................................... 83
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List of Figures
1-1 eCAN Block Diagram and Interface Circuit ............................................................................. 111-2 CAN Data Frame ........................................................................................................... 121-3 Architecture of the eCAN Module ........................................................................................ 131-4 eCAN-A Memory Map ..................................................................................................... 161-5 eCAN-B Memory Map ..................................................................................................... 172-1 Mailbox-Enable Register (CANME) ...................................................................................... 262-2 Mailbox-Direction Register (CANMD) .................................................................................... 272-3 Transmission-Request Set Register (CANTRS) ....................................................................... 282-4 Transmission-Request-Reset Register (CANTRR) .................................................................... 292-5 Transmission-Acknowledge Register (CANTA) ........................................................................ 302-6 Abort-Acknowledge Register (CANAA) .................................................................................. 312-7 Received-Message-Pending Register (CANRMP) ..................................................................... 322-8 Received-Message-Lost Register (CANRML) .......................................................................... 332-9 Remote-Frame-Pending Register (CANRFP) .......................................................................... 342-10 Global Acceptance Mask Register (CANGAM)......................................................................... 362-11 Master Control Register (CANMC) ....................................................................................... 372-12 Bit-Timing Configuration Register (CANBTC) .......................................................................... 402-13 Error and Status Register (CANES) ..................................................................................... 422-14 Transmit-Error-Counter Register (CANTEC) ........................................................................... 442-15 Receive-Error-Counter Register (CANREC) ............................................................................ 442-16 Global Interrupt Flag 0 Register (CANGIF0) ............................................................................ 462-17 Global Interrupt Flag 1 Register (CANGIF1) ............................................................................ 462-18 Global Interrupt Mask Register (CANGIM) .............................................................................. 482-19 Mailbox Interrupt Mask Register (CANMIM) ............................................................................ 502-20 Mailbox Interrupt Level Register (CANMIL) ............................................................................. 512-21 Overwrite Protection Control Register (CANOPC) ..................................................................... 522-22 TX I/O Control Register (CANTIOC) ..................................................................................... 532-23 RX I/O Control Register (CANRIOC) .................................................................................... 542-24 Time-Stamp Counter Register (CANTSC) .............................................................................. 562-25 Message Object Time Stamp Registers (MOTS) ...................................................................... 572-26 Message-Object Time-Out Registers (MOTO) ......................................................................... 582-27 Time-Out Control Register (CANTOC) .................................................................................. 592-28 Time-Out Status Register (CANTOS) ................................................................................... 602-29 Message Identifier Register (MSGID) Register......................................................................... 612-30 Message-Control Register (MSGCTRL) ................................................................................. 632-31 Message-Data-Low Register With DBO = 0 (CANMDL) .............................................................. 642-32 Message-Data-High Register With DBO = 0 (CANMDH) ............................................................. 642-33 Message-Data-Low Register With DBO = 1 (CANMDL) .............................................................. 642-34 Message-Data-High Register With DBO = 1 (CANMDH) ............................................................. 642-35 Local-Acceptance-Mask Register (LAM n).............................................................................. 663-1 Initialization Sequence ..................................................................................................... 683-2 CAN Bit Timing ............................................................................................................. 693-3 Interrupts Scheme .......................................................................................................... 76
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List of Tables
1-1 Register Map ................................................................................................................ 181-2 eCAN-A Mailbox RAM Layout ............................................................................................ 201-3 Addresses of LAM, MOTS and MOTO registers for mailboxes (eCAN-A) ......................................... 211-4 eCAN-B Mailbox Ram Layout ............................................................................................ 221-5 Addresses of LAM, MOTS, and MOTO Registers for Mailboxes (eCAN-B) ........................................ 231-6 Message Object Behavior Configuration ................................................................................ 232-1 Mailbox-Enable Register (CANME) Field Descriptions ................................................................ 262-2 Mailbox-Direction Register (CANMD) Field Descriptions ............................................................. 272-3 Transmission-Request Set Register (CANTRS) Field Descriptions ................................................. 282-4 Transmission-Request-Reset Register (CANTRR) Field Descriptions .............................................. 292-5 Transmission-Acknowledge Register (CANTA) Field Descriptions .................................................. 302-6 Abort-Acknowledge Register (CANAA) Field Descriptions ........................................................... 312-7 Received-Message-Pending Register (CANRMP) Field Descriptions .............................................. 322-8 Received-Message-Lost Register (CANRML) Field Descriptions.................................................... 332-9 Remote-Frame-Pending Register (CANRFP) Field Descriptions .................................................... 342-10 Global Acceptance Mask Register (CANGAM) Field Descriptions .................................................. 362-11 Master Control Register (CANMC) Field Descriptions ................................................................ 372-12 Bit-Timing Configuration Register (CANBTC) Field Descriptions .................................................... 402-13 Error and Status Register (CANES) Field Descriptions ............................................................... 422-14 Global Interrupt Flag Registers (CANGIF0/CANGIF1) Field Descriptions .......................................... 472-15 Global Interrupt Mask Register (CANGIM) Field Descriptions ....................................................... 482-16 Mailbox Interrupt Mask Register (CANMIM) Field Descriptions ...................................................... 502-17 Mailbox Interrupt Level Register (CANMIL) Field Descriptions ...................................................... 512-18 Overwrite Protection Control Register (CANOPC) Field Descriptions .............................................. 522-19 TX I/O Control Register (CANTIOC) Field Descriptions .............................................................. 532-20 RX I/O Control Register (CANRIOC) Field Descriptions .............................................................. 542-21 Time-Stamp Counter Register (CANTSC) Field Descriptions ........................................................ 562-22 Message Object Time Stamp Registers (MOTS) Field Descriptions ................................................ 572-23 Message-Object Time-Out Registers (MOTO) Field Descriptions ................................................... 582-24 Time-Out Control Register (CANTOC) Field Descriptions ............................................................ 592-25 Time-Out Status Register (CANTOS) Field Descriptions ............................................................. 602-26 Message Identifier Register (MSGID) Field Descriptions ............................................................. 612-27 Message-Control Register (MSGCTRL) Field Descriptions .......................................................... 632-28 Local-Acceptance-Mask Register (LAM n) Field Descriptions ........................................................ 663-1 BRP Field for Bit Rates (BT = 15, TSEG1
reg
= 10, TSEG2
reg
= 2, Sampling Point = 80%) ...................... 703-2 Achieving Different Sampling Points With a BT of 15 ................................................................. 703-3 BRP Field for Bit Rates (BT = 10, TSEG1
reg
= 6, TSEG2
reg
= 1, Sampling Point = 80%) ........................ 703-4 BRP Field for Bit Rates (BT = 10, TSEG1
reg
= 6, TSEG2
reg
= 1, Sampling Point = 80%) ........................ 713-5 Achieving Different Sampling Points With a BT of 20 ................................................................. 713-6 BRP Field for Bit Rates .................................................................................................... 713-7 eCAN Interrupt Assertion/Clearing ....................................................................................... 78A-1 Changes Made in This Revision ......................................................................................... 83
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PrefaceSPRU074F – May 2002 – Revised January 2009
Read This First
About This Manual
This document describes the enhanced controller area network (eCAN) on the x281x device.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the x281x device and related peripherals. Copies of these documentsare available for downloading at www.ti.com .
CPU User's Guides—SPRU430— TMS320C28x DSP CPU and Instruction Set Reference Guide describes the centralprocessing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-pointdigital signal processors (DSPs). It also describes emulation features available on these DSPs.
SPRU078— TMS320x281x System Control and Interrupts Reference Guide describes the variousinterrupts and system control features of the 281x digital signal processors (DSPs).
Peripheral Guides—SPRU566— TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral referenceguides of the 28x digital signal processors (DSPs).
SPRU060— TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide describes the ADCmodule, which is a 12-bit pipelined ADC. The analog circuits of this converter, referred to as thecore in this document, include the front-end analog multiplexers (MUXs), sample-and-hold (S/H)circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digitalcircuits, referred to as the wrapper in this document, include programmable conversion sequencer,result registers, interface to analog circuits, interface to device peripheral bus, and interface to otheron-chip modules.
SPRU065— TMS320x281x Event Manager (EV) Reference Guide describes the EV modules that providea broad range of functions and features that are particularly useful in motion control and motorcontrol applications. The EV modules include general-purpose (GP) timers, full-compare/pulsewidth modulator (PWM) units, capture units, and quadrature-encoder pulse (QEP) circuits.
SPRU074— TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide describesthe eCAN that uses established protocol to communicate serially with other controllers in electricallynoisy environments.
SPRU051— TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes theSCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modulessupport digital communications between the CPU and other asynchronous peripherals that use thestandard non-return-to-zero (NRZ) format.
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Related Documentation From Texas Instruments www.ti.com
SPRU059— TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI -a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream ofprogrammed length (one to sixteen bits) to be shifted into and out of the device at a programmedbit-transfer rate.
SPRU061— TMS320x281x Multi-channel Buffered Serial Ports (McBSPs) Reference Guide describes theMcBSP available on the C28x devices. The McBSPs allow direct interface between a DSP andother devices in a system.
SPRU067— TMS320x281x External Interface (XINTF) Reference Guide describes the external interface(XINTF) of the 281x digital signal processors (DSPs).
SPRU095— TMS320x281x Boot ROM Reference Guide describes the purpose and features of thebootloader (factory-programmed boot-loading software). It also describes other contents of thedevice on-chip boot ROM and identifies where all of the information is located within that memory.
Tools Guides—
SPRU513— TMS320C28x Assembly Language Tools User's Guide describes the assembly languagetools (assembler and other tools used to develop assembly language code), assembler directives,macros, common object file format, and symbolic debugging directives for the TMS320C28x device.
SPRU514— TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSPassembly language source code for the TMS320C28x device.
SPRU608— The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instructionset of the C28x™ core.
SPRU625— TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guidedescribes development using DSP/BIOS.
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Chapter 1SPRU074F – May 2002 – Revised January 2009
Architecture
The enhanced Controller Area Network (eCAN) module implemented in the C28x™ DSP is a full-CANcontroller and is compatible with the CAN 2.0B standard (active). It uses established protocol tocommunicate serially with other controllers in electrically noisy environments. With 32 fully configurablemailboxes and time–stamping feature, the eCAN module provides a versatile and robust serialcommunication interface.
The eCAN module described in this reference guide is a Type 0 eCAN. Refer to theTMS320x28xx, 28xxxDSP Peripheral Reference Guide (SPRU566 ) for a list of other devices with a eCAN module of the sametype, to determine the differences between types, and for a list of device-specific differences within a type.Some devices have a second CAN module, eCAN-B. The word eCAN is generically used to refer to theCAN modules. The specific module reference (A or B) is used where appropriate. For a given CANmodule, the same address space is used for the module registers in all 28xx /28xxx devices.
Topic .................................................................................................. Page
1.1 CAN Overview .......................................................................... 101.2 The CAN Network and Module .................................................... 121.3 eCAN Controller Overview ......................................................... 131.4 Message Objects....................................................................... 191.5 Message Mailbox ...................................................................... 19
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1.1 CAN Overview
1.1.1 Features
CAN Overview www.ti.com
Figure 1–1 shows the major blocks of the eCAN and the interface circuits.
The eCAN module has the following features:•Fully compliant with CAN protocol, version 2.0B•Supports data rates up to 1 Mbps•Thirty-two mailboxes, each with the following properties:– Configurable as receive or transmit– Configurable with standard or extended identifier– Has a programmable acceptance filter mask– Supports data and remote frame– Supports 0 to 8 bytes of data– Uses a 32-bit time stamp on received and transmitted message– Protects against reception of new message– Allows dynamically programmable priority of transmit message– Employs a programmable interrupt scheme with two interrupt levels– Employs a programmable interrupt on transmission or reception time-out•Low–power mode•Programmable wake–up on bus activity•Automatic reply to a remote request message•Automatic retransmission of a frame in case of loss of arbitration or error•32-bit time-stamp counter synchronized by a specific message (communication in conjunction withmailbox 16)•Self–test mode– Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided,thereby eliminating the need for another node to provide the acknowledge bit.
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1.1.2 Block Diagram
32−Message
Mailbox RAM
4 X 32−Bit Words
for each mailbox)
Memory Management
Unit
CPU Interface,
Receive Control Unit,
Timer Management Unit
Control and status
registers
32 32
Message Controller
32 3232 3232 32
Enhanced CAN Controller 32
Controls Address Data ECAN1INTECAN0INT
8
SN65HVD23x
3.3−V CAN Transceiver
CAN Bus
Communication
fersA buf
1.1.3 eCAN Compatibility With Other TI CAN Modules
www.ti.com CAN Overview
Figure 1-1. eCAN Block Diagram and Interface Circuit
A The communication buffers are transparent to the user and are not accessible by user code.
The eCAN module is identical to the “High-end CAN Controller (HECC)” used in the TMS470™ seriesmicrocontrollers from Texas Instruments with some minor changes. The eCAN module features severalenhancements (such as increased number of mailboxes with individual acceptance masks, time stamping,etc.) over the CAN module featured in 240x™ series of DSPs. For this reason, code written for 240x CANmodules cannot be directly ported to eCAN. However, eCAN follows the same register bit-layout structureand bit functionality as that of 240x CAN (for registers that exist in both devices) i.e., many registers andbits perform exactly identical functions across these two platforms. This makes code migration a relativelyeasy task, more so with code written in C language.
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1.2 The CAN Network and Module
1.2.1 CAN Protocol Overview
Bit length 112 or 32
Start bit
Arbitration field which contains:
60-8 bytes
Data field
Control bits
16
CRC bits
7
End
2
Acknowledge
– 11-bit identifier + RTR bit for standard frame format
– 29-bit identifier + SRR bit + IDE bit + RTR bit for extended frame format
Where: RTR = RemoteTransmission Request
SRR = Substitute Remote Request
IDE = Identifier Extension
Note: Unless otherwise noted, numbers are amount of bits in field.
The CAN Network and Module www.ti.com
The controller area network (CAN) uses a serial multimaster communication protocol that efficientlysupports distributed real-time control, with a very high level of security, and a communication rate of up to1 Mbps. The CAN bus is ideal for applications operating in noisy and harsh environments, such as in theautomotive and other industrial fields that require reliable communication.
Prioritized messages of up to eight bytes in data length can be sent on a multimaster serial bus using anarbitration protocol and an error-detection mechanism for a high level of data integrity.
The CAN protocol supports four different frame types for communication:•Data frames that carry data from a transmitter node to the receiver nodes•Remote frames that are transmitted by a node to request the transmission of a data frame with thesame identifier•Error frames that are transmitted by any node on a bus-error detection•Overload frames that provide an extra delay between the preceding and the succeeding data frames orremote frames.
In addition, CAN specification version 2.0B defines two different formats that differ in the length of theidentifier field: standard frames with an 11-bit identifier and extended frames with 29-bit identifier.
CAN standard data frames contain from 44 to 108 bits and CAN extended data frames contain 64 to 128bits. Furthermore, up to 23 stuff bits can be inserted in a standard data frame, and up to 28 stuff bits in anextended data frame, depending on the data-stream coding. The overall maximum data frame length isthen 131 bits for a standard frame and 156 bits for an extended frame.
The bit fields that make up standard/extended data frames, along with their position as shown inFigure 1-2 include the following:•Start of frame•Arbitration field containing the identifier and the type of message being sent•Control field indicating the number of bytes being transmitted.•Up to 8 bytes of data•Cyclic redundancy check (CRC)•Acknowledgment
•End-of-frame bits
Figure 1-2. CAN Data Frame
The eCAN controller provides the CPU with full functionality of the CAN protocol, version 2.0B. The CANcontroller minimizes the CPU’s load in communication overhead and enhances the CAN standard byproviding additional features.
The architecture of eCAN module, shown in Figure 1-3 , is composed of a CAN protocol kernel (CPK) anda message controller.
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CAN Bus
CAN controller
Message Controller
CAN Protocol Kernel (CPK)
CAN Transceiver
RX TX
CPU
Receive BufferATransmit BufferA
1.3 eCAN Controller Overview
www.ti.com eCAN Controller Overview
Figure 1-3. Architecture of the eCAN Module
A The receive and transmit buffers are transparent to the user and are not accessible by user code.
Two functions of the CPK are to decode all messages received on the CAN bus according to the CANprotocol and to transfer these messages into a receive buffer. Another CPK function is to transmitmessages on the CAN bus according to the CAN protocol.
The message controller of a CAN controller is responsible for determining if any message received by theCPK must be preserved for the CPU use or be discarded. At the initialization phase, the CPU specifies tothe message controller all message identifiers used by the application. The message controller is alsoresponsible for sending the next message to transmit to the CPK according to the message’s priority.
The eCAN is a CAN controller with an internal 32-bit architecture.
The eCAN module consists of:•The CAN protocol kernel (CPK)•The message controller comprising:– The memory management unit (MMU), including the CPU interface and the receive control unit(acceptance filtering), and the timer management unit– Mailbox RAM enabling the storage of 32 messages– Control and status registers
After the reception of a valid message by the CPK, the receive control unit of the message controllerdetermines if the received message must be stored into one of the 32 message objects of the mailboxRAM. The receive control unit checks the state, the identifier, and the mask of all message objects todetermine the appropriate mailbox location. The received message is stored into the first mailbox passingthe acceptance filtering. If the receive control unit could not find any mailbox to store the receivedmessage, the message is discarded.
A message is composed of an 11- or 29-bit identifier, a control field, and up to 8 bytes of data.
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1.3.1 Standard CAN Controller (SCC) Mode
eCAN Controller Overview www.ti.com
When a message must be transmitted, the message controller transfers the message into the transmitbuffer of the CPK in order to start the message transmission at the next bus-idle state. When more thanone message must be transmitted, the message with the highest priority that is ready to be transmitted istransferred into the CPK by the message controller. If two mailboxes have the same priority, then themailbox with the higher number is transmitted first.
The timer management unit comprises a time-stamp counter and apposes a time stamp to all messagesreceived or transmitted. It generates an interrupt when a message has not been received or transmittedduring an allowed period of time (time-out). The time-stamping feature is available in eCAN mode only.
To initiate a data transfer, the transmission request bit (TRS.n) has to be set in the corresponding controlregister. The entire transmission procedure and possible error handling are then performed without anyCPU involvement. If a mailbox has been configured to receive messages, the CPU easily reads its dataregisters using CPU read instructions. The mailbox may be configured to interrupt the CPU after everysuccessful message transmission or reception.
The SCC Mode is a reduced functionality mode of the eCAN. Only 16 mailboxes (0 through 15) areavailable in this mode. The time stamping feature is not available and the number of acceptance masksavailable is reduced. This mode is selected by default. The SCC mode or the full featured eCAN mode isselected using the SCB bit (CANMC.13).
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1.3.2 Memory Map
1.3.2.1 32-bit Access to Control and Status Registers
www.ti.com eCAN Controller Overview
The eCAN module has two different address segments mapped in the memory. The first segment is usedto access the control registers, the status registers, the acceptance masks, the time stamp, and thetime-out of the message objects. The access to the control and status registers is limited to 32-bit wideaccesses. The local acceptance masks, the time stamp registers, and the time-out registers can beaccessed 8-bit, 16-bit and 32-bit wide. The second address segment is used to access the mailboxes.This memory range can be accessed 8-bit, 16-bit and 32-bit wide. Each of these two memory blocks,shown in Figure 1-4 , uses 512 bytes of address space.
The message storage is implemented by a RAM that can be addressed by the CAN controller or the CPU.The CPU controls the CAN controller by modifying the various mailboxes in the RAM or the additionalregisters. The contents of the various storage elements are used to perform the functions of theacceptance filtering, message transmission, and interrupt handling.
The mailbox module in the eCAN provides 32 message mailboxes of 8-byte data length, a 29-bit identifier,and several control bits. Each mailbox can be configured as either transmit or receive. In the eCAN mode,each mailbox has its individual acceptance mask.
Note: LAMn, MOTSn and MOTOn registers and mailboxes not used in an application (disabled inthe CANME register) may be used as general-purpose data memory by the CPU.
As indicated in Section 1.3.2 , only 32-bit accesses are allowed to the Control and Status registers. 16-bitaccess to these registers could potentially corrupt the register contents or return false data. The DSPheader files released by TI employs a shadow register structure that aids in 32-bit access. Following are afew examples of how the shadow register structure may be employed to perform 32-bit reads/writes:
Example 1-1. Modifying a bit in a register
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; // Step 1ECanaShadow.CANTIOC.bit.TXFUNC = 1; // Step 2ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; // Step 3
Step 1: Perform a 32-bit read to copy the entire register to its shadow
Step 2: Modify the needed bit(s) in the shadow
Step 3: Perform a 32-bit write to copy the modified shadow to the original register.
Note: Some bits like TAn and RMPn are cleared by writing a 1 to it. Care should be taken not toclear bits inadvertently.
Example 1-2. Checking the value of a bit in a register
do
{
ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;}while(ECanaShadow.CANTA.bit.TA25 == 0); // Wait for TA5 bit to be set..
In the above example, the value of TA25 bit needs to be checked. This is done by first copying the entireCANTA register to its shadow (using a 32-bit read) and then checking the relevant bit, repeating thisoperation until that condition is satisfied. TA25 bit should NOT be checked with the following statement:while(ECanaRegs.CANTA.bit.TA25 == 0);
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Global Acceptance Mask − CANGAM
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Master Control − CANMC
Bit−Timing Configuration − CANBTC
Error and Status − CANES
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time−Stamp Counter − CANTSC
Global Interrupt Flag 1 − CANGIF1
Time−Out Control − CANTOC
Time−Out Status − CANTOS
Reserved
eCAN−A Control and Status Registers
Message Identifier − MSGID (32 bits)
61E8h−61E9h Message Control − MSGCTRL (32 bits)
Message Data Low − CANMDL (4 bytes)
Message Data High − CANMDH (4 bytes)
Message Mailbox (16 Bytes)
Control and Status Registers
6000h
603Fh
Local Acceptance Masks (LAM)
(32 ×32−Bit RAM)
6040h
607Fh
6080h
60BFh
60C0h
60FFh
eCAN−A Registers (512 Bytes)
Message Object Time Stamps (MOTS)
(32 ×32−Bit RAM)
Message Object Time−Out (MOTO)
(32 ×32−Bit RAM)
Mailbox 0
6100h−6107h Mailbox 1
6108h−610Fh Mailbox 2
6110h−6117h Mailbox 3
6118h−611Fh
eCAN−A Mailbox RAM (512 Bytes)
Mailbox 4
6120h−6127h
Mailbox 28
61E0h−61E7h Mailbox 29
61E8h−61EFh Mailbox 30
61F0h−61F7h Mailbox 31
61F8h−61FFh
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
eCAN Controller Overview www.ti.com
Figure 1-4. eCAN-A Memory Map
Architecture 16 SPRU074F – May 2002 – Revised January 2009Submit Documentation Feedback

Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
Bit−Timing Configuration − CANBTC
Error and Status − CANES
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Global Interrupt Flag 1 − CANGIF1
Time−Out Control − CANTOC
Time−Out Status − CANTOS
Reserved
eCAN−B Control and Status Registers
Message Identifier − MSGID63E8h−63E9h Message Control − MSGCTRL
Message Data Low − CANMDL
Message Data High − CANMDH
Message Mailbox (16 Bytes)
Control and Status Registers
6200h
623Fh
Local Acceptance Masks (LAM)
(32 ×32−Bit RAM)
6240h
627Fh
6280h
62BFh
62C0h
62FFh
eCAN−B Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32 ×32−Bit RAM)
Message Object Time−Out (MOTO)
(32 ×32−Bit RAM)
Mailbox 0
6300h−6307h Mailbox 1
6308h−630Fh Mailbox 2
6310h−6317h Mailbox 3
6318h−631Fh
eCAN−B Memory RAM (512 Bytes)
Mailbox 4
6320h−6327h
Mailbox 28
63E0h−63E7h Mailbox 29
63E8h−63EFh Mailbox 30
63F0h−63F7h Mailbox 31
63F8h−63FFh
63EAh−63EBh
63ECh−63EDh
63EEh−63EFh
www.ti.com eCAN Controller Overview
Figure 1-5. eCAN-B Memory Map
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1.3.3 eCAN Control and Status Registers
eCAN Controller Overview www.ti.com
The eCAN registers listed in Table 1-1 are used by the CPU to configure and control the CAN controllerand the message objects.
Table 1-1. Register Map
REGISTER NAME
(1)
ECAN-A ECAN-B SIZE DESCRIPTION
ADDRESS ADDRESS (x32)
CANME 0x6000 0x6200 1 Mailbox enableCANMD 0x6002 0x6202 1 Mailbox directionCANTRS 0x6004 0x6204 1 Transmit request setCANTRR 0x6006 0x6206 1 Transmit request resetCANTA 0x6008 0x6208 1 Transmission acknowledgeCANAA 0x600A 0x620A 1 Abort acknowledgeCANRMP 0x600C 0x620C 1 Receive message pendingCANRML 0x600E 0x620E 1 Receive message lostCANRFP 0x6010 0x6210 1 Remote frame pendingCANGAM 0x6012 0x6212 1 Global acceptance maskCANMC 0x6014 0x6214 1 Master controlCANBTC 0x6016 0x6216 1 Bit-timing configurationCANES 0x6018 0x6218 1 Error and statusCANTEC 0x601A 0x621A 1 Transmit error counterCANREC 0x601C 0x621C 1 Receive error counterCANGIF0 0x601E 0x621E 1 Global interrupt flag 0CANGIM 0x6020 0x6220 1 Global interrupt maskCANGIF1 0x6022 0x6222 1 Global interrupt flag 1CANMIM 0x6024 0x6224 1 Mailbox interrupt maskCANMIL 0x6026 0x6226 1 Mailbox interrupt levelCANOPC 0x6028 0x6228 1 Overwrite protection controlCANTIOC 0x602A 0x622A 1 TX I/O controlCANRIOC 0x602C 0x622C 1 RX I/O controlCANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode)CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode)CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)
(1)
These registers are mapped to Peripheral Frame 1.
Note: Only 32-bit accesses are allowed to the control and status registers. This restriction does notapply to the mailbox RAM area. See Section 1.3.2.1 for more information.
18 Architecture SPRU074F – May 2002 – Revised January 2009Submit Documentation Feedback

1.4 Message Objects
1.5 Message Mailbox
www.ti.com Message Objects
The eCAN module has 32 different message objects (mailboxes).
Each message object can be configured to either transmit or receive. Each message object has itsindividual acceptance mask.
A message object consists of a message mailbox with:•The 29-bit message identifier•The message control register•8 bytes of message data•A 29-bit acceptance mask•A 32-bit time stamp•A 32-bit time-out value
Furthermore, corresponding control and status bits located in the registers allow control of the messageobjects.
The message mailboxes are the RAM area where the CAN messages are actually stored after they arereceived or before they are transmitted.
The CPU may use the RAM area of the message mailboxes that are not used for storing messages asnormal memory.
Each mailbox contains:•The message identifier– 29 bits for extended identifier– 11 bits for standard identifier•The identifier extension bit, IDE (MSGID.31)•The acceptance mask enable bit, AME (MSGID.30)•The auto answer mode bit, AAM (MSGID.29)•The transmit priority level, TPL (MSGCTRL.12-8)•The remote transmission request bit, RTR (MSGCTRL.4)•The data length code, DLC (MSGCTRL.3-0)•Up to eight bytes for the data field
Each of the mailboxes can be configured as one of four message object types (see Table 1-5 ). Transmitand receive message objects are used for data exchange between one sender and multiple receivers (1 ton communication link), whereas request and reply message objects are used to set up a one-to-onecommunication link. Table 1-2 lists the mailbox RAM layout.
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Message Mailbox www.ti.com
Table 1-2. eCAN-A Mailbox RAM Layout
Mailbox MSGID MSGCTRL CANMDL CANMDHMSGIDL-MSGIDH MSGCTRL-Rsvd CANMDL_L- CANMDL_H CANMDH_L- CANMDH_H
0 6100-6101h 6102-6103h 6104-6105h 6106-6107h1 6108-6109h 610A-610Bh 610C-610Dh 610E-610Fh2 6110 - 6111h 6112-6113h 6114-6115h 6116-6117h3 6118-6119h 611A-611Bh 611C-611Dh 611E-611Fh4 6120-6121h 6122-6123h 6124-6125h 6126-6127h5 6128-6129h 612A-612Bh 612C-612Dh 612E-612Fh6 6130-6131h 6132-6133h 6134-6135h 6136-6137h7 6138-6139h 613A-613Bh 613C-613Dh 613E-613Fh8 6140-6141h 6142-6143h 6144-6145h 6146-6147h9 6148-6149h 614A-614Bh 614C-614Dh 614E-614Fh10 6150-6151h 6152-6153h 6154-6155h 6156-6157h11 6158-6159h 615A-615Bh 615C-615Dh 615E-615Fh12 6160-6161h 6162-6163h 6164-6165h 6166-6167h13 6168-6169h 616A-616Bh 616C-616Dh 616E-616Fh14 6170-6171h 6172-6173h 6174-6175h 6176-6177h15 6178-6179h 617A-617Bh 617C-617Dh 617E-617Fh16 6180-6181h 6182-6183h 6184-6185h 6186-6187h17 6188-6189h 618A-618Bh 618C-618Dh 618E-618Fh18 6190-6191h 6192-6193h 6194-6195h 6196-6197h19 6198-6199h 619A-619Bh 619C-619Dh 619E-619Fh20 61A0-61A1h 61A2-61A3h 61A4-61A5h 61A6-61A7h21 61A8-61A9h 61AA-61ABh 61AC-61ADh 61AE-61AFh22 61B0-61B1h 61B2-61B3h 61B4-61B5h 61B6-61B7h23 61B8-61B9h 61BA-61BBh 61BC-61BDh 61BE-61BFh24 61C0-61C1h 61C2-61C3h 61C4-61C5h 61C6-61C7h25 61C8-61C9h 61CA-61CBh 61CC-61CDh 61CE-61CFh26 61D0-61D1h 61D2-61D3h 61D4-61D5h 61D6-61D7h27 61D8-61D9h 61DA-61DBh 61DC-61DDh 61DE-61DFh28 61E0-61E1h 61E2-61E3h 61E4-61E5h 61E6-61E7h29 61E8-61E9h 61EA-61EBh 61EC-61EDh 61EE-61EFh30 61F0-61F1h 61F2-61F3h 61F4-61F5h 61F6-61F7h31 61F8-61F9h 61FA-61FBh 61FC-61FDh 61FE-61FFh
Architecture 20 SPRU074F – May 2002 – Revised January 2009Submit Documentation Feedback