Texas Instruments TPS70351EVM User manual

TPS70351EVM
Lo ĆDropout, DualĆOutput Linear Regulator EVM
For Using the TPS70351
October 2000 POWER MANAGEMENT PRODUCTS
User’s Guide
SLVU036

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Copyright 2000, Texas Instruments Incorporated

iii
Read This First
Preface
About This Manual
This user’s guide describes the TPS70351EVM low-dropout, dual-output
evaluation module (SLVP165). The SLVP165 provides a convenient method
for evaluating the performance of a dual-output linear regulator.
How to Use This Manual
- Chapter 1 Introduction
- Chapter 2 EVM Adjustments and Test Points
- Chapter 3 Circuit Design
- Chapter 4 Test Results
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.

Related Documentation From Texas Instruments
iv
Related Documentation From Texas Instruments
- TPS70351 data sheets (literature number SLVS285)
Trademarks
PowerPAD is a trademark of Texas Instruments.

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1-2. . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Design Strategy 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Schematic 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Bill of Materials 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Board Layout 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 EVM Adjustments and Test Points 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Adjustment by Switch and Jumpers 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Adjustment Through Component Changes 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Test Setup 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Design 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 ESR and Transient Response 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Test Results 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Test Results 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
1–1 Typical LDO Application 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 SLVP165B EVM Universal LDO Tester Schematic Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . .
1–3 Top Layer 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 Bottom Layer (top view) 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 Assembly Drawing (top assembly) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Test Setup 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 ESR and ESL 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 LDO Output Stage With Parasitic Resistances ESR 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Correlation of Different ESRs and Their Influence to the Regulation of VOat a
Load Step From Low-to-High Output Current 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 VOUT1 Load Transient 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 VOUT2 Load Transient 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Timing When SEQUENCE Is High 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Timing When SEQUENCE Is Low 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Timing Including RESET 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Timing When SEQUENCE Is Low, With a Fault on VOUT1 4-4. . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Timing When SEQUENCE Is High, With a Fault on VOUT1 4-5. . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Timing When SEQUENCE Is Low, With a Fault on VOUT2 4-5. . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Timing When SEQUENCE Is High, With a Fault on VOUT2 4-6. . . . . . . . . . . . . . . . . . . . . . . . .
4–10 Timing When MR Is Toggled 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 Summary of the TPS703xx LDO Family Features 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 SLVP165B EVM Bill of Materials 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Jumper Functions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Commonly Changed Components 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Timing Equations 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Regulator Loading Options 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Introduction
This user’s guide describes the TPS70351EVM165 low-dropout, dual-output
evaluationmodule(SLVP165B).LDOsprovideidealpowersuppliesforrapidly
transitioning DSP loads. The TPS703xx family of devices is designed to
provide a complete power management solution for DSP, processor power,
ASIC,FPGA,anddigitalapplicationswheredualoutputvoltageregulatorsare
required. Easy programmability of the sequencing function makes this family
ideal for any DSP applications with a power sequencing requirement.
Differentiated features, such as SVS supervisory circuit, manual reset inputs,
and enable function, provide a complete system solution. Moreover, with its
low-quiescent current, low-dropout voltage, low-output noise, high PSRR,
fast-transient response, and high accuracy compared to standard LDOs, the
TPS703xxprovidesan ideal solutionwhere standard linearregulators are too
inefficient or too slow and where a switch converter solution or the source
power supply is too noisy.
Topic Page
1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1–2. . . . . . . . .
1.2 Design Strategy 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Schematic 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Bill of Materials 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Board Layout 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Low Dropout Voltage Linear Regulator Circuit Operation
1-2
Introduction
1.1 Low Dropout Voltage Linear Regulator Circuit Operation
InTI’slowdropoutvoltagelinearregulatortopology,aPMOStransistorisused
for the pass element. Because the PMOS device behaves as a low-value
resistor,thedropoutvoltageisverylowandisdirectlyproportionaltotheoutput
current.Additionally,sincethePMOSpasselementisavoltage-drivendevice,
the quiescent current is very low and independent of output loading.
The basic LDO regulator circuit includes the LDO and an output capacitor for
stabilization. Figure 1–1 shows the circuit of a typical LDO application.
Figure 1–1.Typical LDO Application
_
+
Control
_
+
R1
R2
Q1
Vref
LDO
Co
VO
Load
_
+
VCC
In the LDO application shown in Figure 1–1, the LDO regulates the output
voltage VO.
If VOfalls below the regulation level, the controller increases the VSG
differential and the PMOS transistor conducts more current, resulting in an
increaseinVO.IfVOexceedstheregulationlevel,thecontrollerdecreasesthe
VSG differential and the PMOS transistor conducts less current, resulting in a
decreaseinVO.ThePMOSpasselementactslikeanadjustableresistor.The
morenegative the gatebecomes versus thesource, the lessthe source-drain
resistance becomes, resulting in higher current flow through the PMOS.

Design Strategy
1-3
Introduction
1.2 Design Strategy
The TI SLVP165B EVM provides a convenient method for evaluating the
performance of TPS703xx dual-output linear regulators. The EVM provides
proven, demonstrated reference designs and test modes to aid in evaluation.
Theboardcontainsapowersupplyalongwithanonboardtransientgenerator.
The transient slew rate can be modified by changing two resistors. Jumpers
allow settings of minimum/maximum load as well as device-enabling and
power sequencing. There is enough room on the EVM to evaluate different
typesofoutputcapacitorsincludingESRbehaviors.Manytestpointsallowthe
measuring of input, output, and dropout voltage.
The EVM contains a TPS70351. Regulator 1 provides an output voltage of
3.3 V and a maximum output current of 1 A. Regulator 2 provides an output
voltage of 1.8 V and a maximum output current of 2 A.
Table 1–1 summarizes the TPS703xx family’s features. See the TPS703xx
datasheet,TIliteraturenumberSLVS285
, forafurtherexplanationoffeatures.
Table 1–1.Summary of the TPS703xx LDO Family Features
Description TPS703xx Feature
Maximum input voltage [V] 6
Maximum output current [A] 1/2
Typical quiescent current [µA] 185
Typical dropout voltage [mV] 160
Typical output noise [µVrms]
(30 Hz ≤f ≤50 kHz, Co= 33 µF) 79/77
Accuracy over line, load, and temperature 2%
PSRR (at 1 kHz, Co= 10 µF, TJ= 25°C) 65/60 dB
Package 24 pin TSSOP with PowerPAD
Minimum output capacitor > 47 µF (ceramic)
Available voltage option [V] 3.3/1.5, 3.3/1.2, 3.3/1.8, 3.3/2.5, and adj/adj
Performance advantage Dual output LDO, power-up sequencing, DSP application,
PG and RESET
PowerPAD is a trademark of Texas Instruments.

Schematic
1-4
Introduction
1.3 Schematic
Figure1–2 shows the SLVP165 EVM schematic diagram.
Figure 1–2.SLVP165B EVM Universal LDO Tester Schematic Diagram
Off
7DISCH 6THRES 2TRIG 8 1GND 4RESET 3
OUT
5
CTL
D1
DL4148
J2
C6
+C3
JP7
C10
1000 pF
TP9
11 12 GND/HS
5MR2 6MR1 7ENABLE
3 2
21 22 23 24
GND/HS
1GND/HS 8SEQUENCE 9GND
10
4NC
18
RESET
20
NC
15 16 17
NC
19
PGD
PwrPad 14
OUT2 13
GND/HS
TPS70351PWP
R15
R5 10
R7 10
3GND 1
21IN 42IN
8
REG
6
5
2OUT
7
1OUT Q1
Si4410
Si4410
Q2
C11
1000 pF
DL4148
D2
DL4148
D3
R6 510
R8 510
C5
+C2
R9
TP6
TP4
TP3
TP5
TP8
TP7
JP1
R4
D4
Green
TP11 TP12
TP13
TP10
R12
TP17
C14
+
C12
R11
0
D5 RED
J3
TP14
TP16
R10
R24
R23
R21
R20
JP6 JP5
JP13
JP14
JP9
JP12
JP8
JP11
R19
R18
R17
R16
JP10
C13
R13
0
R14
C15
TP15
JP15
JP16
GND GND
J1 1
2 3
4
100 µF0.1 µF
TP1 VIN1
Sense
PGDGND
10 kΩ
100 µF0.1 µF
TP2
Sense
JP2
JP3
GND VIN
JP4
GND
1 2
C4
0.1 µF
R1
4.3 kΩ
R2
10 kΩ
C1
1µF
On
ENABLE
S1
R3
5.1 kΩ
U1
TLC555D C7
0.1 µF
TP18
U2
TPS2812
C8
10 µF
0.1 µF
C9
U3
IMBD4148
D6
2 kΩ2 kΩ
33µF0.1 µF
33 kΩ
Sense
Sense
1.8 kΩ
+
47µF0.1 µF
4 3 2 1
GND GND
Load 1
R22
VOUT2 V
OUT1
VOUT1 V
IN1
VIN1 V
IN2
VIN2 V
SENSE1
V
SENSE2
V
OUT2
V
OUT1
V
OUT1
V
OUT2
V
IN2
V
IN1
V
IN2
V
CC
V
CC
VCC
V
DD
V

Bill of Materials
1-5
Introduction
1.4 Bill of Materials
Table 1–2 lists materials required for the SLVP165 EVM.
Table 1–2.SLVP165B EVM Bill of Materials
Ref Des Qty Part Number Description MFG Size
C1 1 ECJ-2VF1C105Z Capacitor, ceramic, 1.0 uF, 16 V,
80% – 20%, Y5V Panasonic 805
C2 – 3 2 TPSD107M010R100 Capacitor, tantalum, 100 µF, 10 V,
100-mΩ, 20% AVX D Size
C4 – 7, 9,
14, 15 7 GRM39X7R104K016A Capacitor, ceramic, 0.1 uF, 16 V, 10%, X7R Murata 603
C8 1 GRM235Y5V106Z016A Capacitor, ceramic, 10 µF, 16 V,
80%–20%, Y5 V TDK 1210
C10, 11 2 GRM39X7R102K050A Capacitor, ceramic, 1000 pF, 50 V,
10%, X7R Murata 603
C12 1 10TPA33M Capacitor, POSCAP, 33 µF, 10 V,
20% Sanyo C Size
C13 1 6TPA47M Capacitor, POSCAP, 47 µF, 10 V,
20% Sanyo C Size
D1 – 3 3 1N4148 Diode, signal, 75 V, 300 mA Diodes, Inc. SOT–23
D4 1 SML-LX2832GC-TR Diode. LED, green, 2.1 V, 25 mcd,
SM Lumex 1210
D5 1 SML-LX2832RC-TR Diode. LED, red, 1.7 V, 40 mcd, SM Lumex 1210
D6 1 IMBD4148 Diode, switching, 10 mA, 100 V,
350 mW Vishay-Liteon SOT–23
J1, 3 2 ED1516 Terminal block, 4-pin, 6-A, 3.5 mm OST
J2 1 ED1514 Terminal block, 2-pin, 6A, 3.5 mm OST
JP1, 4 2 PTC36SAAN Header, 3-pin, 100 mil spacing
(36 pin strip) Sullins
JP2, 3,
5 – 16 14 PTC36SAAN Header, 2-pin, 100 mil spacing (36 pin strip) Sullins
Q1, 2 2 Si4410DY MOSFET, N-ch, 30 V, 10 A, 13 mΩSiliconix SO8
R1 1 Std Resistor, chip, 4.3 kΩ, 1/16W, 5% 603
R2, 4 2 Std Resistor, chip, 10 kΩ, 1/16W, 5% 603
R3 1 Std Resistor, chip, 5.1 kΩ, 1/16W, 5% 603
R5, 7 2 Std Resistor, chip, 10 Ω, 1/16W, 5% 603
R6, 8 2 Std Resistor, chip, 510 Ω, 1/16W, 5% 603
R9, 10 2 Std Resistor, chip, 2.0 kΩ, 1/16W, 5% 603
R11, 13 2 Std Resistor, chip, 0 Ω, 1/16W, 5% 603
R12 1 Std Resistor, chip, 3.3 kΩ, 1/16W, 5% 603
R14 1 Std Resistor, chip, 1.8 kΩ, 1/16W, 5% 603

Bill of Materials
1-6
Introduction
Table 1–2. SLVP165B EVM Bill of Materials (Continued)
Ref Des Qty Part Number Description MFG Size
R15 – 19
R15A – 19A 10 ERJ–1WYJ33OU Resistor, chip, 33 Ω, 1 W, 5% Panasonic 2512
R20 – 24
R20A – 24A 10 ERJ–1WY100U Resistor, chip, 10 Ω, 1 W, 5% Panasonic 2512
S1 1 EG1218 Switch, 1P2T, slide, PC-mount,
200 mA E–Switch
TP1, 2, 16,
17 4 131–4244–00 Adaptor, 3.5-mm probe clip (or 131–5031–00) Tektronix
TP3 – 15,
18 14 240–345 Test point, red, 1 mm Farnell
U1 1 TLC555D IC, timer, low-power, CMOS TI SO8
U2 1 TPS2812D IC, MOSFET driver, dual channel
buffer w/regulator TI SO8
U3 1 TPS70351PWP IC, dual 1–A/2–A LDO regulator, TI PWP24
–– 1SLVP165, Rev. B PCB, 2-layer, 2-oz,
3.49”(L) x 2.94”(W) x 0.062”(T)

Board Layout
1-7
Introduction
1.5 Board Layout
Figures 1–3 through 1-5 show the board layout for the SLVP165B EVM.
Figure 1–3.Top Layer
Top Layer
Figure 1–4.Bottom Layer (top view)
Bottom Layer

Board Layout
1-8
Introduction
Figure 1–5.Assembly Drawing (top assembly)
Top Assembly

2-1
EVM Adjustments and Test Points
EVM Adjustments and Test Points
This chapter explains the following EVM adjustment modes:
- Adjustment by switch and jumper
- Adjustment through changing components
Figure 2–1 shows the locations of the adjustment points on the board.
Topic Page
2.1 Adjustment by Switch and Jumpers 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Adjustment Through Component Changes 2–3. . . . . . . . . . . . . . . . . . . . . .
2.3 Test Setup 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

Adjustment by Switch and Jumpers
2-2
EVM Adjustments and Test Points
2.1 Adjustment by Switch and Jumpers
S1 switches the transient generator on or off. Table 2–1 lists adjustments that
can be made by jumpers.
Table 2–1.Jumper Functions
Jumper Setting Functional Description
JP1 Short 1-2 – MR2 tied to GND RESET follows MR2
Short 2-3 – MR2 tied to PG_1 RESET will go high after a 120 ms delay when
VOUT2 reaches 95% of its regulated voltage
and when PG_1 goes high due to VOUT1
reaching 95% of its regulated voltage.
Open MR2 is disabled
JP2 Shorted – MR1 tied to GND RESET follows MR1
Open MR1 is disabled
JP3 Shorted – EN tied to GND Enable device outputs
Open Disable device outputs
JP4 Short 1-2 – SEQ tied to GND SEQ low – regulator 1 powers up first with regu-
lator 2 powering up when VOUT1 is 83% of max
output voltage.
Short 2-3 – SEQ tied to VIN SEQ high or left open – regulator 2 powers up
first with regulator 1 powering up when VOUT2 is
83% of max output voltage
JP5 Shorted – bypass transient generator
for regulator 1 Allows continuous load through onboard load resistors on regulator 1.
Open – engage transient generator
for regulator 1 Allows pulsed load through onboard load resis- tors on regulator 1.
JP6 Shorted – bypass transient generator
for regulator 2 Allows continuous load through onboard load resistors on regulator 2.
Open – engage transient generator
for regulator 2 Allows pulsed load through onboard load resis- tors on regulator 2.
JP7 – JP11 Shorted – include resistor in parallel
combination Increase regulator 1 load from no load to max load.
Open – remove resistor from parallel
combination Decrease regulator 1 load from max load to no load.
JP12 – JP16 Shorted – include resistor in parallel
combination Increase regulator 2 load from no load to max load.
Open – remove resistor from parallel
combination Decrease regulator 2 load from max load to no load.
TheTPS703xxdatasheet, TILiteraturenumberSLVS285,providesfurtherex-
planationofalternativeconfigurationsusingtheSVSsupervisory circuit, pow-
er good, manual reset, and enable inputs.

Adjustment Through Component Changes
2-3
EVM Adjustments and Test Points
2.2 Adjustment Through Component Changes
Through minor soldering work, the onboard device can be changed to any of
thefixed-voltagemembersoftheTPS703xxLDOfamily. Inaddition,Table2–2
summarizes the most common components which a user might wish to re-
place in order to more fully characterize the LDO.
Table 2–2.Commonly Changed Components
Component Regulator 1 Regulator 2 EVM Value
Input capacitor C2 C3 100 µF
Output capacitor C12 C13 33 µF, 47 µF
Resistors controlling transient pulse generator pulse width and
duty cycle (see Table 2-3) R1, R2 R1, R2 4.3 kΩ,
10 kΩ
Resistor controlling load transient rise time†R6 R8 510 Ω
†Larger resistance slows rise time.
Table 2–3 gives the equations for computing the resistor sizes necessary for
changing the transient pulse width and/or duty cycle.
Table 2–3.Timing Equations
Timing Equations With Diode D1 for
Low Duty Cycles Timing Equations Without Diode D1
R 1 +
t
on
0.693 CR
1 +
t
on
(2
D * 1)
0.693
D C
R 2 +
t
on
(1
* D
)
0.693
D CR
2 +
t
on
(1
* D
)
0.693
D C
Note: ton = desired load on-time [s]
D = on-time duty cycle
C = total capacitance in circuit (1 uF)
RH1, RH2 = Timer resistors value (refer to schematics) [Ω]
2.3 Test Setup Figure 2–1 shows the test setup. Follow these steps for initial power up of the
SLVP165:
1) Adjust the settings of jumpers to fit test requirements (see jumper func-
tionsinTable 2-1). Verifythattheswitchcontrolling the load transientgen-
eratorisoff,noexternalloadisconnectedthroughJ3andthatJP5andJP6
are open to prevent loading through the onboard resistors.
2) Connecta12-VlabpowersupplytotheVCC inputandGNDatJ2.Thepo-
larityisprintedontheboard.Acurrentlimit of100mAshouldbe adequate
for the test and measure circuit.
3) Connect a second lab power supply (at least capable of supplying 2 A) to
the J1 connector at VIN1, VIN2, GND1 and GND2. The polarity is printed
on the board. Verify that the lab power supply output voltage limit is set to
6 V and that the output is set to 0 V.
4) Turn on the 12-V lab supply. Turn on the second power supply and ramp
the input voltage up to the desired maximum but not higher than 6 V.

Test Setup
2-4
EVM Adjustments and Test Points
5) Verifythattheoutput voltage(measuredattheVOUT1 andVOUT2pinsre-
spectively) has the desired value.
6) Table2–4showsthethreerecommendedoptionsforloadingeachregula-
tor.
Table 2–4.Regulator Loading Options
Type JP5–Regulator 1
JP6–Regulator 2 SW_1 External Load
Continuous load off-board Open Off Connected
Continuous load onboard Shorted On/off Not connected
Pulsed load onboard Open On Not connected
Jumpers JP7 – JP11 and JP12 – JP16 vary the current through the onboard
resistorsfrom0tomaxloadcurrentforregulator1andregulator2respectively.
Simultaneous and continuous operation of both regulator outputs at full
load may exceed the power dissipation rating of the PWP package. For
more information, refer to the thermal information section in the
TPS703xx data sheet (literature number SLVS285).
Figure 2–1.Test Setup
+
–
Power Supply
5–V, 5–A Supply
Note: All wire pairs should be twisted.
Load
0 – 1A
Test Set–Up
+
–
Power Supply
12–V, 0.5–A Supply
Load
0 – 2A

3-1
Circuit Design
Circuit Design
This chapter describes the LDO circuit design procedure.
Topic Page
3.1 ESR and Transient Response 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3

ESR and Transient Response
3-2
Circuit Design
3.1 ESR and Transient Response
LDOstypicallyrequireanexternaloutputcapacitorforstability.Infasttransient
response applications, capacitors are used to support the load current while
the LDO amplifier is responding. In most applications, one capacitor is used
to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances.
Theseimpedancesareresistiveaswellasinductive.Theresistiveimpedance
is called equivalent series resistance (ESR), and the inductive impedance is
calledequivalentseriesinductance(ESL).Theequivalentschematicdiagram
of any capacitor can therefore be drawn as shown in Figure 3–1.
Figure 3–1.ESR and ESL
RESR LESL C
In most cases one can neglect the effect of inductive impedance ESL. There-
fore,thefollowingapplicationfocusesmainlyontheparasiticresistance ESR.
Figure3–2showstheoutputcapacitoranditsparasiticimpedancesinatypical
LDO output stage.
Figure 3–2.LDO Output Stage With Parasitic Resistances ESR
–
LDO
VI
VESR
IO
RESR
CO
RLOAD VO
++
–
In steady state (dc state condition), the load current is supplied by the LDO
(solid arrow) and the voltage across the capacitor is the same as the output
voltage (V(Co) = VO). This means no current is flowing into or out of the Co
branch.
IfIOsuddenlyincreases(transientcondition),theLDOisnotabletosupplythe
suddencurrentneedduetoitsresponsetime(t1inFigure3–3).Therefore,ca-
pacitor Coprovides the current for the new load condition (dashed arrow). Co
now acts like a battery with an internal resistance, RESR. Depending on the
current demand at the output, a voltage drop will occur at RESR. This voltage
is shown as VESR in Figure 3–2.